sunxi_wdt.c 8.2 KB

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  1. /*
  2. * sunxi Watchdog Driver
  3. *
  4. * Copyright (c) 2013 Carlo Caione
  5. * 2012 Henrik Nordstrom
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. *
  12. * Based on xen_wdt.c
  13. * (c) Copyright 2010 Novell, Inc.
  14. */
  15. #include <linux/clk.h>
  16. #include <linux/delay.h>
  17. #include <linux/err.h>
  18. #include <linux/init.h>
  19. #include <linux/io.h>
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/of.h>
  24. #include <linux/of_device.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/types.h>
  27. #include <linux/watchdog.h>
  28. #define WDT_MAX_TIMEOUT 16
  29. #define WDT_MIN_TIMEOUT 1
  30. #define WDT_TIMEOUT_MASK 0x0F
  31. #define WDT_CTRL_RELOAD ((1 << 0) | (0x0a57 << 1))
  32. #define WDT_MODE_EN (1 << 0)
  33. #define DRV_NAME "sunxi-wdt"
  34. #define DRV_VERSION "1.0"
  35. static bool nowayout = WATCHDOG_NOWAYOUT;
  36. static unsigned int timeout = WDT_MAX_TIMEOUT;
  37. /*
  38. * This structure stores the register offsets for different variants
  39. * of Allwinner's watchdog hardware.
  40. */
  41. struct sunxi_wdt_reg {
  42. u8 wdt_ctrl;
  43. u8 wdt_cfg;
  44. u8 wdt_mode;
  45. u8 wdt_timeout_shift;
  46. u8 wdt_reset_mask;
  47. u8 wdt_reset_val;
  48. };
  49. struct sunxi_wdt_dev {
  50. struct watchdog_device wdt_dev;
  51. void __iomem *wdt_base;
  52. const struct sunxi_wdt_reg *wdt_regs;
  53. };
  54. /*
  55. * wdt_timeout_map maps the watchdog timer interval value in seconds to
  56. * the value of the register WDT_MODE at bits .wdt_timeout_shift ~ +3
  57. *
  58. * [timeout seconds] = register value
  59. *
  60. */
  61. static const int wdt_timeout_map[] = {
  62. [1] = 0x1, /* 1s */
  63. [2] = 0x2, /* 2s */
  64. [3] = 0x3, /* 3s */
  65. [4] = 0x4, /* 4s */
  66. [5] = 0x5, /* 5s */
  67. [6] = 0x6, /* 6s */
  68. [8] = 0x7, /* 8s */
  69. [10] = 0x8, /* 10s */
  70. [12] = 0x9, /* 12s */
  71. [14] = 0xA, /* 14s */
  72. [16] = 0xB, /* 16s */
  73. };
  74. static int sunxi_wdt_restart(struct watchdog_device *wdt_dev,
  75. unsigned long action, void *data)
  76. {
  77. struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
  78. void __iomem *wdt_base = sunxi_wdt->wdt_base;
  79. const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
  80. u32 val;
  81. /* Set system reset function */
  82. val = readl(wdt_base + regs->wdt_cfg);
  83. val &= ~(regs->wdt_reset_mask);
  84. val |= regs->wdt_reset_val;
  85. writel(val, wdt_base + regs->wdt_cfg);
  86. /* Set lowest timeout and enable watchdog */
  87. val = readl(wdt_base + regs->wdt_mode);
  88. val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
  89. val |= WDT_MODE_EN;
  90. writel(val, wdt_base + regs->wdt_mode);
  91. /*
  92. * Restart the watchdog. The default (and lowest) interval
  93. * value for the watchdog is 0.5s.
  94. */
  95. writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);
  96. while (1) {
  97. mdelay(5);
  98. val = readl(wdt_base + regs->wdt_mode);
  99. val |= WDT_MODE_EN;
  100. writel(val, wdt_base + regs->wdt_mode);
  101. }
  102. return 0;
  103. }
  104. static int sunxi_wdt_ping(struct watchdog_device *wdt_dev)
  105. {
  106. struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
  107. void __iomem *wdt_base = sunxi_wdt->wdt_base;
  108. const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
  109. writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);
  110. return 0;
  111. }
  112. static int sunxi_wdt_set_timeout(struct watchdog_device *wdt_dev,
  113. unsigned int timeout)
  114. {
  115. struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
  116. void __iomem *wdt_base = sunxi_wdt->wdt_base;
  117. const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
  118. u32 reg;
  119. if (wdt_timeout_map[timeout] == 0)
  120. timeout++;
  121. sunxi_wdt->wdt_dev.timeout = timeout;
  122. reg = readl(wdt_base + regs->wdt_mode);
  123. reg &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
  124. reg |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift;
  125. writel(reg, wdt_base + regs->wdt_mode);
  126. sunxi_wdt_ping(wdt_dev);
  127. return 0;
  128. }
  129. static int sunxi_wdt_stop(struct watchdog_device *wdt_dev)
  130. {
  131. struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
  132. void __iomem *wdt_base = sunxi_wdt->wdt_base;
  133. const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
  134. writel(0, wdt_base + regs->wdt_mode);
  135. return 0;
  136. }
  137. static int sunxi_wdt_start(struct watchdog_device *wdt_dev)
  138. {
  139. u32 reg;
  140. struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
  141. void __iomem *wdt_base = sunxi_wdt->wdt_base;
  142. const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
  143. int ret;
  144. ret = sunxi_wdt_set_timeout(&sunxi_wdt->wdt_dev,
  145. sunxi_wdt->wdt_dev.timeout);
  146. if (ret < 0)
  147. return ret;
  148. /* Set system reset function */
  149. reg = readl(wdt_base + regs->wdt_cfg);
  150. reg &= ~(regs->wdt_reset_mask);
  151. reg |= regs->wdt_reset_val;
  152. writel(reg, wdt_base + regs->wdt_cfg);
  153. /* Enable watchdog */
  154. reg = readl(wdt_base + regs->wdt_mode);
  155. reg |= WDT_MODE_EN;
  156. writel(reg, wdt_base + regs->wdt_mode);
  157. return 0;
  158. }
  159. static const struct watchdog_info sunxi_wdt_info = {
  160. .identity = DRV_NAME,
  161. .options = WDIOF_SETTIMEOUT |
  162. WDIOF_KEEPALIVEPING |
  163. WDIOF_MAGICCLOSE,
  164. };
  165. static const struct watchdog_ops sunxi_wdt_ops = {
  166. .owner = THIS_MODULE,
  167. .start = sunxi_wdt_start,
  168. .stop = sunxi_wdt_stop,
  169. .ping = sunxi_wdt_ping,
  170. .set_timeout = sunxi_wdt_set_timeout,
  171. .restart = sunxi_wdt_restart,
  172. };
  173. static const struct sunxi_wdt_reg sun4i_wdt_reg = {
  174. .wdt_ctrl = 0x00,
  175. .wdt_cfg = 0x04,
  176. .wdt_mode = 0x04,
  177. .wdt_timeout_shift = 3,
  178. .wdt_reset_mask = 0x02,
  179. .wdt_reset_val = 0x02,
  180. };
  181. static const struct sunxi_wdt_reg sun6i_wdt_reg = {
  182. .wdt_ctrl = 0x10,
  183. .wdt_cfg = 0x14,
  184. .wdt_mode = 0x18,
  185. .wdt_timeout_shift = 4,
  186. .wdt_reset_mask = 0x03,
  187. .wdt_reset_val = 0x01,
  188. };
  189. static const struct of_device_id sunxi_wdt_dt_ids[] = {
  190. { .compatible = "allwinner,sun4i-a10-wdt", .data = &sun4i_wdt_reg },
  191. { .compatible = "allwinner,sun6i-a31-wdt", .data = &sun6i_wdt_reg },
  192. { /* sentinel */ }
  193. };
  194. MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
  195. static int sunxi_wdt_probe(struct platform_device *pdev)
  196. {
  197. struct sunxi_wdt_dev *sunxi_wdt;
  198. const struct of_device_id *device;
  199. struct resource *res;
  200. int err;
  201. sunxi_wdt = devm_kzalloc(&pdev->dev, sizeof(*sunxi_wdt), GFP_KERNEL);
  202. if (!sunxi_wdt)
  203. return -EINVAL;
  204. platform_set_drvdata(pdev, sunxi_wdt);
  205. device = of_match_device(sunxi_wdt_dt_ids, &pdev->dev);
  206. if (!device)
  207. return -ENODEV;
  208. sunxi_wdt->wdt_regs = device->data;
  209. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  210. sunxi_wdt->wdt_base = devm_ioremap_resource(&pdev->dev, res);
  211. if (IS_ERR(sunxi_wdt->wdt_base))
  212. return PTR_ERR(sunxi_wdt->wdt_base);
  213. sunxi_wdt->wdt_dev.info = &sunxi_wdt_info;
  214. sunxi_wdt->wdt_dev.ops = &sunxi_wdt_ops;
  215. sunxi_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
  216. sunxi_wdt->wdt_dev.max_timeout = WDT_MAX_TIMEOUT;
  217. sunxi_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
  218. sunxi_wdt->wdt_dev.parent = &pdev->dev;
  219. watchdog_init_timeout(&sunxi_wdt->wdt_dev, timeout, &pdev->dev);
  220. watchdog_set_nowayout(&sunxi_wdt->wdt_dev, nowayout);
  221. watchdog_set_restart_priority(&sunxi_wdt->wdt_dev, 128);
  222. watchdog_set_drvdata(&sunxi_wdt->wdt_dev, sunxi_wdt);
  223. sunxi_wdt_stop(&sunxi_wdt->wdt_dev);
  224. err = watchdog_register_device(&sunxi_wdt->wdt_dev);
  225. if (unlikely(err))
  226. return err;
  227. dev_info(&pdev->dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)",
  228. sunxi_wdt->wdt_dev.timeout, nowayout);
  229. return 0;
  230. }
  231. static int sunxi_wdt_remove(struct platform_device *pdev)
  232. {
  233. struct sunxi_wdt_dev *sunxi_wdt = platform_get_drvdata(pdev);
  234. watchdog_unregister_device(&sunxi_wdt->wdt_dev);
  235. watchdog_set_drvdata(&sunxi_wdt->wdt_dev, NULL);
  236. return 0;
  237. }
  238. static void sunxi_wdt_shutdown(struct platform_device *pdev)
  239. {
  240. struct sunxi_wdt_dev *sunxi_wdt = platform_get_drvdata(pdev);
  241. sunxi_wdt_stop(&sunxi_wdt->wdt_dev);
  242. }
  243. static struct platform_driver sunxi_wdt_driver = {
  244. .probe = sunxi_wdt_probe,
  245. .remove = sunxi_wdt_remove,
  246. .shutdown = sunxi_wdt_shutdown,
  247. .driver = {
  248. .name = DRV_NAME,
  249. .of_match_table = sunxi_wdt_dt_ids,
  250. },
  251. };
  252. module_platform_driver(sunxi_wdt_driver);
  253. module_param(timeout, uint, 0);
  254. MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
  255. module_param(nowayout, bool, 0);
  256. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  257. "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  258. MODULE_LICENSE("GPL");
  259. MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
  260. MODULE_AUTHOR("Henrik Nordstrom <henrik@henriknordstrom.net>");
  261. MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
  262. MODULE_VERSION(DRV_VERSION);