speedo-tegra124.c 4.3 KB

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  1. /*
  2. * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. #include <linux/device.h>
  17. #include <linux/kernel.h>
  18. #include <linux/bug.h>
  19. #include <soc/tegra/fuse.h>
  20. #include "fuse.h"
  21. #define CPU_PROCESS_CORNERS 2
  22. #define GPU_PROCESS_CORNERS 2
  23. #define SOC_PROCESS_CORNERS 2
  24. #define FUSE_CPU_SPEEDO_0 0x14
  25. #define FUSE_CPU_SPEEDO_1 0x2c
  26. #define FUSE_CPU_SPEEDO_2 0x30
  27. #define FUSE_SOC_SPEEDO_0 0x34
  28. #define FUSE_SOC_SPEEDO_1 0x38
  29. #define FUSE_SOC_SPEEDO_2 0x3c
  30. #define FUSE_CPU_IDDQ 0x18
  31. #define FUSE_SOC_IDDQ 0x40
  32. #define FUSE_GPU_IDDQ 0x128
  33. #define FUSE_FT_REV 0x28
  34. enum {
  35. THRESHOLD_INDEX_0,
  36. THRESHOLD_INDEX_1,
  37. THRESHOLD_INDEX_COUNT,
  38. };
  39. static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
  40. {2190, UINT_MAX},
  41. {0, UINT_MAX},
  42. };
  43. static const u32 __initconst gpu_process_speedos[][GPU_PROCESS_CORNERS] = {
  44. {1965, UINT_MAX},
  45. {0, UINT_MAX},
  46. };
  47. static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
  48. {2101, UINT_MAX},
  49. {0, UINT_MAX},
  50. };
  51. static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
  52. int *threshold)
  53. {
  54. int sku = sku_info->sku_id;
  55. /* Assign to default */
  56. sku_info->cpu_speedo_id = 0;
  57. sku_info->soc_speedo_id = 0;
  58. sku_info->gpu_speedo_id = 0;
  59. *threshold = THRESHOLD_INDEX_0;
  60. switch (sku) {
  61. case 0x00: /* Eng sku */
  62. case 0x0F:
  63. case 0x23:
  64. /* Using the default */
  65. break;
  66. case 0x83:
  67. sku_info->cpu_speedo_id = 2;
  68. break;
  69. case 0x1F:
  70. case 0x87:
  71. case 0x27:
  72. sku_info->cpu_speedo_id = 2;
  73. sku_info->soc_speedo_id = 0;
  74. sku_info->gpu_speedo_id = 1;
  75. *threshold = THRESHOLD_INDEX_0;
  76. break;
  77. case 0x81:
  78. case 0x21:
  79. case 0x07:
  80. sku_info->cpu_speedo_id = 1;
  81. sku_info->soc_speedo_id = 1;
  82. sku_info->gpu_speedo_id = 1;
  83. *threshold = THRESHOLD_INDEX_1;
  84. break;
  85. case 0x49:
  86. case 0x4A:
  87. case 0x48:
  88. sku_info->cpu_speedo_id = 4;
  89. sku_info->soc_speedo_id = 2;
  90. sku_info->gpu_speedo_id = 3;
  91. *threshold = THRESHOLD_INDEX_1;
  92. break;
  93. default:
  94. pr_err("Tegra Unknown SKU %d\n", sku);
  95. /* Using the default for the error case */
  96. break;
  97. }
  98. }
  99. void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info)
  100. {
  101. int i, threshold, cpu_speedo_0_value, soc_speedo_0_value;
  102. int cpu_iddq_value, gpu_iddq_value, soc_iddq_value;
  103. BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
  104. THRESHOLD_INDEX_COUNT);
  105. BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=
  106. THRESHOLD_INDEX_COUNT);
  107. BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
  108. THRESHOLD_INDEX_COUNT);
  109. cpu_speedo_0_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
  110. /* GPU Speedo is stored in CPU_SPEEDO_2 */
  111. sku_info->gpu_speedo_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
  112. soc_speedo_0_value = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0);
  113. cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ);
  114. soc_iddq_value = tegra_fuse_read_early(FUSE_SOC_IDDQ);
  115. gpu_iddq_value = tegra_fuse_read_early(FUSE_GPU_IDDQ);
  116. sku_info->cpu_speedo_value = cpu_speedo_0_value;
  117. if (sku_info->cpu_speedo_value == 0) {
  118. pr_warn("Tegra Warning: Speedo value not fused.\n");
  119. WARN_ON(1);
  120. return;
  121. }
  122. rev_sku_to_speedo_ids(sku_info, &threshold);
  123. sku_info->cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ);
  124. for (i = 0; i < GPU_PROCESS_CORNERS; i++)
  125. if (sku_info->gpu_speedo_value <
  126. gpu_process_speedos[threshold][i])
  127. break;
  128. sku_info->gpu_process_id = i;
  129. for (i = 0; i < CPU_PROCESS_CORNERS; i++)
  130. if (sku_info->cpu_speedo_value <
  131. cpu_process_speedos[threshold][i])
  132. break;
  133. sku_info->cpu_process_id = i;
  134. for (i = 0; i < SOC_PROCESS_CORNERS; i++)
  135. if (soc_speedo_0_value <
  136. soc_process_speedos[threshold][i])
  137. break;
  138. sku_info->soc_process_id = i;
  139. pr_debug("Tegra GPU Speedo ID=%d, Speedo Value=%d\n",
  140. sku_info->gpu_speedo_id, sku_info->gpu_speedo_value);
  141. }