qla_os.c 167 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2014 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/moduleparam.h>
  9. #include <linux/vmalloc.h>
  10. #include <linux/delay.h>
  11. #include <linux/kthread.h>
  12. #include <linux/mutex.h>
  13. #include <linux/kobject.h>
  14. #include <linux/slab.h>
  15. #include <scsi/scsi_tcq.h>
  16. #include <scsi/scsicam.h>
  17. #include <scsi/scsi_transport.h>
  18. #include <scsi/scsi_transport_fc.h>
  19. #include "qla_target.h"
  20. /*
  21. * Driver version
  22. */
  23. char qla2x00_version_str[40];
  24. static int apidev_major;
  25. /*
  26. * SRB allocation cache
  27. */
  28. static struct kmem_cache *srb_cachep;
  29. /*
  30. * CT6 CTX allocation cache
  31. */
  32. static struct kmem_cache *ctx_cachep;
  33. /*
  34. * error level for logging
  35. */
  36. int ql_errlev = ql_log_all;
  37. static int ql2xenableclass2;
  38. module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
  39. MODULE_PARM_DESC(ql2xenableclass2,
  40. "Specify if Class 2 operations are supported from the very "
  41. "beginning. Default is 0 - class 2 not supported.");
  42. int ql2xlogintimeout = 20;
  43. module_param(ql2xlogintimeout, int, S_IRUGO);
  44. MODULE_PARM_DESC(ql2xlogintimeout,
  45. "Login timeout value in seconds.");
  46. int qlport_down_retry;
  47. module_param(qlport_down_retry, int, S_IRUGO);
  48. MODULE_PARM_DESC(qlport_down_retry,
  49. "Maximum number of command retries to a port that returns "
  50. "a PORT-DOWN status.");
  51. int ql2xplogiabsentdevice;
  52. module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
  53. MODULE_PARM_DESC(ql2xplogiabsentdevice,
  54. "Option to enable PLOGI to devices that are not present after "
  55. "a Fabric scan. This is needed for several broken switches. "
  56. "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
  57. int ql2xloginretrycount = 0;
  58. module_param(ql2xloginretrycount, int, S_IRUGO);
  59. MODULE_PARM_DESC(ql2xloginretrycount,
  60. "Specify an alternate value for the NVRAM login retry count.");
  61. int ql2xallocfwdump = 1;
  62. module_param(ql2xallocfwdump, int, S_IRUGO);
  63. MODULE_PARM_DESC(ql2xallocfwdump,
  64. "Option to enable allocation of memory for a firmware dump "
  65. "during HBA initialization. Memory allocation requirements "
  66. "vary by ISP type. Default is 1 - allocate memory.");
  67. int ql2xextended_error_logging;
  68. module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
  69. module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
  70. MODULE_PARM_DESC(ql2xextended_error_logging,
  71. "Option to enable extended error logging,\n"
  72. "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
  73. "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
  74. "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
  75. "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
  76. "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
  77. "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
  78. "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
  79. "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
  80. "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
  81. "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
  82. "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
  83. "\t\t0x1e400000 - Preferred value for capturing essential "
  84. "debug information (equivalent to old "
  85. "ql2xextended_error_logging=1).\n"
  86. "\t\tDo LOGICAL OR of the value to enable more than one level");
  87. int ql2xshiftctondsd = 6;
  88. module_param(ql2xshiftctondsd, int, S_IRUGO);
  89. MODULE_PARM_DESC(ql2xshiftctondsd,
  90. "Set to control shifting of command type processing "
  91. "based on total number of SG elements.");
  92. int ql2xfdmienable=1;
  93. module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
  94. module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
  95. MODULE_PARM_DESC(ql2xfdmienable,
  96. "Enables FDMI registrations. "
  97. "0 - no FDMI. Default is 1 - perform FDMI.");
  98. #define MAX_Q_DEPTH 32
  99. static int ql2xmaxqdepth = MAX_Q_DEPTH;
  100. module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
  101. MODULE_PARM_DESC(ql2xmaxqdepth,
  102. "Maximum queue depth to set for each LUN. "
  103. "Default is 32.");
  104. int ql2xenabledif = 2;
  105. module_param(ql2xenabledif, int, S_IRUGO);
  106. MODULE_PARM_DESC(ql2xenabledif,
  107. " Enable T10-CRC-DIF:\n"
  108. " Default is 2.\n"
  109. " 0 -- No DIF Support\n"
  110. " 1 -- Enable DIF for all types\n"
  111. " 2 -- Enable DIF for all types, except Type 0.\n");
  112. int ql2xenablehba_err_chk = 2;
  113. module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
  114. MODULE_PARM_DESC(ql2xenablehba_err_chk,
  115. " Enable T10-CRC-DIF Error isolation by HBA:\n"
  116. " Default is 2.\n"
  117. " 0 -- Error isolation disabled\n"
  118. " 1 -- Error isolation enabled only for DIX Type 0\n"
  119. " 2 -- Error isolation enabled for all Types\n");
  120. int ql2xiidmaenable=1;
  121. module_param(ql2xiidmaenable, int, S_IRUGO);
  122. MODULE_PARM_DESC(ql2xiidmaenable,
  123. "Enables iIDMA settings "
  124. "Default is 1 - perform iIDMA. 0 - no iIDMA.");
  125. int ql2xmaxqueues = 1;
  126. module_param(ql2xmaxqueues, int, S_IRUGO);
  127. MODULE_PARM_DESC(ql2xmaxqueues,
  128. "Enables MQ settings "
  129. "Default is 1 for single queue. Set it to number "
  130. "of queues in MQ mode.");
  131. int ql2xmultique_tag;
  132. module_param(ql2xmultique_tag, int, S_IRUGO);
  133. MODULE_PARM_DESC(ql2xmultique_tag,
  134. "Enables CPU affinity settings for the driver "
  135. "Default is 0 for no affinity of request and response IO. "
  136. "Set it to 1 to turn on the cpu affinity.");
  137. int ql2xfwloadbin;
  138. module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
  139. module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
  140. MODULE_PARM_DESC(ql2xfwloadbin,
  141. "Option to specify location from which to load ISP firmware:.\n"
  142. " 2 -- load firmware via the reject_firmware() (hotplug).\n"
  143. " interface.\n"
  144. " 1 -- load firmware from flash.\n"
  145. " 0 -- use default semantics.\n");
  146. int ql2xetsenable;
  147. module_param(ql2xetsenable, int, S_IRUGO);
  148. MODULE_PARM_DESC(ql2xetsenable,
  149. "Enables firmware ETS burst."
  150. "Default is 0 - skip ETS enablement.");
  151. int ql2xdbwr = 1;
  152. module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
  153. MODULE_PARM_DESC(ql2xdbwr,
  154. "Option to specify scheme for request queue posting.\n"
  155. " 0 -- Regular doorbell.\n"
  156. " 1 -- CAMRAM doorbell (faster).\n");
  157. int ql2xtargetreset = 1;
  158. module_param(ql2xtargetreset, int, S_IRUGO);
  159. MODULE_PARM_DESC(ql2xtargetreset,
  160. "Enable target reset."
  161. "Default is 1 - use hw defaults.");
  162. int ql2xgffidenable;
  163. module_param(ql2xgffidenable, int, S_IRUGO);
  164. MODULE_PARM_DESC(ql2xgffidenable,
  165. "Enables GFF_ID checks of port type. "
  166. "Default is 0 - Do not use GFF_ID information.");
  167. int ql2xasynctmfenable;
  168. module_param(ql2xasynctmfenable, int, S_IRUGO);
  169. MODULE_PARM_DESC(ql2xasynctmfenable,
  170. "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
  171. "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
  172. int ql2xdontresethba;
  173. module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
  174. MODULE_PARM_DESC(ql2xdontresethba,
  175. "Option to specify reset behaviour.\n"
  176. " 0 (Default) -- Reset on failure.\n"
  177. " 1 -- Do not reset on failure.\n");
  178. uint64_t ql2xmaxlun = MAX_LUNS;
  179. module_param(ql2xmaxlun, ullong, S_IRUGO);
  180. MODULE_PARM_DESC(ql2xmaxlun,
  181. "Defines the maximum LU number to register with the SCSI "
  182. "midlayer. Default is 65535.");
  183. int ql2xmdcapmask = 0x1F;
  184. module_param(ql2xmdcapmask, int, S_IRUGO);
  185. MODULE_PARM_DESC(ql2xmdcapmask,
  186. "Set the Minidump driver capture mask level. "
  187. "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
  188. int ql2xmdenable = 1;
  189. module_param(ql2xmdenable, int, S_IRUGO);
  190. MODULE_PARM_DESC(ql2xmdenable,
  191. "Enable/disable MiniDump. "
  192. "0 - MiniDump disabled. "
  193. "1 (Default) - MiniDump enabled.");
  194. int ql2xexlogins = 0;
  195. module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
  196. MODULE_PARM_DESC(ql2xexlogins,
  197. "Number of extended Logins. "
  198. "0 (Default)- Disabled.");
  199. int ql2xexchoffld = 0;
  200. module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
  201. MODULE_PARM_DESC(ql2xexchoffld,
  202. "Number of exchanges to offload. "
  203. "0 (Default)- Disabled.");
  204. int ql2xfwholdabts = 0;
  205. module_param(ql2xfwholdabts, int, S_IRUGO);
  206. MODULE_PARM_DESC(ql2xfwholdabts,
  207. "Allow FW to hold status IOCB until ABTS rsp received. "
  208. "0 (Default) Do not set fw option. "
  209. "1 - Set fw option to hold ABTS.");
  210. /*
  211. * SCSI host template entry points
  212. */
  213. static int qla2xxx_slave_configure(struct scsi_device * device);
  214. static int qla2xxx_slave_alloc(struct scsi_device *);
  215. static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
  216. static void qla2xxx_scan_start(struct Scsi_Host *);
  217. static void qla2xxx_slave_destroy(struct scsi_device *);
  218. static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  219. static int qla2xxx_eh_abort(struct scsi_cmnd *);
  220. static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
  221. static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
  222. static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
  223. static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
  224. static void qla2x00_clear_drv_active(struct qla_hw_data *);
  225. static void qla2x00_free_device(scsi_qla_host_t *);
  226. static void qla83xx_disable_laser(scsi_qla_host_t *vha);
  227. struct scsi_host_template qla2xxx_driver_template = {
  228. .module = THIS_MODULE,
  229. .name = QLA2XXX_DRIVER_NAME,
  230. .queuecommand = qla2xxx_queuecommand,
  231. .eh_abort_handler = qla2xxx_eh_abort,
  232. .eh_device_reset_handler = qla2xxx_eh_device_reset,
  233. .eh_target_reset_handler = qla2xxx_eh_target_reset,
  234. .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
  235. .eh_host_reset_handler = qla2xxx_eh_host_reset,
  236. .slave_configure = qla2xxx_slave_configure,
  237. .slave_alloc = qla2xxx_slave_alloc,
  238. .slave_destroy = qla2xxx_slave_destroy,
  239. .scan_finished = qla2xxx_scan_finished,
  240. .scan_start = qla2xxx_scan_start,
  241. .change_queue_depth = scsi_change_queue_depth,
  242. .this_id = -1,
  243. .cmd_per_lun = 3,
  244. .use_clustering = ENABLE_CLUSTERING,
  245. .sg_tablesize = SG_ALL,
  246. .max_sectors = 0xFFFF,
  247. .shost_attrs = qla2x00_host_attrs,
  248. .supported_mode = MODE_INITIATOR,
  249. .track_queue_depth = 1,
  250. };
  251. static struct scsi_transport_template *qla2xxx_transport_template = NULL;
  252. struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
  253. /* TODO Convert to inlines
  254. *
  255. * Timer routines
  256. */
  257. __inline__ void
  258. qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
  259. {
  260. init_timer(&vha->timer);
  261. vha->timer.expires = jiffies + interval * HZ;
  262. vha->timer.data = (unsigned long)vha;
  263. vha->timer.function = (void (*)(unsigned long))func;
  264. add_timer(&vha->timer);
  265. vha->timer_active = 1;
  266. }
  267. static inline void
  268. qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
  269. {
  270. /* Currently used for 82XX only. */
  271. if (vha->device_flags & DFLG_DEV_FAILED) {
  272. ql_dbg(ql_dbg_timer, vha, 0x600d,
  273. "Device in a failed state, returning.\n");
  274. return;
  275. }
  276. mod_timer(&vha->timer, jiffies + interval * HZ);
  277. }
  278. static __inline__ void
  279. qla2x00_stop_timer(scsi_qla_host_t *vha)
  280. {
  281. del_timer_sync(&vha->timer);
  282. vha->timer_active = 0;
  283. }
  284. static int qla2x00_do_dpc(void *data);
  285. static void qla2x00_rst_aen(scsi_qla_host_t *);
  286. static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
  287. struct req_que **, struct rsp_que **);
  288. static void qla2x00_free_fw_dump(struct qla_hw_data *);
  289. static void qla2x00_mem_free(struct qla_hw_data *);
  290. /* -------------------------------------------------------------------------- */
  291. static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
  292. struct rsp_que *rsp)
  293. {
  294. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  295. ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
  296. GFP_KERNEL);
  297. if (!ha->req_q_map) {
  298. ql_log(ql_log_fatal, vha, 0x003b,
  299. "Unable to allocate memory for request queue ptrs.\n");
  300. goto fail_req_map;
  301. }
  302. ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
  303. GFP_KERNEL);
  304. if (!ha->rsp_q_map) {
  305. ql_log(ql_log_fatal, vha, 0x003c,
  306. "Unable to allocate memory for response queue ptrs.\n");
  307. goto fail_rsp_map;
  308. }
  309. /*
  310. * Make sure we record at least the request and response queue zero in
  311. * case we need to free them if part of the probe fails.
  312. */
  313. ha->rsp_q_map[0] = rsp;
  314. ha->req_q_map[0] = req;
  315. set_bit(0, ha->rsp_qid_map);
  316. set_bit(0, ha->req_qid_map);
  317. return 1;
  318. fail_rsp_map:
  319. kfree(ha->req_q_map);
  320. ha->req_q_map = NULL;
  321. fail_req_map:
  322. return -ENOMEM;
  323. }
  324. static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
  325. {
  326. if (IS_QLAFX00(ha)) {
  327. if (req && req->ring_fx00)
  328. dma_free_coherent(&ha->pdev->dev,
  329. (req->length_fx00 + 1) * sizeof(request_t),
  330. req->ring_fx00, req->dma_fx00);
  331. } else if (req && req->ring)
  332. dma_free_coherent(&ha->pdev->dev,
  333. (req->length + 1) * sizeof(request_t),
  334. req->ring, req->dma);
  335. if (req)
  336. kfree(req->outstanding_cmds);
  337. kfree(req);
  338. req = NULL;
  339. }
  340. static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
  341. {
  342. if (IS_QLAFX00(ha)) {
  343. if (rsp && rsp->ring)
  344. dma_free_coherent(&ha->pdev->dev,
  345. (rsp->length_fx00 + 1) * sizeof(request_t),
  346. rsp->ring_fx00, rsp->dma_fx00);
  347. } else if (rsp && rsp->ring) {
  348. dma_free_coherent(&ha->pdev->dev,
  349. (rsp->length + 1) * sizeof(response_t),
  350. rsp->ring, rsp->dma);
  351. }
  352. kfree(rsp);
  353. rsp = NULL;
  354. }
  355. static void qla2x00_free_queues(struct qla_hw_data *ha)
  356. {
  357. struct req_que *req;
  358. struct rsp_que *rsp;
  359. int cnt;
  360. for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
  361. if (!test_bit(cnt, ha->req_qid_map))
  362. continue;
  363. req = ha->req_q_map[cnt];
  364. qla2x00_free_req_que(ha, req);
  365. }
  366. kfree(ha->req_q_map);
  367. ha->req_q_map = NULL;
  368. for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
  369. if (!test_bit(cnt, ha->rsp_qid_map))
  370. continue;
  371. rsp = ha->rsp_q_map[cnt];
  372. qla2x00_free_rsp_que(ha, rsp);
  373. }
  374. kfree(ha->rsp_q_map);
  375. ha->rsp_q_map = NULL;
  376. }
  377. static int qla25xx_setup_mode(struct scsi_qla_host *vha)
  378. {
  379. uint16_t options = 0;
  380. int ques, req, ret;
  381. struct qla_hw_data *ha = vha->hw;
  382. if (!(ha->fw_attributes & BIT_6)) {
  383. ql_log(ql_log_warn, vha, 0x00d8,
  384. "Firmware is not multi-queue capable.\n");
  385. goto fail;
  386. }
  387. if (ql2xmultique_tag) {
  388. /* create a request queue for IO */
  389. options |= BIT_7;
  390. req = qla25xx_create_req_que(ha, options, 0, 0, -1,
  391. QLA_DEFAULT_QUE_QOS);
  392. if (!req) {
  393. ql_log(ql_log_warn, vha, 0x00e0,
  394. "Failed to create request queue.\n");
  395. goto fail;
  396. }
  397. ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
  398. vha->req = ha->req_q_map[req];
  399. options |= BIT_1;
  400. for (ques = 1; ques < ha->max_rsp_queues; ques++) {
  401. ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
  402. if (!ret) {
  403. ql_log(ql_log_warn, vha, 0x00e8,
  404. "Failed to create response queue.\n");
  405. goto fail2;
  406. }
  407. }
  408. ha->flags.cpu_affinity_enabled = 1;
  409. ql_dbg(ql_dbg_multiq, vha, 0xc007,
  410. "CPU affinity mode enabled, "
  411. "no. of response queues:%d no. of request queues:%d.\n",
  412. ha->max_rsp_queues, ha->max_req_queues);
  413. ql_dbg(ql_dbg_init, vha, 0x00e9,
  414. "CPU affinity mode enabled, "
  415. "no. of response queues:%d no. of request queues:%d.\n",
  416. ha->max_rsp_queues, ha->max_req_queues);
  417. }
  418. return 0;
  419. fail2:
  420. qla25xx_delete_queues(vha);
  421. destroy_workqueue(ha->wq);
  422. ha->wq = NULL;
  423. vha->req = ha->req_q_map[0];
  424. fail:
  425. ha->mqenable = 0;
  426. kfree(ha->req_q_map);
  427. kfree(ha->rsp_q_map);
  428. ha->max_req_queues = ha->max_rsp_queues = 1;
  429. return 1;
  430. }
  431. static char *
  432. qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
  433. {
  434. struct qla_hw_data *ha = vha->hw;
  435. static char *pci_bus_modes[] = {
  436. "33", "66", "100", "133",
  437. };
  438. uint16_t pci_bus;
  439. strcpy(str, "PCI");
  440. pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
  441. if (pci_bus) {
  442. strcat(str, "-X (");
  443. strcat(str, pci_bus_modes[pci_bus]);
  444. } else {
  445. pci_bus = (ha->pci_attr & BIT_8) >> 8;
  446. strcat(str, " (");
  447. strcat(str, pci_bus_modes[pci_bus]);
  448. }
  449. strcat(str, " MHz)");
  450. return (str);
  451. }
  452. static char *
  453. qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
  454. {
  455. static char *pci_bus_modes[] = { "33", "66", "100", "133", };
  456. struct qla_hw_data *ha = vha->hw;
  457. uint32_t pci_bus;
  458. if (pci_is_pcie(ha->pdev)) {
  459. char lwstr[6];
  460. uint32_t lstat, lspeed, lwidth;
  461. pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
  462. lspeed = lstat & PCI_EXP_LNKCAP_SLS;
  463. lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
  464. strcpy(str, "PCIe (");
  465. switch (lspeed) {
  466. case 1:
  467. strcat(str, "2.5GT/s ");
  468. break;
  469. case 2:
  470. strcat(str, "5.0GT/s ");
  471. break;
  472. case 3:
  473. strcat(str, "8.0GT/s ");
  474. break;
  475. default:
  476. strcat(str, "<unknown> ");
  477. break;
  478. }
  479. snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
  480. strcat(str, lwstr);
  481. return str;
  482. }
  483. strcpy(str, "PCI");
  484. pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
  485. if (pci_bus == 0 || pci_bus == 8) {
  486. strcat(str, " (");
  487. strcat(str, pci_bus_modes[pci_bus >> 3]);
  488. } else {
  489. strcat(str, "-X ");
  490. if (pci_bus & BIT_2)
  491. strcat(str, "Mode 2");
  492. else
  493. strcat(str, "Mode 1");
  494. strcat(str, " (");
  495. strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
  496. }
  497. strcat(str, " MHz)");
  498. return str;
  499. }
  500. static char *
  501. qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
  502. {
  503. char un_str[10];
  504. struct qla_hw_data *ha = vha->hw;
  505. snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
  506. ha->fw_minor_version, ha->fw_subminor_version);
  507. if (ha->fw_attributes & BIT_9) {
  508. strcat(str, "FLX");
  509. return (str);
  510. }
  511. switch (ha->fw_attributes & 0xFF) {
  512. case 0x7:
  513. strcat(str, "EF");
  514. break;
  515. case 0x17:
  516. strcat(str, "TP");
  517. break;
  518. case 0x37:
  519. strcat(str, "IP");
  520. break;
  521. case 0x77:
  522. strcat(str, "VI");
  523. break;
  524. default:
  525. sprintf(un_str, "(%x)", ha->fw_attributes);
  526. strcat(str, un_str);
  527. break;
  528. }
  529. if (ha->fw_attributes & 0x100)
  530. strcat(str, "X");
  531. return (str);
  532. }
  533. static char *
  534. qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
  535. {
  536. struct qla_hw_data *ha = vha->hw;
  537. snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
  538. ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
  539. return str;
  540. }
  541. void
  542. qla2x00_sp_free_dma(void *vha, void *ptr)
  543. {
  544. srb_t *sp = (srb_t *)ptr;
  545. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  546. struct qla_hw_data *ha = sp->fcport->vha->hw;
  547. void *ctx = GET_CMD_CTX_SP(sp);
  548. if (sp->flags & SRB_DMA_VALID) {
  549. scsi_dma_unmap(cmd);
  550. sp->flags &= ~SRB_DMA_VALID;
  551. }
  552. if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
  553. dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
  554. scsi_prot_sg_count(cmd), cmd->sc_data_direction);
  555. sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
  556. }
  557. if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
  558. /* List assured to be having elements */
  559. qla2x00_clean_dsd_pool(ha, sp, NULL);
  560. sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
  561. }
  562. if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
  563. dma_pool_free(ha->dl_dma_pool, ctx,
  564. ((struct crc_context *)ctx)->crc_ctx_dma);
  565. sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
  566. }
  567. if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
  568. struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
  569. dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
  570. ctx1->fcp_cmnd_dma);
  571. list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
  572. ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
  573. ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
  574. mempool_free(ctx1, ha->ctx_mempool);
  575. ctx1 = NULL;
  576. }
  577. CMD_SP(cmd) = NULL;
  578. qla2x00_rel_sp(sp->fcport->vha, sp);
  579. }
  580. static void
  581. qla2x00_sp_compl(void *data, void *ptr, int res)
  582. {
  583. struct qla_hw_data *ha = (struct qla_hw_data *)data;
  584. srb_t *sp = (srb_t *)ptr;
  585. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  586. cmd->result = res;
  587. if (atomic_read(&sp->ref_count) == 0) {
  588. ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
  589. "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
  590. sp, GET_CMD_SP(sp));
  591. if (ql2xextended_error_logging & ql_dbg_io)
  592. WARN_ON(atomic_read(&sp->ref_count) == 0);
  593. return;
  594. }
  595. if (!atomic_dec_and_test(&sp->ref_count))
  596. return;
  597. qla2x00_sp_free_dma(ha, sp);
  598. cmd->scsi_done(cmd);
  599. }
  600. /* If we are SP1 here, we need to still take and release the host_lock as SP1
  601. * does not have the changes necessary to avoid taking host->host_lock.
  602. */
  603. static int
  604. qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
  605. {
  606. scsi_qla_host_t *vha = shost_priv(host);
  607. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  608. struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
  609. struct qla_hw_data *ha = vha->hw;
  610. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  611. srb_t *sp;
  612. int rval;
  613. if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
  614. cmd->result = DID_NO_CONNECT << 16;
  615. goto qc24_fail_command;
  616. }
  617. if (ha->flags.eeh_busy) {
  618. if (ha->flags.pci_channel_io_perm_failure) {
  619. ql_dbg(ql_dbg_aer, vha, 0x9010,
  620. "PCI Channel IO permanent failure, exiting "
  621. "cmd=%p.\n", cmd);
  622. cmd->result = DID_NO_CONNECT << 16;
  623. } else {
  624. ql_dbg(ql_dbg_aer, vha, 0x9011,
  625. "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
  626. cmd->result = DID_REQUEUE << 16;
  627. }
  628. goto qc24_fail_command;
  629. }
  630. rval = fc_remote_port_chkready(rport);
  631. if (rval) {
  632. cmd->result = rval;
  633. ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
  634. "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
  635. cmd, rval);
  636. goto qc24_fail_command;
  637. }
  638. if (!vha->flags.difdix_supported &&
  639. scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
  640. ql_dbg(ql_dbg_io, vha, 0x3004,
  641. "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
  642. cmd);
  643. cmd->result = DID_NO_CONNECT << 16;
  644. goto qc24_fail_command;
  645. }
  646. if (!fcport) {
  647. cmd->result = DID_NO_CONNECT << 16;
  648. goto qc24_fail_command;
  649. }
  650. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  651. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
  652. atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  653. ql_dbg(ql_dbg_io, vha, 0x3005,
  654. "Returning DNC, fcport_state=%d loop_state=%d.\n",
  655. atomic_read(&fcport->state),
  656. atomic_read(&base_vha->loop_state));
  657. cmd->result = DID_NO_CONNECT << 16;
  658. goto qc24_fail_command;
  659. }
  660. goto qc24_target_busy;
  661. }
  662. /*
  663. * Return target busy if we've received a non-zero retry_delay_timer
  664. * in a FCP_RSP.
  665. */
  666. if (fcport->retry_delay_timestamp == 0) {
  667. /* retry delay not set */
  668. } else if (time_after(jiffies, fcport->retry_delay_timestamp))
  669. fcport->retry_delay_timestamp = 0;
  670. else
  671. goto qc24_target_busy;
  672. sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
  673. if (!sp)
  674. goto qc24_host_busy;
  675. sp->u.scmd.cmd = cmd;
  676. sp->type = SRB_SCSI_CMD;
  677. atomic_set(&sp->ref_count, 1);
  678. CMD_SP(cmd) = (void *)sp;
  679. sp->free = qla2x00_sp_free_dma;
  680. sp->done = qla2x00_sp_compl;
  681. rval = ha->isp_ops->start_scsi(sp);
  682. if (rval != QLA_SUCCESS) {
  683. ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
  684. "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
  685. goto qc24_host_busy_free_sp;
  686. }
  687. return 0;
  688. qc24_host_busy_free_sp:
  689. qla2x00_sp_free_dma(ha, sp);
  690. qc24_host_busy:
  691. return SCSI_MLQUEUE_HOST_BUSY;
  692. qc24_target_busy:
  693. return SCSI_MLQUEUE_TARGET_BUSY;
  694. qc24_fail_command:
  695. cmd->scsi_done(cmd);
  696. return 0;
  697. }
  698. /*
  699. * qla2x00_eh_wait_on_command
  700. * Waits for the command to be returned by the Firmware for some
  701. * max time.
  702. *
  703. * Input:
  704. * cmd = Scsi Command to wait on.
  705. *
  706. * Return:
  707. * Not Found : 0
  708. * Found : 1
  709. */
  710. static int
  711. qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
  712. {
  713. #define ABORT_POLLING_PERIOD 1000
  714. #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
  715. unsigned long wait_iter = ABORT_WAIT_ITER;
  716. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  717. struct qla_hw_data *ha = vha->hw;
  718. int ret = QLA_SUCCESS;
  719. if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
  720. ql_dbg(ql_dbg_taskm, vha, 0x8005,
  721. "Return:eh_wait.\n");
  722. return ret;
  723. }
  724. while (CMD_SP(cmd) && wait_iter--) {
  725. msleep(ABORT_POLLING_PERIOD);
  726. }
  727. if (CMD_SP(cmd))
  728. ret = QLA_FUNCTION_FAILED;
  729. return ret;
  730. }
  731. /*
  732. * qla2x00_wait_for_hba_online
  733. * Wait till the HBA is online after going through
  734. * <= MAX_RETRIES_OF_ISP_ABORT or
  735. * finally HBA is disabled ie marked offline
  736. *
  737. * Input:
  738. * ha - pointer to host adapter structure
  739. *
  740. * Note:
  741. * Does context switching-Release SPIN_LOCK
  742. * (if any) before calling this routine.
  743. *
  744. * Return:
  745. * Success (Adapter is online) : 0
  746. * Failed (Adapter is offline/disabled) : 1
  747. */
  748. int
  749. qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
  750. {
  751. int return_status;
  752. unsigned long wait_online;
  753. struct qla_hw_data *ha = vha->hw;
  754. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  755. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  756. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  757. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  758. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  759. ha->dpc_active) && time_before(jiffies, wait_online)) {
  760. msleep(1000);
  761. }
  762. if (base_vha->flags.online)
  763. return_status = QLA_SUCCESS;
  764. else
  765. return_status = QLA_FUNCTION_FAILED;
  766. return (return_status);
  767. }
  768. /*
  769. * qla2x00_wait_for_hba_ready
  770. * Wait till the HBA is ready before doing driver unload
  771. *
  772. * Input:
  773. * ha - pointer to host adapter structure
  774. *
  775. * Note:
  776. * Does context switching-Release SPIN_LOCK
  777. * (if any) before calling this routine.
  778. *
  779. */
  780. static void
  781. qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
  782. {
  783. struct qla_hw_data *ha = vha->hw;
  784. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  785. while ((qla2x00_reset_active(vha) || ha->dpc_active ||
  786. ha->flags.mbox_busy) ||
  787. test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
  788. test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
  789. if (test_bit(UNLOADING, &base_vha->dpc_flags))
  790. break;
  791. msleep(1000);
  792. }
  793. }
  794. int
  795. qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
  796. {
  797. int return_status;
  798. unsigned long wait_reset;
  799. struct qla_hw_data *ha = vha->hw;
  800. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  801. wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  802. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  803. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  804. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  805. ha->dpc_active) && time_before(jiffies, wait_reset)) {
  806. msleep(1000);
  807. if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
  808. ha->flags.chip_reset_done)
  809. break;
  810. }
  811. if (ha->flags.chip_reset_done)
  812. return_status = QLA_SUCCESS;
  813. else
  814. return_status = QLA_FUNCTION_FAILED;
  815. return return_status;
  816. }
  817. static void
  818. sp_get(struct srb *sp)
  819. {
  820. atomic_inc(&sp->ref_count);
  821. }
  822. #define ISP_REG_DISCONNECT 0xffffffffU
  823. /**************************************************************************
  824. * qla2x00_isp_reg_stat
  825. *
  826. * Description:
  827. * Read the host status register of ISP before aborting the command.
  828. *
  829. * Input:
  830. * ha = pointer to host adapter structure.
  831. *
  832. *
  833. * Returns:
  834. * Either true or false.
  835. *
  836. * Note: Return true if there is register disconnect.
  837. **************************************************************************/
  838. static inline
  839. uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
  840. {
  841. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  842. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  843. if (IS_P3P_TYPE(ha))
  844. return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
  845. else
  846. return ((RD_REG_DWORD(&reg->host_status)) ==
  847. ISP_REG_DISCONNECT);
  848. }
  849. /**************************************************************************
  850. * qla2xxx_eh_abort
  851. *
  852. * Description:
  853. * The abort function will abort the specified command.
  854. *
  855. * Input:
  856. * cmd = Linux SCSI command packet to be aborted.
  857. *
  858. * Returns:
  859. * Either SUCCESS or FAILED.
  860. *
  861. * Note:
  862. * Only return FAILED if command not returned by firmware.
  863. **************************************************************************/
  864. static int
  865. qla2xxx_eh_abort(struct scsi_cmnd *cmd)
  866. {
  867. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  868. srb_t *sp;
  869. int ret;
  870. unsigned int id;
  871. uint64_t lun;
  872. unsigned long flags;
  873. int rval, wait = 0;
  874. struct qla_hw_data *ha = vha->hw;
  875. if (qla2x00_isp_reg_stat(ha)) {
  876. ql_log(ql_log_info, vha, 0x8042,
  877. "PCI/Register disconnect, exiting.\n");
  878. return FAILED;
  879. }
  880. if (!CMD_SP(cmd))
  881. return SUCCESS;
  882. ret = fc_block_scsi_eh(cmd);
  883. if (ret != 0)
  884. return ret;
  885. ret = SUCCESS;
  886. id = cmd->device->id;
  887. lun = cmd->device->lun;
  888. spin_lock_irqsave(&ha->hardware_lock, flags);
  889. sp = (srb_t *) CMD_SP(cmd);
  890. if (!sp) {
  891. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  892. return SUCCESS;
  893. }
  894. ql_dbg(ql_dbg_taskm, vha, 0x8002,
  895. "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
  896. vha->host_no, id, lun, sp, cmd, sp->handle);
  897. /* Get a reference to the sp and drop the lock.*/
  898. sp_get(sp);
  899. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  900. rval = ha->isp_ops->abort_command(sp);
  901. if (rval) {
  902. if (rval == QLA_FUNCTION_PARAMETER_ERROR)
  903. ret = SUCCESS;
  904. else
  905. ret = FAILED;
  906. ql_dbg(ql_dbg_taskm, vha, 0x8003,
  907. "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
  908. } else {
  909. ql_dbg(ql_dbg_taskm, vha, 0x8004,
  910. "Abort command mbx success cmd=%p.\n", cmd);
  911. wait = 1;
  912. }
  913. spin_lock_irqsave(&ha->hardware_lock, flags);
  914. sp->done(ha, sp, 0);
  915. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  916. /* Did the command return during mailbox execution? */
  917. if (ret == FAILED && !CMD_SP(cmd))
  918. ret = SUCCESS;
  919. /* Wait for the command to be returned. */
  920. if (wait) {
  921. if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
  922. ql_log(ql_log_warn, vha, 0x8006,
  923. "Abort handler timed out cmd=%p.\n", cmd);
  924. ret = FAILED;
  925. }
  926. }
  927. ql_log(ql_log_info, vha, 0x801c,
  928. "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
  929. vha->host_no, id, lun, wait, ret);
  930. return ret;
  931. }
  932. int
  933. qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
  934. uint64_t l, enum nexus_wait_type type)
  935. {
  936. int cnt, match, status;
  937. unsigned long flags;
  938. struct qla_hw_data *ha = vha->hw;
  939. struct req_que *req;
  940. srb_t *sp;
  941. struct scsi_cmnd *cmd;
  942. status = QLA_SUCCESS;
  943. spin_lock_irqsave(&ha->hardware_lock, flags);
  944. req = vha->req;
  945. for (cnt = 1; status == QLA_SUCCESS &&
  946. cnt < req->num_outstanding_cmds; cnt++) {
  947. sp = req->outstanding_cmds[cnt];
  948. if (!sp)
  949. continue;
  950. if (sp->type != SRB_SCSI_CMD)
  951. continue;
  952. if (vha->vp_idx != sp->fcport->vha->vp_idx)
  953. continue;
  954. match = 0;
  955. cmd = GET_CMD_SP(sp);
  956. switch (type) {
  957. case WAIT_HOST:
  958. match = 1;
  959. break;
  960. case WAIT_TARGET:
  961. match = cmd->device->id == t;
  962. break;
  963. case WAIT_LUN:
  964. match = (cmd->device->id == t &&
  965. cmd->device->lun == l);
  966. break;
  967. }
  968. if (!match)
  969. continue;
  970. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  971. status = qla2x00_eh_wait_on_command(cmd);
  972. spin_lock_irqsave(&ha->hardware_lock, flags);
  973. }
  974. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  975. return status;
  976. }
  977. static char *reset_errors[] = {
  978. "HBA not online",
  979. "HBA not ready",
  980. "Task management failed",
  981. "Waiting for command completions",
  982. };
  983. static int
  984. __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
  985. struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
  986. {
  987. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  988. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  989. int err;
  990. if (!fcport) {
  991. return FAILED;
  992. }
  993. err = fc_block_scsi_eh(cmd);
  994. if (err != 0)
  995. return err;
  996. ql_log(ql_log_info, vha, 0x8009,
  997. "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
  998. cmd->device->id, cmd->device->lun, cmd);
  999. err = 0;
  1000. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
  1001. ql_log(ql_log_warn, vha, 0x800a,
  1002. "Wait for hba online failed for cmd=%p.\n", cmd);
  1003. goto eh_reset_failed;
  1004. }
  1005. err = 2;
  1006. if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
  1007. != QLA_SUCCESS) {
  1008. ql_log(ql_log_warn, vha, 0x800c,
  1009. "do_reset failed for cmd=%p.\n", cmd);
  1010. goto eh_reset_failed;
  1011. }
  1012. err = 3;
  1013. if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
  1014. cmd->device->lun, type) != QLA_SUCCESS) {
  1015. ql_log(ql_log_warn, vha, 0x800d,
  1016. "wait for pending cmds failed for cmd=%p.\n", cmd);
  1017. goto eh_reset_failed;
  1018. }
  1019. ql_log(ql_log_info, vha, 0x800e,
  1020. "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
  1021. vha->host_no, cmd->device->id, cmd->device->lun, cmd);
  1022. return SUCCESS;
  1023. eh_reset_failed:
  1024. ql_log(ql_log_info, vha, 0x800f,
  1025. "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
  1026. reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
  1027. cmd);
  1028. return FAILED;
  1029. }
  1030. static int
  1031. qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
  1032. {
  1033. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  1034. struct qla_hw_data *ha = vha->hw;
  1035. if (qla2x00_isp_reg_stat(ha)) {
  1036. ql_log(ql_log_info, vha, 0x803e,
  1037. "PCI/Register disconnect, exiting.\n");
  1038. return FAILED;
  1039. }
  1040. return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
  1041. ha->isp_ops->lun_reset);
  1042. }
  1043. static int
  1044. qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
  1045. {
  1046. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  1047. struct qla_hw_data *ha = vha->hw;
  1048. if (qla2x00_isp_reg_stat(ha)) {
  1049. ql_log(ql_log_info, vha, 0x803f,
  1050. "PCI/Register disconnect, exiting.\n");
  1051. return FAILED;
  1052. }
  1053. return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
  1054. ha->isp_ops->target_reset);
  1055. }
  1056. /**************************************************************************
  1057. * qla2xxx_eh_bus_reset
  1058. *
  1059. * Description:
  1060. * The bus reset function will reset the bus and abort any executing
  1061. * commands.
  1062. *
  1063. * Input:
  1064. * cmd = Linux SCSI command packet of the command that cause the
  1065. * bus reset.
  1066. *
  1067. * Returns:
  1068. * SUCCESS/FAILURE (defined as macro in scsi.h).
  1069. *
  1070. **************************************************************************/
  1071. static int
  1072. qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
  1073. {
  1074. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  1075. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  1076. int ret = FAILED;
  1077. unsigned int id;
  1078. uint64_t lun;
  1079. struct qla_hw_data *ha = vha->hw;
  1080. if (qla2x00_isp_reg_stat(ha)) {
  1081. ql_log(ql_log_info, vha, 0x8040,
  1082. "PCI/Register disconnect, exiting.\n");
  1083. return FAILED;
  1084. }
  1085. id = cmd->device->id;
  1086. lun = cmd->device->lun;
  1087. if (!fcport) {
  1088. return ret;
  1089. }
  1090. ret = fc_block_scsi_eh(cmd);
  1091. if (ret != 0)
  1092. return ret;
  1093. ret = FAILED;
  1094. ql_log(ql_log_info, vha, 0x8012,
  1095. "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
  1096. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
  1097. ql_log(ql_log_fatal, vha, 0x8013,
  1098. "Wait for hba online failed board disabled.\n");
  1099. goto eh_bus_reset_done;
  1100. }
  1101. if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
  1102. ret = SUCCESS;
  1103. if (ret == FAILED)
  1104. goto eh_bus_reset_done;
  1105. /* Flush outstanding commands. */
  1106. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
  1107. QLA_SUCCESS) {
  1108. ql_log(ql_log_warn, vha, 0x8014,
  1109. "Wait for pending commands failed.\n");
  1110. ret = FAILED;
  1111. }
  1112. eh_bus_reset_done:
  1113. ql_log(ql_log_warn, vha, 0x802b,
  1114. "BUS RESET %s nexus=%ld:%d:%llu.\n",
  1115. (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
  1116. return ret;
  1117. }
  1118. /**************************************************************************
  1119. * qla2xxx_eh_host_reset
  1120. *
  1121. * Description:
  1122. * The reset function will reset the Adapter.
  1123. *
  1124. * Input:
  1125. * cmd = Linux SCSI command packet of the command that cause the
  1126. * adapter reset.
  1127. *
  1128. * Returns:
  1129. * Either SUCCESS or FAILED.
  1130. *
  1131. * Note:
  1132. **************************************************************************/
  1133. static int
  1134. qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
  1135. {
  1136. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  1137. struct qla_hw_data *ha = vha->hw;
  1138. int ret = FAILED;
  1139. unsigned int id;
  1140. uint64_t lun;
  1141. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  1142. if (qla2x00_isp_reg_stat(ha)) {
  1143. ql_log(ql_log_info, vha, 0x8041,
  1144. "PCI/Register disconnect, exiting.\n");
  1145. schedule_work(&ha->board_disable);
  1146. return SUCCESS;
  1147. }
  1148. id = cmd->device->id;
  1149. lun = cmd->device->lun;
  1150. ql_log(ql_log_info, vha, 0x8018,
  1151. "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
  1152. /*
  1153. * No point in issuing another reset if one is active. Also do not
  1154. * attempt a reset if we are updating flash.
  1155. */
  1156. if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
  1157. goto eh_host_reset_lock;
  1158. if (vha != base_vha) {
  1159. if (qla2x00_vp_abort_isp(vha))
  1160. goto eh_host_reset_lock;
  1161. } else {
  1162. if (IS_P3P_TYPE(vha->hw)) {
  1163. if (!qla82xx_fcoe_ctx_reset(vha)) {
  1164. /* Ctx reset success */
  1165. ret = SUCCESS;
  1166. goto eh_host_reset_lock;
  1167. }
  1168. /* fall thru if ctx reset failed */
  1169. }
  1170. if (ha->wq)
  1171. flush_workqueue(ha->wq);
  1172. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  1173. if (ha->isp_ops->abort_isp(base_vha)) {
  1174. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  1175. /* failed. schedule dpc to try */
  1176. set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
  1177. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
  1178. ql_log(ql_log_warn, vha, 0x802a,
  1179. "wait for hba online failed.\n");
  1180. goto eh_host_reset_lock;
  1181. }
  1182. }
  1183. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  1184. }
  1185. /* Waiting for command to be returned to OS.*/
  1186. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
  1187. QLA_SUCCESS)
  1188. ret = SUCCESS;
  1189. eh_host_reset_lock:
  1190. ql_log(ql_log_info, vha, 0x8017,
  1191. "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
  1192. (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
  1193. return ret;
  1194. }
  1195. /*
  1196. * qla2x00_loop_reset
  1197. * Issue loop reset.
  1198. *
  1199. * Input:
  1200. * ha = adapter block pointer.
  1201. *
  1202. * Returns:
  1203. * 0 = success
  1204. */
  1205. int
  1206. qla2x00_loop_reset(scsi_qla_host_t *vha)
  1207. {
  1208. int ret;
  1209. struct fc_port *fcport;
  1210. struct qla_hw_data *ha = vha->hw;
  1211. if (IS_QLAFX00(ha)) {
  1212. return qlafx00_loop_reset(vha);
  1213. }
  1214. if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
  1215. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1216. if (fcport->port_type != FCT_TARGET)
  1217. continue;
  1218. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  1219. if (ret != QLA_SUCCESS) {
  1220. ql_dbg(ql_dbg_taskm, vha, 0x802c,
  1221. "Bus Reset failed: Reset=%d "
  1222. "d_id=%x.\n", ret, fcport->d_id.b24);
  1223. }
  1224. }
  1225. }
  1226. if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
  1227. atomic_set(&vha->loop_state, LOOP_DOWN);
  1228. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1229. qla2x00_mark_all_devices_lost(vha, 0);
  1230. ret = qla2x00_full_login_lip(vha);
  1231. if (ret != QLA_SUCCESS) {
  1232. ql_dbg(ql_dbg_taskm, vha, 0x802d,
  1233. "full_login_lip=%d.\n", ret);
  1234. }
  1235. }
  1236. if (ha->flags.enable_lip_reset) {
  1237. ret = qla2x00_lip_reset(vha);
  1238. if (ret != QLA_SUCCESS)
  1239. ql_dbg(ql_dbg_taskm, vha, 0x802e,
  1240. "lip_reset failed (%d).\n", ret);
  1241. }
  1242. /* Issue marker command only when we are going to start the I/O */
  1243. vha->marker_needed = 1;
  1244. return QLA_SUCCESS;
  1245. }
  1246. void
  1247. qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
  1248. {
  1249. int que, cnt, status;
  1250. unsigned long flags;
  1251. srb_t *sp;
  1252. struct qla_hw_data *ha = vha->hw;
  1253. struct req_que *req;
  1254. qlt_host_reset_handler(ha);
  1255. spin_lock_irqsave(&ha->hardware_lock, flags);
  1256. for (que = 0; que < ha->max_req_queues; que++) {
  1257. req = ha->req_q_map[que];
  1258. if (!req)
  1259. continue;
  1260. if (!req->outstanding_cmds)
  1261. continue;
  1262. for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
  1263. sp = req->outstanding_cmds[cnt];
  1264. if (sp) {
  1265. /* Don't abort commands in adapter during EEH
  1266. * recovery as it's not accessible/responding.
  1267. */
  1268. if (GET_CMD_SP(sp) && !ha->flags.eeh_busy &&
  1269. (sp->type == SRB_SCSI_CMD)) {
  1270. /* Get a reference to the sp and drop the lock.
  1271. * The reference ensures this sp->done() call
  1272. * - and not the call in qla2xxx_eh_abort() -
  1273. * ends the SCSI command (with result 'res').
  1274. */
  1275. sp_get(sp);
  1276. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1277. status = qla2xxx_eh_abort(GET_CMD_SP(sp));
  1278. spin_lock_irqsave(&ha->hardware_lock, flags);
  1279. /* Get rid of extra reference if immediate exit
  1280. * from ql2xxx_eh_abort */
  1281. if (status == FAILED && (qla2x00_isp_reg_stat(ha)))
  1282. atomic_dec(&sp->ref_count);
  1283. }
  1284. req->outstanding_cmds[cnt] = NULL;
  1285. sp->done(vha, sp, res);
  1286. }
  1287. }
  1288. }
  1289. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1290. }
  1291. static int
  1292. qla2xxx_slave_alloc(struct scsi_device *sdev)
  1293. {
  1294. struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
  1295. if (!rport || fc_remote_port_chkready(rport))
  1296. return -ENXIO;
  1297. sdev->hostdata = *(fc_port_t **)rport->dd_data;
  1298. return 0;
  1299. }
  1300. static int
  1301. qla2xxx_slave_configure(struct scsi_device *sdev)
  1302. {
  1303. scsi_qla_host_t *vha = shost_priv(sdev->host);
  1304. struct req_que *req = vha->req;
  1305. if (IS_T10_PI_CAPABLE(vha->hw))
  1306. blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
  1307. scsi_change_queue_depth(sdev, req->max_q_depth);
  1308. return 0;
  1309. }
  1310. static void
  1311. qla2xxx_slave_destroy(struct scsi_device *sdev)
  1312. {
  1313. sdev->hostdata = NULL;
  1314. }
  1315. /**
  1316. * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
  1317. * @ha: HA context
  1318. *
  1319. * At exit, the @ha's flags.enable_64bit_addressing set to indicated
  1320. * supported addressing method.
  1321. */
  1322. static void
  1323. qla2x00_config_dma_addressing(struct qla_hw_data *ha)
  1324. {
  1325. /* Assume a 32bit DMA mask. */
  1326. ha->flags.enable_64bit_addressing = 0;
  1327. if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
  1328. /* Any upper-dword bits set? */
  1329. if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
  1330. !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
  1331. /* Ok, a 64bit DMA mask is applicable. */
  1332. ha->flags.enable_64bit_addressing = 1;
  1333. ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
  1334. ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
  1335. return;
  1336. }
  1337. }
  1338. dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
  1339. pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
  1340. }
  1341. static void
  1342. qla2x00_enable_intrs(struct qla_hw_data *ha)
  1343. {
  1344. unsigned long flags = 0;
  1345. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1346. spin_lock_irqsave(&ha->hardware_lock, flags);
  1347. ha->interrupts_on = 1;
  1348. /* enable risc and host interrupts */
  1349. WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
  1350. RD_REG_WORD(&reg->ictrl);
  1351. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1352. }
  1353. static void
  1354. qla2x00_disable_intrs(struct qla_hw_data *ha)
  1355. {
  1356. unsigned long flags = 0;
  1357. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1358. spin_lock_irqsave(&ha->hardware_lock, flags);
  1359. ha->interrupts_on = 0;
  1360. /* disable risc and host interrupts */
  1361. WRT_REG_WORD(&reg->ictrl, 0);
  1362. RD_REG_WORD(&reg->ictrl);
  1363. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1364. }
  1365. static void
  1366. qla24xx_enable_intrs(struct qla_hw_data *ha)
  1367. {
  1368. unsigned long flags = 0;
  1369. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1370. spin_lock_irqsave(&ha->hardware_lock, flags);
  1371. ha->interrupts_on = 1;
  1372. WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
  1373. RD_REG_DWORD(&reg->ictrl);
  1374. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1375. }
  1376. static void
  1377. qla24xx_disable_intrs(struct qla_hw_data *ha)
  1378. {
  1379. unsigned long flags = 0;
  1380. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1381. if (IS_NOPOLLING_TYPE(ha))
  1382. return;
  1383. spin_lock_irqsave(&ha->hardware_lock, flags);
  1384. ha->interrupts_on = 0;
  1385. WRT_REG_DWORD(&reg->ictrl, 0);
  1386. RD_REG_DWORD(&reg->ictrl);
  1387. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1388. }
  1389. static int
  1390. qla2x00_iospace_config(struct qla_hw_data *ha)
  1391. {
  1392. resource_size_t pio;
  1393. uint16_t msix;
  1394. int cpus;
  1395. if (pci_request_selected_regions(ha->pdev, ha->bars,
  1396. QLA2XXX_DRIVER_NAME)) {
  1397. ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
  1398. "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
  1399. pci_name(ha->pdev));
  1400. goto iospace_error_exit;
  1401. }
  1402. if (!(ha->bars & 1))
  1403. goto skip_pio;
  1404. /* We only need PIO for Flash operations on ISP2312 v2 chips. */
  1405. pio = pci_resource_start(ha->pdev, 0);
  1406. if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
  1407. if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
  1408. ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
  1409. "Invalid pci I/O region size (%s).\n",
  1410. pci_name(ha->pdev));
  1411. pio = 0;
  1412. }
  1413. } else {
  1414. ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
  1415. "Region #0 no a PIO resource (%s).\n",
  1416. pci_name(ha->pdev));
  1417. pio = 0;
  1418. }
  1419. ha->pio_address = pio;
  1420. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
  1421. "PIO address=%llu.\n",
  1422. (unsigned long long)ha->pio_address);
  1423. skip_pio:
  1424. /* Use MMIO operations for all accesses. */
  1425. if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
  1426. ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
  1427. "Region #1 not an MMIO resource (%s), aborting.\n",
  1428. pci_name(ha->pdev));
  1429. goto iospace_error_exit;
  1430. }
  1431. if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
  1432. ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
  1433. "Invalid PCI mem region size (%s), aborting.\n",
  1434. pci_name(ha->pdev));
  1435. goto iospace_error_exit;
  1436. }
  1437. ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
  1438. if (!ha->iobase) {
  1439. ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
  1440. "Cannot remap MMIO (%s), aborting.\n",
  1441. pci_name(ha->pdev));
  1442. goto iospace_error_exit;
  1443. }
  1444. /* Determine queue resources */
  1445. ha->max_req_queues = ha->max_rsp_queues = 1;
  1446. if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
  1447. (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
  1448. (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
  1449. goto mqiobase_exit;
  1450. ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
  1451. pci_resource_len(ha->pdev, 3));
  1452. if (ha->mqiobase) {
  1453. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
  1454. "MQIO Base=%p.\n", ha->mqiobase);
  1455. /* Read MSIX vector size of the board */
  1456. pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
  1457. ha->msix_count = msix;
  1458. /* Max queues are bounded by available msix vectors */
  1459. /* queue 0 uses two msix vectors */
  1460. if (ql2xmultique_tag) {
  1461. cpus = num_online_cpus();
  1462. ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
  1463. (cpus + 1) : (ha->msix_count - 1);
  1464. ha->max_req_queues = 2;
  1465. } else if (ql2xmaxqueues > 1) {
  1466. ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
  1467. QLA_MQ_SIZE : ql2xmaxqueues;
  1468. ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
  1469. "QoS mode set, max no of request queues:%d.\n",
  1470. ha->max_req_queues);
  1471. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
  1472. "QoS mode set, max no of request queues:%d.\n",
  1473. ha->max_req_queues);
  1474. }
  1475. ql_log_pci(ql_log_info, ha->pdev, 0x001a,
  1476. "MSI-X vector count: %d.\n", msix);
  1477. } else
  1478. ql_log_pci(ql_log_info, ha->pdev, 0x001b,
  1479. "BAR 3 not enabled.\n");
  1480. mqiobase_exit:
  1481. ha->msix_count = ha->max_rsp_queues + 1;
  1482. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
  1483. "MSIX Count:%d.\n", ha->msix_count);
  1484. return (0);
  1485. iospace_error_exit:
  1486. return (-ENOMEM);
  1487. }
  1488. static int
  1489. qla83xx_iospace_config(struct qla_hw_data *ha)
  1490. {
  1491. uint16_t msix;
  1492. int cpus;
  1493. if (pci_request_selected_regions(ha->pdev, ha->bars,
  1494. QLA2XXX_DRIVER_NAME)) {
  1495. ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
  1496. "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
  1497. pci_name(ha->pdev));
  1498. goto iospace_error_exit;
  1499. }
  1500. /* Use MMIO operations for all accesses. */
  1501. if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
  1502. ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
  1503. "Invalid pci I/O region size (%s).\n",
  1504. pci_name(ha->pdev));
  1505. goto iospace_error_exit;
  1506. }
  1507. if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
  1508. ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
  1509. "Invalid PCI mem region size (%s), aborting\n",
  1510. pci_name(ha->pdev));
  1511. goto iospace_error_exit;
  1512. }
  1513. ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
  1514. if (!ha->iobase) {
  1515. ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
  1516. "Cannot remap MMIO (%s), aborting.\n",
  1517. pci_name(ha->pdev));
  1518. goto iospace_error_exit;
  1519. }
  1520. /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
  1521. /* 83XX 26XX always use MQ type access for queues
  1522. * - mbar 2, a.k.a region 4 */
  1523. ha->max_req_queues = ha->max_rsp_queues = 1;
  1524. ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
  1525. pci_resource_len(ha->pdev, 4));
  1526. if (!ha->mqiobase) {
  1527. ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
  1528. "BAR2/region4 not enabled\n");
  1529. goto mqiobase_exit;
  1530. }
  1531. ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
  1532. pci_resource_len(ha->pdev, 2));
  1533. if (ha->msixbase) {
  1534. /* Read MSIX vector size of the board */
  1535. pci_read_config_word(ha->pdev,
  1536. QLA_83XX_PCI_MSIX_CONTROL, &msix);
  1537. ha->msix_count = msix;
  1538. /* Max queues are bounded by available msix vectors */
  1539. /* queue 0 uses two msix vectors */
  1540. if (ql2xmultique_tag) {
  1541. cpus = num_online_cpus();
  1542. ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
  1543. (cpus + 1) : (ha->msix_count - 1);
  1544. ha->max_req_queues = 2;
  1545. } else if (ql2xmaxqueues > 1) {
  1546. ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
  1547. QLA_MQ_SIZE : ql2xmaxqueues;
  1548. ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
  1549. "QoS mode set, max no of request queues:%d.\n",
  1550. ha->max_req_queues);
  1551. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
  1552. "QoS mode set, max no of request queues:%d.\n",
  1553. ha->max_req_queues);
  1554. }
  1555. ql_log_pci(ql_log_info, ha->pdev, 0x011c,
  1556. "MSI-X vector count: %d.\n", msix);
  1557. } else
  1558. ql_log_pci(ql_log_info, ha->pdev, 0x011e,
  1559. "BAR 1 not enabled.\n");
  1560. mqiobase_exit:
  1561. ha->msix_count = ha->max_rsp_queues + 1;
  1562. qlt_83xx_iospace_config(ha);
  1563. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
  1564. "MSIX Count:%d.\n", ha->msix_count);
  1565. return 0;
  1566. iospace_error_exit:
  1567. return -ENOMEM;
  1568. }
  1569. static struct isp_operations qla2100_isp_ops = {
  1570. .pci_config = qla2100_pci_config,
  1571. .reset_chip = qla2x00_reset_chip,
  1572. .chip_diag = qla2x00_chip_diag,
  1573. .config_rings = qla2x00_config_rings,
  1574. .reset_adapter = qla2x00_reset_adapter,
  1575. .nvram_config = qla2x00_nvram_config,
  1576. .update_fw_options = qla2x00_update_fw_options,
  1577. .load_risc = qla2x00_load_risc,
  1578. .pci_info_str = qla2x00_pci_info_str,
  1579. .fw_version_str = qla2x00_fw_version_str,
  1580. .intr_handler = qla2100_intr_handler,
  1581. .enable_intrs = qla2x00_enable_intrs,
  1582. .disable_intrs = qla2x00_disable_intrs,
  1583. .abort_command = qla2x00_abort_command,
  1584. .target_reset = qla2x00_abort_target,
  1585. .lun_reset = qla2x00_lun_reset,
  1586. .fabric_login = qla2x00_login_fabric,
  1587. .fabric_logout = qla2x00_fabric_logout,
  1588. .calc_req_entries = qla2x00_calc_iocbs_32,
  1589. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1590. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1591. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1592. .read_nvram = qla2x00_read_nvram_data,
  1593. .write_nvram = qla2x00_write_nvram_data,
  1594. .fw_dump = qla2100_fw_dump,
  1595. .beacon_on = NULL,
  1596. .beacon_off = NULL,
  1597. .beacon_blink = NULL,
  1598. .read_optrom = qla2x00_read_optrom_data,
  1599. .write_optrom = qla2x00_write_optrom_data,
  1600. .get_flash_version = qla2x00_get_flash_version,
  1601. .start_scsi = qla2x00_start_scsi,
  1602. .abort_isp = qla2x00_abort_isp,
  1603. .iospace_config = qla2x00_iospace_config,
  1604. .initialize_adapter = qla2x00_initialize_adapter,
  1605. };
  1606. static struct isp_operations qla2300_isp_ops = {
  1607. .pci_config = qla2300_pci_config,
  1608. .reset_chip = qla2x00_reset_chip,
  1609. .chip_diag = qla2x00_chip_diag,
  1610. .config_rings = qla2x00_config_rings,
  1611. .reset_adapter = qla2x00_reset_adapter,
  1612. .nvram_config = qla2x00_nvram_config,
  1613. .update_fw_options = qla2x00_update_fw_options,
  1614. .load_risc = qla2x00_load_risc,
  1615. .pci_info_str = qla2x00_pci_info_str,
  1616. .fw_version_str = qla2x00_fw_version_str,
  1617. .intr_handler = qla2300_intr_handler,
  1618. .enable_intrs = qla2x00_enable_intrs,
  1619. .disable_intrs = qla2x00_disable_intrs,
  1620. .abort_command = qla2x00_abort_command,
  1621. .target_reset = qla2x00_abort_target,
  1622. .lun_reset = qla2x00_lun_reset,
  1623. .fabric_login = qla2x00_login_fabric,
  1624. .fabric_logout = qla2x00_fabric_logout,
  1625. .calc_req_entries = qla2x00_calc_iocbs_32,
  1626. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1627. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1628. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1629. .read_nvram = qla2x00_read_nvram_data,
  1630. .write_nvram = qla2x00_write_nvram_data,
  1631. .fw_dump = qla2300_fw_dump,
  1632. .beacon_on = qla2x00_beacon_on,
  1633. .beacon_off = qla2x00_beacon_off,
  1634. .beacon_blink = qla2x00_beacon_blink,
  1635. .read_optrom = qla2x00_read_optrom_data,
  1636. .write_optrom = qla2x00_write_optrom_data,
  1637. .get_flash_version = qla2x00_get_flash_version,
  1638. .start_scsi = qla2x00_start_scsi,
  1639. .abort_isp = qla2x00_abort_isp,
  1640. .iospace_config = qla2x00_iospace_config,
  1641. .initialize_adapter = qla2x00_initialize_adapter,
  1642. };
  1643. static struct isp_operations qla24xx_isp_ops = {
  1644. .pci_config = qla24xx_pci_config,
  1645. .reset_chip = qla24xx_reset_chip,
  1646. .chip_diag = qla24xx_chip_diag,
  1647. .config_rings = qla24xx_config_rings,
  1648. .reset_adapter = qla24xx_reset_adapter,
  1649. .nvram_config = qla24xx_nvram_config,
  1650. .update_fw_options = qla24xx_update_fw_options,
  1651. .load_risc = qla24xx_load_risc,
  1652. .pci_info_str = qla24xx_pci_info_str,
  1653. .fw_version_str = qla24xx_fw_version_str,
  1654. .intr_handler = qla24xx_intr_handler,
  1655. .enable_intrs = qla24xx_enable_intrs,
  1656. .disable_intrs = qla24xx_disable_intrs,
  1657. .abort_command = qla24xx_abort_command,
  1658. .target_reset = qla24xx_abort_target,
  1659. .lun_reset = qla24xx_lun_reset,
  1660. .fabric_login = qla24xx_login_fabric,
  1661. .fabric_logout = qla24xx_fabric_logout,
  1662. .calc_req_entries = NULL,
  1663. .build_iocbs = NULL,
  1664. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1665. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1666. .read_nvram = qla24xx_read_nvram_data,
  1667. .write_nvram = qla24xx_write_nvram_data,
  1668. .fw_dump = qla24xx_fw_dump,
  1669. .beacon_on = qla24xx_beacon_on,
  1670. .beacon_off = qla24xx_beacon_off,
  1671. .beacon_blink = qla24xx_beacon_blink,
  1672. .read_optrom = qla24xx_read_optrom_data,
  1673. .write_optrom = qla24xx_write_optrom_data,
  1674. .get_flash_version = qla24xx_get_flash_version,
  1675. .start_scsi = qla24xx_start_scsi,
  1676. .abort_isp = qla2x00_abort_isp,
  1677. .iospace_config = qla2x00_iospace_config,
  1678. .initialize_adapter = qla2x00_initialize_adapter,
  1679. };
  1680. static struct isp_operations qla25xx_isp_ops = {
  1681. .pci_config = qla25xx_pci_config,
  1682. .reset_chip = qla24xx_reset_chip,
  1683. .chip_diag = qla24xx_chip_diag,
  1684. .config_rings = qla24xx_config_rings,
  1685. .reset_adapter = qla24xx_reset_adapter,
  1686. .nvram_config = qla24xx_nvram_config,
  1687. .update_fw_options = qla24xx_update_fw_options,
  1688. .load_risc = qla24xx_load_risc,
  1689. .pci_info_str = qla24xx_pci_info_str,
  1690. .fw_version_str = qla24xx_fw_version_str,
  1691. .intr_handler = qla24xx_intr_handler,
  1692. .enable_intrs = qla24xx_enable_intrs,
  1693. .disable_intrs = qla24xx_disable_intrs,
  1694. .abort_command = qla24xx_abort_command,
  1695. .target_reset = qla24xx_abort_target,
  1696. .lun_reset = qla24xx_lun_reset,
  1697. .fabric_login = qla24xx_login_fabric,
  1698. .fabric_logout = qla24xx_fabric_logout,
  1699. .calc_req_entries = NULL,
  1700. .build_iocbs = NULL,
  1701. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1702. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1703. .read_nvram = qla25xx_read_nvram_data,
  1704. .write_nvram = qla25xx_write_nvram_data,
  1705. .fw_dump = qla25xx_fw_dump,
  1706. .beacon_on = qla24xx_beacon_on,
  1707. .beacon_off = qla24xx_beacon_off,
  1708. .beacon_blink = qla24xx_beacon_blink,
  1709. .read_optrom = qla25xx_read_optrom_data,
  1710. .write_optrom = qla24xx_write_optrom_data,
  1711. .get_flash_version = qla24xx_get_flash_version,
  1712. .start_scsi = qla24xx_dif_start_scsi,
  1713. .abort_isp = qla2x00_abort_isp,
  1714. .iospace_config = qla2x00_iospace_config,
  1715. .initialize_adapter = qla2x00_initialize_adapter,
  1716. };
  1717. static struct isp_operations qla81xx_isp_ops = {
  1718. .pci_config = qla25xx_pci_config,
  1719. .reset_chip = qla24xx_reset_chip,
  1720. .chip_diag = qla24xx_chip_diag,
  1721. .config_rings = qla24xx_config_rings,
  1722. .reset_adapter = qla24xx_reset_adapter,
  1723. .nvram_config = qla81xx_nvram_config,
  1724. .update_fw_options = qla81xx_update_fw_options,
  1725. .load_risc = qla81xx_load_risc,
  1726. .pci_info_str = qla24xx_pci_info_str,
  1727. .fw_version_str = qla24xx_fw_version_str,
  1728. .intr_handler = qla24xx_intr_handler,
  1729. .enable_intrs = qla24xx_enable_intrs,
  1730. .disable_intrs = qla24xx_disable_intrs,
  1731. .abort_command = qla24xx_abort_command,
  1732. .target_reset = qla24xx_abort_target,
  1733. .lun_reset = qla24xx_lun_reset,
  1734. .fabric_login = qla24xx_login_fabric,
  1735. .fabric_logout = qla24xx_fabric_logout,
  1736. .calc_req_entries = NULL,
  1737. .build_iocbs = NULL,
  1738. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1739. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1740. .read_nvram = NULL,
  1741. .write_nvram = NULL,
  1742. .fw_dump = qla81xx_fw_dump,
  1743. .beacon_on = qla24xx_beacon_on,
  1744. .beacon_off = qla24xx_beacon_off,
  1745. .beacon_blink = qla83xx_beacon_blink,
  1746. .read_optrom = qla25xx_read_optrom_data,
  1747. .write_optrom = qla24xx_write_optrom_data,
  1748. .get_flash_version = qla24xx_get_flash_version,
  1749. .start_scsi = qla24xx_dif_start_scsi,
  1750. .abort_isp = qla2x00_abort_isp,
  1751. .iospace_config = qla2x00_iospace_config,
  1752. .initialize_adapter = qla2x00_initialize_adapter,
  1753. };
  1754. static struct isp_operations qla82xx_isp_ops = {
  1755. .pci_config = qla82xx_pci_config,
  1756. .reset_chip = qla82xx_reset_chip,
  1757. .chip_diag = qla24xx_chip_diag,
  1758. .config_rings = qla82xx_config_rings,
  1759. .reset_adapter = qla24xx_reset_adapter,
  1760. .nvram_config = qla81xx_nvram_config,
  1761. .update_fw_options = qla24xx_update_fw_options,
  1762. .load_risc = qla82xx_load_risc,
  1763. .pci_info_str = qla24xx_pci_info_str,
  1764. .fw_version_str = qla24xx_fw_version_str,
  1765. .intr_handler = qla82xx_intr_handler,
  1766. .enable_intrs = qla82xx_enable_intrs,
  1767. .disable_intrs = qla82xx_disable_intrs,
  1768. .abort_command = qla24xx_abort_command,
  1769. .target_reset = qla24xx_abort_target,
  1770. .lun_reset = qla24xx_lun_reset,
  1771. .fabric_login = qla24xx_login_fabric,
  1772. .fabric_logout = qla24xx_fabric_logout,
  1773. .calc_req_entries = NULL,
  1774. .build_iocbs = NULL,
  1775. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1776. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1777. .read_nvram = qla24xx_read_nvram_data,
  1778. .write_nvram = qla24xx_write_nvram_data,
  1779. .fw_dump = qla82xx_fw_dump,
  1780. .beacon_on = qla82xx_beacon_on,
  1781. .beacon_off = qla82xx_beacon_off,
  1782. .beacon_blink = NULL,
  1783. .read_optrom = qla82xx_read_optrom_data,
  1784. .write_optrom = qla82xx_write_optrom_data,
  1785. .get_flash_version = qla82xx_get_flash_version,
  1786. .start_scsi = qla82xx_start_scsi,
  1787. .abort_isp = qla82xx_abort_isp,
  1788. .iospace_config = qla82xx_iospace_config,
  1789. .initialize_adapter = qla2x00_initialize_adapter,
  1790. };
  1791. static struct isp_operations qla8044_isp_ops = {
  1792. .pci_config = qla82xx_pci_config,
  1793. .reset_chip = qla82xx_reset_chip,
  1794. .chip_diag = qla24xx_chip_diag,
  1795. .config_rings = qla82xx_config_rings,
  1796. .reset_adapter = qla24xx_reset_adapter,
  1797. .nvram_config = qla81xx_nvram_config,
  1798. .update_fw_options = qla24xx_update_fw_options,
  1799. .load_risc = qla82xx_load_risc,
  1800. .pci_info_str = qla24xx_pci_info_str,
  1801. .fw_version_str = qla24xx_fw_version_str,
  1802. .intr_handler = qla8044_intr_handler,
  1803. .enable_intrs = qla82xx_enable_intrs,
  1804. .disable_intrs = qla82xx_disable_intrs,
  1805. .abort_command = qla24xx_abort_command,
  1806. .target_reset = qla24xx_abort_target,
  1807. .lun_reset = qla24xx_lun_reset,
  1808. .fabric_login = qla24xx_login_fabric,
  1809. .fabric_logout = qla24xx_fabric_logout,
  1810. .calc_req_entries = NULL,
  1811. .build_iocbs = NULL,
  1812. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1813. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1814. .read_nvram = NULL,
  1815. .write_nvram = NULL,
  1816. .fw_dump = qla8044_fw_dump,
  1817. .beacon_on = qla82xx_beacon_on,
  1818. .beacon_off = qla82xx_beacon_off,
  1819. .beacon_blink = NULL,
  1820. .read_optrom = qla8044_read_optrom_data,
  1821. .write_optrom = qla8044_write_optrom_data,
  1822. .get_flash_version = qla82xx_get_flash_version,
  1823. .start_scsi = qla82xx_start_scsi,
  1824. .abort_isp = qla8044_abort_isp,
  1825. .iospace_config = qla82xx_iospace_config,
  1826. .initialize_adapter = qla2x00_initialize_adapter,
  1827. };
  1828. static struct isp_operations qla83xx_isp_ops = {
  1829. .pci_config = qla25xx_pci_config,
  1830. .reset_chip = qla24xx_reset_chip,
  1831. .chip_diag = qla24xx_chip_diag,
  1832. .config_rings = qla24xx_config_rings,
  1833. .reset_adapter = qla24xx_reset_adapter,
  1834. .nvram_config = qla81xx_nvram_config,
  1835. .update_fw_options = qla81xx_update_fw_options,
  1836. .load_risc = qla81xx_load_risc,
  1837. .pci_info_str = qla24xx_pci_info_str,
  1838. .fw_version_str = qla24xx_fw_version_str,
  1839. .intr_handler = qla24xx_intr_handler,
  1840. .enable_intrs = qla24xx_enable_intrs,
  1841. .disable_intrs = qla24xx_disable_intrs,
  1842. .abort_command = qla24xx_abort_command,
  1843. .target_reset = qla24xx_abort_target,
  1844. .lun_reset = qla24xx_lun_reset,
  1845. .fabric_login = qla24xx_login_fabric,
  1846. .fabric_logout = qla24xx_fabric_logout,
  1847. .calc_req_entries = NULL,
  1848. .build_iocbs = NULL,
  1849. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1850. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1851. .read_nvram = NULL,
  1852. .write_nvram = NULL,
  1853. .fw_dump = qla83xx_fw_dump,
  1854. .beacon_on = qla24xx_beacon_on,
  1855. .beacon_off = qla24xx_beacon_off,
  1856. .beacon_blink = qla83xx_beacon_blink,
  1857. .read_optrom = qla25xx_read_optrom_data,
  1858. .write_optrom = qla24xx_write_optrom_data,
  1859. .get_flash_version = qla24xx_get_flash_version,
  1860. .start_scsi = qla24xx_dif_start_scsi,
  1861. .abort_isp = qla2x00_abort_isp,
  1862. .iospace_config = qla83xx_iospace_config,
  1863. .initialize_adapter = qla2x00_initialize_adapter,
  1864. };
  1865. static struct isp_operations qlafx00_isp_ops = {
  1866. .pci_config = qlafx00_pci_config,
  1867. .reset_chip = qlafx00_soft_reset,
  1868. .chip_diag = qlafx00_chip_diag,
  1869. .config_rings = qlafx00_config_rings,
  1870. .reset_adapter = qlafx00_soft_reset,
  1871. .nvram_config = NULL,
  1872. .update_fw_options = NULL,
  1873. .load_risc = NULL,
  1874. .pci_info_str = qlafx00_pci_info_str,
  1875. .fw_version_str = qlafx00_fw_version_str,
  1876. .intr_handler = qlafx00_intr_handler,
  1877. .enable_intrs = qlafx00_enable_intrs,
  1878. .disable_intrs = qlafx00_disable_intrs,
  1879. .abort_command = qla24xx_async_abort_command,
  1880. .target_reset = qlafx00_abort_target,
  1881. .lun_reset = qlafx00_lun_reset,
  1882. .fabric_login = NULL,
  1883. .fabric_logout = NULL,
  1884. .calc_req_entries = NULL,
  1885. .build_iocbs = NULL,
  1886. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1887. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1888. .read_nvram = qla24xx_read_nvram_data,
  1889. .write_nvram = qla24xx_write_nvram_data,
  1890. .fw_dump = NULL,
  1891. .beacon_on = qla24xx_beacon_on,
  1892. .beacon_off = qla24xx_beacon_off,
  1893. .beacon_blink = NULL,
  1894. .read_optrom = qla24xx_read_optrom_data,
  1895. .write_optrom = qla24xx_write_optrom_data,
  1896. .get_flash_version = qla24xx_get_flash_version,
  1897. .start_scsi = qlafx00_start_scsi,
  1898. .abort_isp = qlafx00_abort_isp,
  1899. .iospace_config = qlafx00_iospace_config,
  1900. .initialize_adapter = qlafx00_initialize_adapter,
  1901. };
  1902. static struct isp_operations qla27xx_isp_ops = {
  1903. .pci_config = qla25xx_pci_config,
  1904. .reset_chip = qla24xx_reset_chip,
  1905. .chip_diag = qla24xx_chip_diag,
  1906. .config_rings = qla24xx_config_rings,
  1907. .reset_adapter = qla24xx_reset_adapter,
  1908. .nvram_config = qla81xx_nvram_config,
  1909. .update_fw_options = qla81xx_update_fw_options,
  1910. .load_risc = qla81xx_load_risc,
  1911. .pci_info_str = qla24xx_pci_info_str,
  1912. .fw_version_str = qla24xx_fw_version_str,
  1913. .intr_handler = qla24xx_intr_handler,
  1914. .enable_intrs = qla24xx_enable_intrs,
  1915. .disable_intrs = qla24xx_disable_intrs,
  1916. .abort_command = qla24xx_abort_command,
  1917. .target_reset = qla24xx_abort_target,
  1918. .lun_reset = qla24xx_lun_reset,
  1919. .fabric_login = qla24xx_login_fabric,
  1920. .fabric_logout = qla24xx_fabric_logout,
  1921. .calc_req_entries = NULL,
  1922. .build_iocbs = NULL,
  1923. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1924. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1925. .read_nvram = NULL,
  1926. .write_nvram = NULL,
  1927. .fw_dump = qla27xx_fwdump,
  1928. .beacon_on = qla24xx_beacon_on,
  1929. .beacon_off = qla24xx_beacon_off,
  1930. .beacon_blink = qla83xx_beacon_blink,
  1931. .read_optrom = qla25xx_read_optrom_data,
  1932. .write_optrom = qla24xx_write_optrom_data,
  1933. .get_flash_version = qla24xx_get_flash_version,
  1934. .start_scsi = qla24xx_dif_start_scsi,
  1935. .abort_isp = qla2x00_abort_isp,
  1936. .iospace_config = qla83xx_iospace_config,
  1937. .initialize_adapter = qla2x00_initialize_adapter,
  1938. };
  1939. static inline void
  1940. qla2x00_set_isp_flags(struct qla_hw_data *ha)
  1941. {
  1942. ha->device_type = DT_EXTENDED_IDS;
  1943. switch (ha->pdev->device) {
  1944. case PCI_DEVICE_ID_QLOGIC_ISP2100:
  1945. ha->isp_type |= DT_ISP2100;
  1946. ha->device_type &= ~DT_EXTENDED_IDS;
  1947. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1948. break;
  1949. case PCI_DEVICE_ID_QLOGIC_ISP2200:
  1950. ha->isp_type |= DT_ISP2200;
  1951. ha->device_type &= ~DT_EXTENDED_IDS;
  1952. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1953. break;
  1954. case PCI_DEVICE_ID_QLOGIC_ISP2300:
  1955. ha->isp_type |= DT_ISP2300;
  1956. ha->device_type |= DT_ZIO_SUPPORTED;
  1957. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1958. break;
  1959. case PCI_DEVICE_ID_QLOGIC_ISP2312:
  1960. ha->isp_type |= DT_ISP2312;
  1961. ha->device_type |= DT_ZIO_SUPPORTED;
  1962. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1963. break;
  1964. case PCI_DEVICE_ID_QLOGIC_ISP2322:
  1965. ha->isp_type |= DT_ISP2322;
  1966. ha->device_type |= DT_ZIO_SUPPORTED;
  1967. if (ha->pdev->subsystem_vendor == 0x1028 &&
  1968. ha->pdev->subsystem_device == 0x0170)
  1969. ha->device_type |= DT_OEM_001;
  1970. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1971. break;
  1972. case PCI_DEVICE_ID_QLOGIC_ISP6312:
  1973. ha->isp_type |= DT_ISP6312;
  1974. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1975. break;
  1976. case PCI_DEVICE_ID_QLOGIC_ISP6322:
  1977. ha->isp_type |= DT_ISP6322;
  1978. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1979. break;
  1980. case PCI_DEVICE_ID_QLOGIC_ISP2422:
  1981. ha->isp_type |= DT_ISP2422;
  1982. ha->device_type |= DT_ZIO_SUPPORTED;
  1983. ha->device_type |= DT_FWI2;
  1984. ha->device_type |= DT_IIDMA;
  1985. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1986. break;
  1987. case PCI_DEVICE_ID_QLOGIC_ISP2432:
  1988. ha->isp_type |= DT_ISP2432;
  1989. ha->device_type |= DT_ZIO_SUPPORTED;
  1990. ha->device_type |= DT_FWI2;
  1991. ha->device_type |= DT_IIDMA;
  1992. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1993. break;
  1994. case PCI_DEVICE_ID_QLOGIC_ISP8432:
  1995. ha->isp_type |= DT_ISP8432;
  1996. ha->device_type |= DT_ZIO_SUPPORTED;
  1997. ha->device_type |= DT_FWI2;
  1998. ha->device_type |= DT_IIDMA;
  1999. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  2000. break;
  2001. case PCI_DEVICE_ID_QLOGIC_ISP5422:
  2002. ha->isp_type |= DT_ISP5422;
  2003. ha->device_type |= DT_FWI2;
  2004. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  2005. break;
  2006. case PCI_DEVICE_ID_QLOGIC_ISP5432:
  2007. ha->isp_type |= DT_ISP5432;
  2008. ha->device_type |= DT_FWI2;
  2009. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  2010. break;
  2011. case PCI_DEVICE_ID_QLOGIC_ISP2532:
  2012. ha->isp_type |= DT_ISP2532;
  2013. ha->device_type |= DT_ZIO_SUPPORTED;
  2014. ha->device_type |= DT_FWI2;
  2015. ha->device_type |= DT_IIDMA;
  2016. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  2017. break;
  2018. case PCI_DEVICE_ID_QLOGIC_ISP8001:
  2019. ha->isp_type |= DT_ISP8001;
  2020. ha->device_type |= DT_ZIO_SUPPORTED;
  2021. ha->device_type |= DT_FWI2;
  2022. ha->device_type |= DT_IIDMA;
  2023. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  2024. break;
  2025. case PCI_DEVICE_ID_QLOGIC_ISP8021:
  2026. ha->isp_type |= DT_ISP8021;
  2027. ha->device_type |= DT_ZIO_SUPPORTED;
  2028. ha->device_type |= DT_FWI2;
  2029. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  2030. /* Initialize 82XX ISP flags */
  2031. qla82xx_init_flags(ha);
  2032. break;
  2033. case PCI_DEVICE_ID_QLOGIC_ISP8044:
  2034. ha->isp_type |= DT_ISP8044;
  2035. ha->device_type |= DT_ZIO_SUPPORTED;
  2036. ha->device_type |= DT_FWI2;
  2037. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  2038. /* Initialize 82XX ISP flags */
  2039. qla82xx_init_flags(ha);
  2040. break;
  2041. case PCI_DEVICE_ID_QLOGIC_ISP2031:
  2042. ha->isp_type |= DT_ISP2031;
  2043. ha->device_type |= DT_ZIO_SUPPORTED;
  2044. ha->device_type |= DT_FWI2;
  2045. ha->device_type |= DT_IIDMA;
  2046. ha->device_type |= DT_T10_PI;
  2047. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  2048. break;
  2049. case PCI_DEVICE_ID_QLOGIC_ISP8031:
  2050. ha->isp_type |= DT_ISP8031;
  2051. ha->device_type |= DT_ZIO_SUPPORTED;
  2052. ha->device_type |= DT_FWI2;
  2053. ha->device_type |= DT_IIDMA;
  2054. ha->device_type |= DT_T10_PI;
  2055. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  2056. break;
  2057. case PCI_DEVICE_ID_QLOGIC_ISPF001:
  2058. ha->isp_type |= DT_ISPFX00;
  2059. break;
  2060. case PCI_DEVICE_ID_QLOGIC_ISP2071:
  2061. ha->isp_type |= DT_ISP2071;
  2062. ha->device_type |= DT_ZIO_SUPPORTED;
  2063. ha->device_type |= DT_FWI2;
  2064. ha->device_type |= DT_IIDMA;
  2065. ha->device_type |= DT_T10_PI;
  2066. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  2067. break;
  2068. case PCI_DEVICE_ID_QLOGIC_ISP2271:
  2069. ha->isp_type |= DT_ISP2271;
  2070. ha->device_type |= DT_ZIO_SUPPORTED;
  2071. ha->device_type |= DT_FWI2;
  2072. ha->device_type |= DT_IIDMA;
  2073. ha->device_type |= DT_T10_PI;
  2074. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  2075. break;
  2076. case PCI_DEVICE_ID_QLOGIC_ISP2261:
  2077. ha->isp_type |= DT_ISP2261;
  2078. ha->device_type |= DT_ZIO_SUPPORTED;
  2079. ha->device_type |= DT_FWI2;
  2080. ha->device_type |= DT_IIDMA;
  2081. ha->device_type |= DT_T10_PI;
  2082. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  2083. break;
  2084. }
  2085. if (IS_QLA82XX(ha))
  2086. ha->port_no = ha->portnum & 1;
  2087. else {
  2088. /* Get adapter physical port no from interrupt pin register. */
  2089. pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
  2090. if (IS_QLA27XX(ha))
  2091. ha->port_no--;
  2092. else
  2093. ha->port_no = !(ha->port_no & 1);
  2094. }
  2095. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
  2096. "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
  2097. ha->device_type, ha->port_no, ha->fw_srisc_address);
  2098. }
  2099. static void
  2100. qla2xxx_scan_start(struct Scsi_Host *shost)
  2101. {
  2102. scsi_qla_host_t *vha = shost_priv(shost);
  2103. if (vha->hw->flags.running_gold_fw)
  2104. return;
  2105. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2106. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2107. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  2108. set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
  2109. }
  2110. static int
  2111. qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
  2112. {
  2113. scsi_qla_host_t *vha = shost_priv(shost);
  2114. if (test_bit(UNLOADING, &vha->dpc_flags))
  2115. return 1;
  2116. if (!vha->host)
  2117. return 1;
  2118. if (time > vha->hw->loop_reset_delay * HZ)
  2119. return 1;
  2120. return atomic_read(&vha->loop_state) == LOOP_READY;
  2121. }
  2122. /*
  2123. * PCI driver interface
  2124. */
  2125. static int
  2126. qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
  2127. {
  2128. int ret = -ENODEV;
  2129. struct Scsi_Host *host;
  2130. scsi_qla_host_t *base_vha = NULL;
  2131. struct qla_hw_data *ha;
  2132. char pci_info[30];
  2133. char fw_str[30], wq_name[30];
  2134. struct scsi_host_template *sht;
  2135. int bars, mem_only = 0;
  2136. uint16_t req_length = 0, rsp_length = 0;
  2137. struct req_que *req = NULL;
  2138. struct rsp_que *rsp = NULL;
  2139. bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
  2140. sht = &qla2xxx_driver_template;
  2141. if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
  2142. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
  2143. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
  2144. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
  2145. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
  2146. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
  2147. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
  2148. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
  2149. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
  2150. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
  2151. pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
  2152. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
  2153. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
  2154. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
  2155. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
  2156. bars = pci_select_bars(pdev, IORESOURCE_MEM);
  2157. mem_only = 1;
  2158. ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
  2159. "Mem only adapter.\n");
  2160. }
  2161. ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
  2162. "Bars=%d.\n", bars);
  2163. if (mem_only) {
  2164. if (pci_enable_device_mem(pdev))
  2165. return ret;
  2166. } else {
  2167. if (pci_enable_device(pdev))
  2168. return ret;
  2169. }
  2170. /* This may fail but that's ok */
  2171. pci_enable_pcie_error_reporting(pdev);
  2172. ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
  2173. if (!ha) {
  2174. ql_log_pci(ql_log_fatal, pdev, 0x0009,
  2175. "Unable to allocate memory for ha.\n");
  2176. goto disable_device;
  2177. }
  2178. ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
  2179. "Memory allocated for ha=%p.\n", ha);
  2180. ha->pdev = pdev;
  2181. ha->tgt.enable_class_2 = ql2xenableclass2;
  2182. INIT_LIST_HEAD(&ha->tgt.q_full_list);
  2183. spin_lock_init(&ha->tgt.q_full_lock);
  2184. spin_lock_init(&ha->tgt.sess_lock);
  2185. spin_lock_init(&ha->tgt.atio_lock);
  2186. /* Clear our data area */
  2187. ha->bars = bars;
  2188. ha->mem_only = mem_only;
  2189. spin_lock_init(&ha->hardware_lock);
  2190. spin_lock_init(&ha->vport_slock);
  2191. mutex_init(&ha->selflogin_lock);
  2192. mutex_init(&ha->optrom_mutex);
  2193. /* Set ISP-type information. */
  2194. qla2x00_set_isp_flags(ha);
  2195. /* Set EEH reset type to fundamental if required by hba */
  2196. if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
  2197. IS_QLA83XX(ha) || IS_QLA27XX(ha))
  2198. pdev->needs_freset = 1;
  2199. ha->prev_topology = 0;
  2200. ha->init_cb_size = sizeof(init_cb_t);
  2201. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  2202. ha->optrom_size = OPTROM_SIZE_2300;
  2203. /* Assign ISP specific operations. */
  2204. if (IS_QLA2100(ha)) {
  2205. ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
  2206. ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
  2207. req_length = REQUEST_ENTRY_CNT_2100;
  2208. rsp_length = RESPONSE_ENTRY_CNT_2100;
  2209. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  2210. ha->gid_list_info_size = 4;
  2211. ha->flash_conf_off = ~0;
  2212. ha->flash_data_off = ~0;
  2213. ha->nvram_conf_off = ~0;
  2214. ha->nvram_data_off = ~0;
  2215. ha->isp_ops = &qla2100_isp_ops;
  2216. } else if (IS_QLA2200(ha)) {
  2217. ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
  2218. ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
  2219. req_length = REQUEST_ENTRY_CNT_2200;
  2220. rsp_length = RESPONSE_ENTRY_CNT_2100;
  2221. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  2222. ha->gid_list_info_size = 4;
  2223. ha->flash_conf_off = ~0;
  2224. ha->flash_data_off = ~0;
  2225. ha->nvram_conf_off = ~0;
  2226. ha->nvram_data_off = ~0;
  2227. ha->isp_ops = &qla2100_isp_ops;
  2228. } else if (IS_QLA23XX(ha)) {
  2229. ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
  2230. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  2231. req_length = REQUEST_ENTRY_CNT_2200;
  2232. rsp_length = RESPONSE_ENTRY_CNT_2300;
  2233. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  2234. ha->gid_list_info_size = 6;
  2235. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  2236. ha->optrom_size = OPTROM_SIZE_2322;
  2237. ha->flash_conf_off = ~0;
  2238. ha->flash_data_off = ~0;
  2239. ha->nvram_conf_off = ~0;
  2240. ha->nvram_data_off = ~0;
  2241. ha->isp_ops = &qla2300_isp_ops;
  2242. } else if (IS_QLA24XX_TYPE(ha)) {
  2243. ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
  2244. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  2245. req_length = REQUEST_ENTRY_CNT_24XX;
  2246. rsp_length = RESPONSE_ENTRY_CNT_2300;
  2247. ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
  2248. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  2249. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  2250. ha->gid_list_info_size = 8;
  2251. ha->optrom_size = OPTROM_SIZE_24XX;
  2252. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
  2253. ha->isp_ops = &qla24xx_isp_ops;
  2254. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  2255. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  2256. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  2257. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  2258. } else if (IS_QLA25XX(ha)) {
  2259. ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
  2260. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  2261. req_length = REQUEST_ENTRY_CNT_24XX;
  2262. rsp_length = RESPONSE_ENTRY_CNT_2300;
  2263. ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
  2264. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  2265. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  2266. ha->gid_list_info_size = 8;
  2267. ha->optrom_size = OPTROM_SIZE_25XX;
  2268. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  2269. ha->isp_ops = &qla25xx_isp_ops;
  2270. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  2271. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  2272. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  2273. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  2274. } else if (IS_QLA81XX(ha)) {
  2275. ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
  2276. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  2277. req_length = REQUEST_ENTRY_CNT_24XX;
  2278. rsp_length = RESPONSE_ENTRY_CNT_2300;
  2279. ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
  2280. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  2281. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  2282. ha->gid_list_info_size = 8;
  2283. ha->optrom_size = OPTROM_SIZE_81XX;
  2284. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  2285. ha->isp_ops = &qla81xx_isp_ops;
  2286. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
  2287. ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
  2288. ha->nvram_conf_off = ~0;
  2289. ha->nvram_data_off = ~0;
  2290. } else if (IS_QLA82XX(ha)) {
  2291. ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
  2292. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  2293. req_length = REQUEST_ENTRY_CNT_82XX;
  2294. rsp_length = RESPONSE_ENTRY_CNT_82XX;
  2295. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  2296. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  2297. ha->gid_list_info_size = 8;
  2298. ha->optrom_size = OPTROM_SIZE_82XX;
  2299. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  2300. ha->isp_ops = &qla82xx_isp_ops;
  2301. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  2302. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  2303. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  2304. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  2305. } else if (IS_QLA8044(ha)) {
  2306. ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
  2307. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  2308. req_length = REQUEST_ENTRY_CNT_82XX;
  2309. rsp_length = RESPONSE_ENTRY_CNT_82XX;
  2310. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  2311. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  2312. ha->gid_list_info_size = 8;
  2313. ha->optrom_size = OPTROM_SIZE_83XX;
  2314. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  2315. ha->isp_ops = &qla8044_isp_ops;
  2316. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  2317. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  2318. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  2319. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  2320. } else if (IS_QLA83XX(ha)) {
  2321. ha->portnum = PCI_FUNC(ha->pdev->devfn);
  2322. ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
  2323. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  2324. req_length = REQUEST_ENTRY_CNT_83XX;
  2325. rsp_length = RESPONSE_ENTRY_CNT_83XX;
  2326. ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
  2327. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  2328. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  2329. ha->gid_list_info_size = 8;
  2330. ha->optrom_size = OPTROM_SIZE_83XX;
  2331. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  2332. ha->isp_ops = &qla83xx_isp_ops;
  2333. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
  2334. ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
  2335. ha->nvram_conf_off = ~0;
  2336. ha->nvram_data_off = ~0;
  2337. } else if (IS_QLAFX00(ha)) {
  2338. ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
  2339. ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
  2340. ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
  2341. req_length = REQUEST_ENTRY_CNT_FX00;
  2342. rsp_length = RESPONSE_ENTRY_CNT_FX00;
  2343. ha->isp_ops = &qlafx00_isp_ops;
  2344. ha->port_down_retry_count = 30; /* default value */
  2345. ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
  2346. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  2347. ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
  2348. ha->mr.fw_hbt_en = 1;
  2349. ha->mr.host_info_resend = false;
  2350. ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
  2351. } else if (IS_QLA27XX(ha)) {
  2352. ha->portnum = PCI_FUNC(ha->pdev->devfn);
  2353. ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
  2354. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  2355. req_length = REQUEST_ENTRY_CNT_83XX;
  2356. rsp_length = RESPONSE_ENTRY_CNT_83XX;
  2357. ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
  2358. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  2359. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  2360. ha->gid_list_info_size = 8;
  2361. ha->optrom_size = OPTROM_SIZE_83XX;
  2362. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  2363. ha->isp_ops = &qla27xx_isp_ops;
  2364. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
  2365. ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
  2366. ha->nvram_conf_off = ~0;
  2367. ha->nvram_data_off = ~0;
  2368. }
  2369. ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
  2370. "mbx_count=%d, req_length=%d, "
  2371. "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
  2372. "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
  2373. "max_fibre_devices=%d.\n",
  2374. ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
  2375. ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
  2376. ha->nvram_npiv_size, ha->max_fibre_devices);
  2377. ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
  2378. "isp_ops=%p, flash_conf_off=%d, "
  2379. "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
  2380. ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
  2381. ha->nvram_conf_off, ha->nvram_data_off);
  2382. /* Configure PCI I/O space */
  2383. ret = ha->isp_ops->iospace_config(ha);
  2384. if (ret)
  2385. goto iospace_config_failed;
  2386. ql_log_pci(ql_log_info, pdev, 0x001d,
  2387. "Found an ISP%04X irq %d iobase 0x%p.\n",
  2388. pdev->device, pdev->irq, ha->iobase);
  2389. mutex_init(&ha->vport_lock);
  2390. init_completion(&ha->mbx_cmd_comp);
  2391. complete(&ha->mbx_cmd_comp);
  2392. init_completion(&ha->mbx_intr_comp);
  2393. init_completion(&ha->dcbx_comp);
  2394. init_completion(&ha->lb_portup_comp);
  2395. set_bit(0, (unsigned long *) ha->vp_idx_map);
  2396. qla2x00_config_dma_addressing(ha);
  2397. ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
  2398. "64 Bit addressing is %s.\n",
  2399. ha->flags.enable_64bit_addressing ? "enable" :
  2400. "disable");
  2401. ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
  2402. if (ret) {
  2403. ql_log_pci(ql_log_fatal, pdev, 0x0031,
  2404. "Failed to allocate memory for adapter, aborting.\n");
  2405. goto probe_hw_failed;
  2406. }
  2407. req->max_q_depth = MAX_Q_DEPTH;
  2408. if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
  2409. req->max_q_depth = ql2xmaxqdepth;
  2410. base_vha = qla2x00_create_host(sht, ha);
  2411. if (!base_vha) {
  2412. ret = -ENOMEM;
  2413. qla2x00_mem_free(ha);
  2414. qla2x00_free_req_que(ha, req);
  2415. qla2x00_free_rsp_que(ha, rsp);
  2416. goto probe_hw_failed;
  2417. }
  2418. pci_set_drvdata(pdev, base_vha);
  2419. set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
  2420. host = base_vha->host;
  2421. base_vha->req = req;
  2422. if (IS_QLA2XXX_MIDTYPE(ha))
  2423. base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
  2424. else
  2425. base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
  2426. base_vha->vp_idx;
  2427. /* Setup fcport template structure. */
  2428. ha->mr.fcport.vha = base_vha;
  2429. ha->mr.fcport.port_type = FCT_UNKNOWN;
  2430. ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
  2431. qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
  2432. ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
  2433. ha->mr.fcport.scan_state = 1;
  2434. /* Set the SG table size based on ISP type */
  2435. if (!IS_FWI2_CAPABLE(ha)) {
  2436. if (IS_QLA2100(ha))
  2437. host->sg_tablesize = 32;
  2438. } else {
  2439. if (!IS_QLA82XX(ha))
  2440. host->sg_tablesize = QLA_SG_ALL;
  2441. }
  2442. host->max_id = ha->max_fibre_devices;
  2443. host->cmd_per_lun = 3;
  2444. host->unique_id = host->host_no;
  2445. if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
  2446. host->max_cmd_len = 32;
  2447. else
  2448. host->max_cmd_len = MAX_CMDSZ;
  2449. host->max_channel = MAX_BUSES - 1;
  2450. /* Older HBAs support only 16-bit LUNs */
  2451. if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
  2452. ql2xmaxlun > 0xffff)
  2453. host->max_lun = 0xffff;
  2454. else
  2455. host->max_lun = ql2xmaxlun;
  2456. host->transportt = qla2xxx_transport_template;
  2457. sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
  2458. ql_dbg(ql_dbg_init, base_vha, 0x0033,
  2459. "max_id=%d this_id=%d "
  2460. "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
  2461. "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
  2462. host->this_id, host->cmd_per_lun, host->unique_id,
  2463. host->max_cmd_len, host->max_channel, host->max_lun,
  2464. host->transportt, sht->vendor_id);
  2465. que_init:
  2466. /* Alloc arrays of request and response ring ptrs */
  2467. if (!qla2x00_alloc_queues(ha, req, rsp)) {
  2468. ql_log(ql_log_fatal, base_vha, 0x003d,
  2469. "Failed to allocate memory for queue pointers..."
  2470. "aborting.\n");
  2471. goto probe_init_failed;
  2472. }
  2473. qlt_probe_one_stage1(base_vha, ha);
  2474. /* Set up the irqs */
  2475. ret = qla2x00_request_irqs(ha, rsp);
  2476. if (ret)
  2477. goto probe_init_failed;
  2478. pci_save_state(pdev);
  2479. /* Assign back pointers */
  2480. rsp->req = req;
  2481. req->rsp = rsp;
  2482. if (IS_QLAFX00(ha)) {
  2483. ha->rsp_q_map[0] = rsp;
  2484. ha->req_q_map[0] = req;
  2485. set_bit(0, ha->req_qid_map);
  2486. set_bit(0, ha->rsp_qid_map);
  2487. }
  2488. /* FWI2-capable only. */
  2489. req->req_q_in = &ha->iobase->isp24.req_q_in;
  2490. req->req_q_out = &ha->iobase->isp24.req_q_out;
  2491. rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
  2492. rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
  2493. if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
  2494. req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
  2495. req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
  2496. rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
  2497. rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
  2498. }
  2499. if (IS_QLAFX00(ha)) {
  2500. req->req_q_in = &ha->iobase->ispfx00.req_q_in;
  2501. req->req_q_out = &ha->iobase->ispfx00.req_q_out;
  2502. rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
  2503. rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
  2504. }
  2505. if (IS_P3P_TYPE(ha)) {
  2506. req->req_q_out = &ha->iobase->isp82.req_q_out[0];
  2507. rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
  2508. rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
  2509. }
  2510. ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
  2511. "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
  2512. ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
  2513. ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
  2514. "req->req_q_in=%p req->req_q_out=%p "
  2515. "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
  2516. req->req_q_in, req->req_q_out,
  2517. rsp->rsp_q_in, rsp->rsp_q_out);
  2518. ql_dbg(ql_dbg_init, base_vha, 0x003e,
  2519. "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
  2520. ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
  2521. ql_dbg(ql_dbg_init, base_vha, 0x003f,
  2522. "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
  2523. req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
  2524. if (ha->isp_ops->initialize_adapter(base_vha)) {
  2525. ql_log(ql_log_fatal, base_vha, 0x00d6,
  2526. "Failed to initialize adapter - Adapter flags %x.\n",
  2527. base_vha->device_flags);
  2528. if (IS_QLA82XX(ha)) {
  2529. qla82xx_idc_lock(ha);
  2530. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  2531. QLA8XXX_DEV_FAILED);
  2532. qla82xx_idc_unlock(ha);
  2533. ql_log(ql_log_fatal, base_vha, 0x00d7,
  2534. "HW State: FAILED.\n");
  2535. } else if (IS_QLA8044(ha)) {
  2536. qla8044_idc_lock(ha);
  2537. qla8044_wr_direct(base_vha,
  2538. QLA8044_CRB_DEV_STATE_INDEX,
  2539. QLA8XXX_DEV_FAILED);
  2540. qla8044_idc_unlock(ha);
  2541. ql_log(ql_log_fatal, base_vha, 0x0150,
  2542. "HW State: FAILED.\n");
  2543. }
  2544. ret = -ENODEV;
  2545. goto probe_failed;
  2546. }
  2547. if (IS_QLAFX00(ha))
  2548. host->can_queue = QLAFX00_MAX_CANQUEUE;
  2549. else
  2550. host->can_queue = req->num_outstanding_cmds - 10;
  2551. ql_dbg(ql_dbg_init, base_vha, 0x0032,
  2552. "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
  2553. host->can_queue, base_vha->req,
  2554. base_vha->mgmt_svr_loop_id, host->sg_tablesize);
  2555. if (ha->mqenable) {
  2556. if (qla25xx_setup_mode(base_vha)) {
  2557. ql_log(ql_log_warn, base_vha, 0x00ec,
  2558. "Failed to create queues, falling back to single queue mode.\n");
  2559. goto que_init;
  2560. }
  2561. }
  2562. if (ha->flags.running_gold_fw)
  2563. goto skip_dpc;
  2564. /*
  2565. * Startup the kernel thread for this host adapter
  2566. */
  2567. ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
  2568. "%s_dpc", base_vha->host_str);
  2569. if (IS_ERR(ha->dpc_thread)) {
  2570. ql_log(ql_log_fatal, base_vha, 0x00ed,
  2571. "Failed to start DPC thread.\n");
  2572. ret = PTR_ERR(ha->dpc_thread);
  2573. goto probe_failed;
  2574. }
  2575. ql_dbg(ql_dbg_init, base_vha, 0x00ee,
  2576. "DPC thread started successfully.\n");
  2577. /*
  2578. * If we're not coming up in initiator mode, we might sit for
  2579. * a while without waking up the dpc thread, which leads to a
  2580. * stuck process warning. So just kick the dpc once here and
  2581. * let the kthread start (and go back to sleep in qla2x00_do_dpc).
  2582. */
  2583. qla2xxx_wake_dpc(base_vha);
  2584. INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
  2585. if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
  2586. sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
  2587. ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
  2588. INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
  2589. sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
  2590. ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
  2591. INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
  2592. INIT_WORK(&ha->idc_state_handler,
  2593. qla83xx_idc_state_handler_work);
  2594. INIT_WORK(&ha->nic_core_unrecoverable,
  2595. qla83xx_nic_core_unrecoverable_work);
  2596. }
  2597. skip_dpc:
  2598. list_add_tail(&base_vha->list, &ha->vp_list);
  2599. base_vha->host->irq = ha->pdev->irq;
  2600. /* Initialized the timer */
  2601. qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
  2602. ql_dbg(ql_dbg_init, base_vha, 0x00ef,
  2603. "Started qla2x00_timer with "
  2604. "interval=%d.\n", WATCH_INTERVAL);
  2605. ql_dbg(ql_dbg_init, base_vha, 0x00f0,
  2606. "Detected hba at address=%p.\n",
  2607. ha);
  2608. if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
  2609. if (ha->fw_attributes & BIT_4) {
  2610. int prot = 0, guard;
  2611. base_vha->flags.difdix_supported = 1;
  2612. ql_dbg(ql_dbg_init, base_vha, 0x00f1,
  2613. "Registering for DIF/DIX type 1 and 3 protection.\n");
  2614. if (ql2xenabledif == 1)
  2615. prot = SHOST_DIX_TYPE0_PROTECTION;
  2616. scsi_host_set_prot(host,
  2617. prot | SHOST_DIF_TYPE1_PROTECTION
  2618. | SHOST_DIF_TYPE2_PROTECTION
  2619. | SHOST_DIF_TYPE3_PROTECTION
  2620. | SHOST_DIX_TYPE1_PROTECTION
  2621. | SHOST_DIX_TYPE2_PROTECTION
  2622. | SHOST_DIX_TYPE3_PROTECTION);
  2623. guard = SHOST_DIX_GUARD_CRC;
  2624. if (IS_PI_IPGUARD_CAPABLE(ha) &&
  2625. (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
  2626. guard |= SHOST_DIX_GUARD_IP;
  2627. scsi_host_set_guard(host, guard);
  2628. } else
  2629. base_vha->flags.difdix_supported = 0;
  2630. }
  2631. ha->isp_ops->enable_intrs(ha);
  2632. if (IS_QLAFX00(ha)) {
  2633. ret = qlafx00_fx_disc(base_vha,
  2634. &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
  2635. host->sg_tablesize = (ha->mr.extended_io_enabled) ?
  2636. QLA_SG_ALL : 128;
  2637. }
  2638. ret = scsi_add_host(host, &pdev->dev);
  2639. if (ret)
  2640. goto probe_failed;
  2641. base_vha->flags.init_done = 1;
  2642. base_vha->flags.online = 1;
  2643. ha->prev_minidump_failed = 0;
  2644. ql_dbg(ql_dbg_init, base_vha, 0x00f2,
  2645. "Init done and hba is online.\n");
  2646. if (qla_ini_mode_enabled(base_vha))
  2647. scsi_scan_host(host);
  2648. else
  2649. ql_dbg(ql_dbg_init, base_vha, 0x0122,
  2650. "skipping scsi_scan_host() for non-initiator port\n");
  2651. qla2x00_alloc_sysfs_attr(base_vha);
  2652. if (IS_QLAFX00(ha)) {
  2653. ret = qlafx00_fx_disc(base_vha,
  2654. &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
  2655. /* Register system information */
  2656. ret = qlafx00_fx_disc(base_vha,
  2657. &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
  2658. }
  2659. qla2x00_init_host_attr(base_vha);
  2660. qla2x00_dfs_setup(base_vha);
  2661. ql_log(ql_log_info, base_vha, 0x00fb,
  2662. "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
  2663. ql_log(ql_log_info, base_vha, 0x00fc,
  2664. "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
  2665. pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
  2666. pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
  2667. base_vha->host_no,
  2668. ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
  2669. qlt_add_target(ha, base_vha);
  2670. clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
  2671. if (test_bit(UNLOADING, &base_vha->dpc_flags))
  2672. return -ENODEV;
  2673. return 0;
  2674. probe_init_failed:
  2675. qla2x00_free_req_que(ha, req);
  2676. ha->req_q_map[0] = NULL;
  2677. clear_bit(0, ha->req_qid_map);
  2678. qla2x00_free_rsp_que(ha, rsp);
  2679. ha->rsp_q_map[0] = NULL;
  2680. clear_bit(0, ha->rsp_qid_map);
  2681. ha->max_req_queues = ha->max_rsp_queues = 0;
  2682. probe_failed:
  2683. if (base_vha->timer_active)
  2684. qla2x00_stop_timer(base_vha);
  2685. base_vha->flags.online = 0;
  2686. if (ha->dpc_thread) {
  2687. struct task_struct *t = ha->dpc_thread;
  2688. ha->dpc_thread = NULL;
  2689. kthread_stop(t);
  2690. }
  2691. qla2x00_free_device(base_vha);
  2692. scsi_host_put(base_vha->host);
  2693. probe_hw_failed:
  2694. qla2x00_clear_drv_active(ha);
  2695. iospace_config_failed:
  2696. if (IS_P3P_TYPE(ha)) {
  2697. if (!ha->nx_pcibase)
  2698. iounmap((device_reg_t *)ha->nx_pcibase);
  2699. if (!ql2xdbwr)
  2700. iounmap((device_reg_t *)ha->nxdb_wr_ptr);
  2701. } else {
  2702. if (ha->iobase)
  2703. iounmap(ha->iobase);
  2704. if (ha->cregbase)
  2705. iounmap(ha->cregbase);
  2706. }
  2707. pci_release_selected_regions(ha->pdev, ha->bars);
  2708. kfree(ha);
  2709. ha = NULL;
  2710. disable_device:
  2711. pci_disable_device(pdev);
  2712. return ret;
  2713. }
  2714. static void
  2715. qla2x00_shutdown(struct pci_dev *pdev)
  2716. {
  2717. scsi_qla_host_t *vha;
  2718. struct qla_hw_data *ha;
  2719. if (!atomic_read(&pdev->enable_cnt))
  2720. return;
  2721. vha = pci_get_drvdata(pdev);
  2722. ha = vha->hw;
  2723. /* Notify ISPFX00 firmware */
  2724. if (IS_QLAFX00(ha))
  2725. qlafx00_driver_shutdown(vha, 20);
  2726. /* Turn-off FCE trace */
  2727. if (ha->flags.fce_enabled) {
  2728. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2729. ha->flags.fce_enabled = 0;
  2730. }
  2731. /* Turn-off EFT trace */
  2732. if (ha->eft)
  2733. qla2x00_disable_eft_trace(vha);
  2734. /* Stop currently executing firmware. */
  2735. qla2x00_try_to_stop_firmware(vha);
  2736. /* Turn adapter off line */
  2737. vha->flags.online = 0;
  2738. /* turn-off interrupts on the card */
  2739. if (ha->interrupts_on) {
  2740. vha->flags.init_done = 0;
  2741. ha->isp_ops->disable_intrs(ha);
  2742. }
  2743. qla2x00_free_irqs(vha);
  2744. qla2x00_free_fw_dump(ha);
  2745. pci_disable_pcie_error_reporting(pdev);
  2746. pci_disable_device(pdev);
  2747. }
  2748. /* Deletes all the virtual ports for a given ha */
  2749. static void
  2750. qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
  2751. {
  2752. scsi_qla_host_t *vha;
  2753. unsigned long flags;
  2754. mutex_lock(&ha->vport_lock);
  2755. while (ha->cur_vport_count) {
  2756. spin_lock_irqsave(&ha->vport_slock, flags);
  2757. BUG_ON(base_vha->list.next == &ha->vp_list);
  2758. /* This assumes first entry in ha->vp_list is always base vha */
  2759. vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
  2760. scsi_host_get(vha->host);
  2761. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2762. mutex_unlock(&ha->vport_lock);
  2763. fc_vport_terminate(vha->fc_vport);
  2764. scsi_host_put(vha->host);
  2765. mutex_lock(&ha->vport_lock);
  2766. }
  2767. mutex_unlock(&ha->vport_lock);
  2768. }
  2769. /* Stops all deferred work threads */
  2770. static void
  2771. qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
  2772. {
  2773. /* Flush the work queue and remove it */
  2774. if (ha->wq) {
  2775. flush_workqueue(ha->wq);
  2776. destroy_workqueue(ha->wq);
  2777. ha->wq = NULL;
  2778. }
  2779. /* Cancel all work and destroy DPC workqueues */
  2780. if (ha->dpc_lp_wq) {
  2781. cancel_work_sync(&ha->idc_aen);
  2782. destroy_workqueue(ha->dpc_lp_wq);
  2783. ha->dpc_lp_wq = NULL;
  2784. }
  2785. if (ha->dpc_hp_wq) {
  2786. cancel_work_sync(&ha->nic_core_reset);
  2787. cancel_work_sync(&ha->idc_state_handler);
  2788. cancel_work_sync(&ha->nic_core_unrecoverable);
  2789. destroy_workqueue(ha->dpc_hp_wq);
  2790. ha->dpc_hp_wq = NULL;
  2791. }
  2792. /* Kill the kernel thread for this host */
  2793. if (ha->dpc_thread) {
  2794. struct task_struct *t = ha->dpc_thread;
  2795. /*
  2796. * qla2xxx_wake_dpc checks for ->dpc_thread
  2797. * so we need to zero it out.
  2798. */
  2799. ha->dpc_thread = NULL;
  2800. kthread_stop(t);
  2801. }
  2802. }
  2803. static void
  2804. qla2x00_unmap_iobases(struct qla_hw_data *ha)
  2805. {
  2806. if (IS_QLA82XX(ha)) {
  2807. iounmap((device_reg_t *)ha->nx_pcibase);
  2808. if (!ql2xdbwr)
  2809. iounmap((device_reg_t *)ha->nxdb_wr_ptr);
  2810. } else {
  2811. if (ha->iobase)
  2812. iounmap(ha->iobase);
  2813. if (ha->cregbase)
  2814. iounmap(ha->cregbase);
  2815. if (ha->mqiobase)
  2816. iounmap(ha->mqiobase);
  2817. if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
  2818. iounmap(ha->msixbase);
  2819. }
  2820. }
  2821. static void
  2822. qla2x00_clear_drv_active(struct qla_hw_data *ha)
  2823. {
  2824. if (IS_QLA8044(ha)) {
  2825. qla8044_idc_lock(ha);
  2826. qla8044_clear_drv_active(ha);
  2827. qla8044_idc_unlock(ha);
  2828. } else if (IS_QLA82XX(ha)) {
  2829. qla82xx_idc_lock(ha);
  2830. qla82xx_clear_drv_active(ha);
  2831. qla82xx_idc_unlock(ha);
  2832. }
  2833. }
  2834. static void
  2835. qla2x00_remove_one(struct pci_dev *pdev)
  2836. {
  2837. scsi_qla_host_t *base_vha;
  2838. struct qla_hw_data *ha;
  2839. base_vha = pci_get_drvdata(pdev);
  2840. ha = base_vha->hw;
  2841. /* Indicate device removal to prevent future board_disable and wait
  2842. * until any pending board_disable has completed. */
  2843. set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
  2844. cancel_work_sync(&ha->board_disable);
  2845. /*
  2846. * If the PCI device is disabled then there was a PCI-disconnect and
  2847. * qla2x00_disable_board_on_pci_error has taken care of most of the
  2848. * resources.
  2849. */
  2850. if (!atomic_read(&pdev->enable_cnt)) {
  2851. scsi_host_put(base_vha->host);
  2852. kfree(ha);
  2853. pci_set_drvdata(pdev, NULL);
  2854. return;
  2855. }
  2856. qla2x00_wait_for_hba_ready(base_vha);
  2857. /* if UNLOAD flag is already set, then continue unload,
  2858. * where it was set first.
  2859. */
  2860. if (test_bit(UNLOADING, &base_vha->dpc_flags))
  2861. return;
  2862. set_bit(UNLOADING, &base_vha->dpc_flags);
  2863. if (IS_QLAFX00(ha))
  2864. qlafx00_driver_shutdown(base_vha, 20);
  2865. qla2x00_delete_all_vps(ha, base_vha);
  2866. if (IS_QLA8031(ha)) {
  2867. ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
  2868. "Clearing fcoe driver presence.\n");
  2869. if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
  2870. ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
  2871. "Error while clearing DRV-Presence.\n");
  2872. }
  2873. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2874. qla2x00_dfs_remove(base_vha);
  2875. qla84xx_put_chip(base_vha);
  2876. /* Laser should be disabled only for ISP2031 */
  2877. if (IS_QLA2031(ha))
  2878. qla83xx_disable_laser(base_vha);
  2879. /* Disable timer */
  2880. if (base_vha->timer_active)
  2881. qla2x00_stop_timer(base_vha);
  2882. base_vha->flags.online = 0;
  2883. /* free DMA memory */
  2884. if (ha->exlogin_buf)
  2885. qla2x00_free_exlogin_buffer(ha);
  2886. /* free DMA memory */
  2887. if (ha->exchoffld_buf)
  2888. qla2x00_free_exchoffld_buffer(ha);
  2889. qla2x00_destroy_deferred_work(ha);
  2890. qlt_remove_target(ha, base_vha);
  2891. qla2x00_free_sysfs_attr(base_vha, true);
  2892. fc_remove_host(base_vha->host);
  2893. scsi_remove_host(base_vha->host);
  2894. qla2x00_free_device(base_vha);
  2895. qla2x00_clear_drv_active(ha);
  2896. scsi_host_put(base_vha->host);
  2897. qla2x00_unmap_iobases(ha);
  2898. pci_release_selected_regions(ha->pdev, ha->bars);
  2899. kfree(ha);
  2900. ha = NULL;
  2901. pci_disable_pcie_error_reporting(pdev);
  2902. pci_disable_device(pdev);
  2903. }
  2904. static void
  2905. qla2x00_free_device(scsi_qla_host_t *vha)
  2906. {
  2907. struct qla_hw_data *ha = vha->hw;
  2908. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  2909. /* Disable timer */
  2910. if (vha->timer_active)
  2911. qla2x00_stop_timer(vha);
  2912. qla25xx_delete_queues(vha);
  2913. if (ha->flags.fce_enabled)
  2914. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2915. if (ha->eft)
  2916. qla2x00_disable_eft_trace(vha);
  2917. /* Stop currently executing firmware. */
  2918. qla2x00_try_to_stop_firmware(vha);
  2919. vha->flags.online = 0;
  2920. /* turn-off interrupts on the card */
  2921. if (ha->interrupts_on) {
  2922. vha->flags.init_done = 0;
  2923. ha->isp_ops->disable_intrs(ha);
  2924. }
  2925. qla2x00_free_irqs(vha);
  2926. qla2x00_free_fcports(vha);
  2927. qla2x00_mem_free(ha);
  2928. qla82xx_md_free(vha);
  2929. qla2x00_free_queues(ha);
  2930. }
  2931. void qla2x00_free_fcports(struct scsi_qla_host *vha)
  2932. {
  2933. fc_port_t *fcport, *tfcport;
  2934. list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
  2935. list_del(&fcport->list);
  2936. qla2x00_clear_loop_id(fcport);
  2937. kfree(fcport);
  2938. fcport = NULL;
  2939. }
  2940. }
  2941. static inline void
  2942. qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
  2943. int defer)
  2944. {
  2945. struct fc_rport *rport;
  2946. scsi_qla_host_t *base_vha;
  2947. unsigned long flags;
  2948. if (!fcport->rport)
  2949. return;
  2950. rport = fcport->rport;
  2951. if (defer) {
  2952. base_vha = pci_get_drvdata(vha->hw->pdev);
  2953. spin_lock_irqsave(vha->host->host_lock, flags);
  2954. fcport->drport = rport;
  2955. spin_unlock_irqrestore(vha->host->host_lock, flags);
  2956. qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
  2957. set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2958. qla2xxx_wake_dpc(base_vha);
  2959. } else {
  2960. int now;
  2961. if (rport)
  2962. fc_remote_port_delete(rport);
  2963. qlt_do_generation_tick(vha, &now);
  2964. qlt_fc_port_deleted(vha, fcport, now);
  2965. }
  2966. }
  2967. /*
  2968. * qla2x00_mark_device_lost Updates fcport state when device goes offline.
  2969. *
  2970. * Input: ha = adapter block pointer. fcport = port structure pointer.
  2971. *
  2972. * Return: None.
  2973. *
  2974. * Context:
  2975. */
  2976. void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
  2977. int do_login, int defer)
  2978. {
  2979. if (IS_QLAFX00(vha->hw)) {
  2980. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2981. qla2x00_schedule_rport_del(vha, fcport, defer);
  2982. return;
  2983. }
  2984. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2985. vha->vp_idx == fcport->vha->vp_idx) {
  2986. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2987. qla2x00_schedule_rport_del(vha, fcport, defer);
  2988. }
  2989. /*
  2990. * We may need to retry the login, so don't change the state of the
  2991. * port but do the retries.
  2992. */
  2993. if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
  2994. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2995. if (!do_login)
  2996. return;
  2997. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2998. if (fcport->login_retry == 0) {
  2999. fcport->login_retry = vha->hw->login_retry_count;
  3000. ql_dbg(ql_dbg_disc, vha, 0x2067,
  3001. "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
  3002. fcport->port_name, fcport->loop_id, fcport->login_retry);
  3003. }
  3004. }
  3005. /*
  3006. * qla2x00_mark_all_devices_lost
  3007. * Updates fcport state when device goes offline.
  3008. *
  3009. * Input:
  3010. * ha = adapter block pointer.
  3011. * fcport = port structure pointer.
  3012. *
  3013. * Return:
  3014. * None.
  3015. *
  3016. * Context:
  3017. */
  3018. void
  3019. qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
  3020. {
  3021. fc_port_t *fcport;
  3022. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3023. if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
  3024. continue;
  3025. /*
  3026. * No point in marking the device as lost, if the device is
  3027. * already DEAD.
  3028. */
  3029. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
  3030. continue;
  3031. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  3032. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  3033. if (defer)
  3034. qla2x00_schedule_rport_del(vha, fcport, defer);
  3035. else if (vha->vp_idx == fcport->vha->vp_idx)
  3036. qla2x00_schedule_rport_del(vha, fcport, defer);
  3037. }
  3038. }
  3039. }
  3040. /*
  3041. * qla2x00_mem_alloc
  3042. * Allocates adapter memory.
  3043. *
  3044. * Returns:
  3045. * 0 = success.
  3046. * !0 = failure.
  3047. */
  3048. static int
  3049. qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
  3050. struct req_que **req, struct rsp_que **rsp)
  3051. {
  3052. char name[16];
  3053. ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
  3054. &ha->init_cb_dma, GFP_KERNEL);
  3055. if (!ha->init_cb)
  3056. goto fail;
  3057. if (qlt_mem_alloc(ha) < 0)
  3058. goto fail_free_init_cb;
  3059. ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
  3060. qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
  3061. if (!ha->gid_list)
  3062. goto fail_free_tgt_mem;
  3063. ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
  3064. if (!ha->srb_mempool)
  3065. goto fail_free_gid_list;
  3066. if (IS_P3P_TYPE(ha)) {
  3067. /* Allocate cache for CT6 Ctx. */
  3068. if (!ctx_cachep) {
  3069. ctx_cachep = kmem_cache_create("qla2xxx_ctx",
  3070. sizeof(struct ct6_dsd), 0,
  3071. SLAB_HWCACHE_ALIGN, NULL);
  3072. if (!ctx_cachep)
  3073. goto fail_free_srb_mempool;
  3074. }
  3075. ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
  3076. ctx_cachep);
  3077. if (!ha->ctx_mempool)
  3078. goto fail_free_srb_mempool;
  3079. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
  3080. "ctx_cachep=%p ctx_mempool=%p.\n",
  3081. ctx_cachep, ha->ctx_mempool);
  3082. }
  3083. /* Get memory for cached NVRAM */
  3084. ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
  3085. if (!ha->nvram)
  3086. goto fail_free_ctx_mempool;
  3087. snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
  3088. ha->pdev->device);
  3089. ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  3090. DMA_POOL_SIZE, 8, 0);
  3091. if (!ha->s_dma_pool)
  3092. goto fail_free_nvram;
  3093. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
  3094. "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
  3095. ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
  3096. if (IS_P3P_TYPE(ha) || ql2xenabledif) {
  3097. ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  3098. DSD_LIST_DMA_POOL_SIZE, 8, 0);
  3099. if (!ha->dl_dma_pool) {
  3100. ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
  3101. "Failed to allocate memory for dl_dma_pool.\n");
  3102. goto fail_s_dma_pool;
  3103. }
  3104. ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  3105. FCP_CMND_DMA_POOL_SIZE, 8, 0);
  3106. if (!ha->fcp_cmnd_dma_pool) {
  3107. ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
  3108. "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
  3109. goto fail_dl_dma_pool;
  3110. }
  3111. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
  3112. "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
  3113. ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
  3114. }
  3115. /* Allocate memory for SNS commands */
  3116. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  3117. /* Get consistent memory allocated for SNS commands */
  3118. ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
  3119. sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
  3120. if (!ha->sns_cmd)
  3121. goto fail_dma_pool;
  3122. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
  3123. "sns_cmd: %p.\n", ha->sns_cmd);
  3124. } else {
  3125. /* Get consistent memory allocated for MS IOCB */
  3126. ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  3127. &ha->ms_iocb_dma);
  3128. if (!ha->ms_iocb)
  3129. goto fail_dma_pool;
  3130. /* Get consistent memory allocated for CT SNS commands */
  3131. ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
  3132. sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
  3133. if (!ha->ct_sns)
  3134. goto fail_free_ms_iocb;
  3135. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
  3136. "ms_iocb=%p ct_sns=%p.\n",
  3137. ha->ms_iocb, ha->ct_sns);
  3138. }
  3139. /* Allocate memory for request ring */
  3140. *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
  3141. if (!*req) {
  3142. ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
  3143. "Failed to allocate memory for req.\n");
  3144. goto fail_req;
  3145. }
  3146. (*req)->length = req_len;
  3147. (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
  3148. ((*req)->length + 1) * sizeof(request_t),
  3149. &(*req)->dma, GFP_KERNEL);
  3150. if (!(*req)->ring) {
  3151. ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
  3152. "Failed to allocate memory for req_ring.\n");
  3153. goto fail_req_ring;
  3154. }
  3155. /* Allocate memory for response ring */
  3156. *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
  3157. if (!*rsp) {
  3158. ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
  3159. "Failed to allocate memory for rsp.\n");
  3160. goto fail_rsp;
  3161. }
  3162. (*rsp)->hw = ha;
  3163. (*rsp)->length = rsp_len;
  3164. (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
  3165. ((*rsp)->length + 1) * sizeof(response_t),
  3166. &(*rsp)->dma, GFP_KERNEL);
  3167. if (!(*rsp)->ring) {
  3168. ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
  3169. "Failed to allocate memory for rsp_ring.\n");
  3170. goto fail_rsp_ring;
  3171. }
  3172. (*req)->rsp = *rsp;
  3173. (*rsp)->req = *req;
  3174. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
  3175. "req=%p req->length=%d req->ring=%p rsp=%p "
  3176. "rsp->length=%d rsp->ring=%p.\n",
  3177. *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
  3178. (*rsp)->ring);
  3179. /* Allocate memory for NVRAM data for vports */
  3180. if (ha->nvram_npiv_size) {
  3181. ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
  3182. ha->nvram_npiv_size, GFP_KERNEL);
  3183. if (!ha->npiv_info) {
  3184. ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
  3185. "Failed to allocate memory for npiv_info.\n");
  3186. goto fail_npiv_info;
  3187. }
  3188. } else
  3189. ha->npiv_info = NULL;
  3190. /* Get consistent memory allocated for EX-INIT-CB. */
  3191. if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
  3192. ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  3193. &ha->ex_init_cb_dma);
  3194. if (!ha->ex_init_cb)
  3195. goto fail_ex_init_cb;
  3196. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
  3197. "ex_init_cb=%p.\n", ha->ex_init_cb);
  3198. }
  3199. INIT_LIST_HEAD(&ha->gbl_dsd_list);
  3200. /* Get consistent memory allocated for Async Port-Database. */
  3201. if (!IS_FWI2_CAPABLE(ha)) {
  3202. ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  3203. &ha->async_pd_dma);
  3204. if (!ha->async_pd)
  3205. goto fail_async_pd;
  3206. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
  3207. "async_pd=%p.\n", ha->async_pd);
  3208. }
  3209. INIT_LIST_HEAD(&ha->vp_list);
  3210. /* Allocate memory for our loop_id bitmap */
  3211. ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
  3212. GFP_KERNEL);
  3213. if (!ha->loop_id_map)
  3214. goto fail_loop_id_map;
  3215. else {
  3216. qla2x00_set_reserved_loop_ids(ha);
  3217. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
  3218. "loop_id_map=%p.\n", ha->loop_id_map);
  3219. }
  3220. return 0;
  3221. fail_loop_id_map:
  3222. dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
  3223. fail_async_pd:
  3224. dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
  3225. fail_ex_init_cb:
  3226. kfree(ha->npiv_info);
  3227. fail_npiv_info:
  3228. dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
  3229. sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
  3230. (*rsp)->ring = NULL;
  3231. (*rsp)->dma = 0;
  3232. fail_rsp_ring:
  3233. kfree(*rsp);
  3234. fail_rsp:
  3235. dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
  3236. sizeof(request_t), (*req)->ring, (*req)->dma);
  3237. (*req)->ring = NULL;
  3238. (*req)->dma = 0;
  3239. fail_req_ring:
  3240. kfree(*req);
  3241. fail_req:
  3242. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  3243. ha->ct_sns, ha->ct_sns_dma);
  3244. ha->ct_sns = NULL;
  3245. ha->ct_sns_dma = 0;
  3246. fail_free_ms_iocb:
  3247. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  3248. ha->ms_iocb = NULL;
  3249. ha->ms_iocb_dma = 0;
  3250. if (ha->sns_cmd)
  3251. dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
  3252. ha->sns_cmd, ha->sns_cmd_dma);
  3253. fail_dma_pool:
  3254. if (IS_QLA82XX(ha) || ql2xenabledif) {
  3255. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  3256. ha->fcp_cmnd_dma_pool = NULL;
  3257. }
  3258. fail_dl_dma_pool:
  3259. if (IS_QLA82XX(ha) || ql2xenabledif) {
  3260. dma_pool_destroy(ha->dl_dma_pool);
  3261. ha->dl_dma_pool = NULL;
  3262. }
  3263. fail_s_dma_pool:
  3264. dma_pool_destroy(ha->s_dma_pool);
  3265. ha->s_dma_pool = NULL;
  3266. fail_free_nvram:
  3267. kfree(ha->nvram);
  3268. ha->nvram = NULL;
  3269. fail_free_ctx_mempool:
  3270. if (ha->ctx_mempool)
  3271. mempool_destroy(ha->ctx_mempool);
  3272. ha->ctx_mempool = NULL;
  3273. fail_free_srb_mempool:
  3274. if (ha->srb_mempool)
  3275. mempool_destroy(ha->srb_mempool);
  3276. ha->srb_mempool = NULL;
  3277. fail_free_gid_list:
  3278. dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
  3279. ha->gid_list,
  3280. ha->gid_list_dma);
  3281. ha->gid_list = NULL;
  3282. ha->gid_list_dma = 0;
  3283. fail_free_tgt_mem:
  3284. qlt_mem_free(ha);
  3285. fail_free_init_cb:
  3286. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
  3287. ha->init_cb_dma);
  3288. ha->init_cb = NULL;
  3289. ha->init_cb_dma = 0;
  3290. fail:
  3291. ql_log(ql_log_fatal, NULL, 0x0030,
  3292. "Memory allocation failure.\n");
  3293. return -ENOMEM;
  3294. }
  3295. int
  3296. qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
  3297. {
  3298. int rval;
  3299. uint16_t size, max_cnt, temp;
  3300. struct qla_hw_data *ha = vha->hw;
  3301. /* Return if we don't need to alloacate any extended logins */
  3302. if (!ql2xexlogins)
  3303. return QLA_SUCCESS;
  3304. ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
  3305. max_cnt = 0;
  3306. rval = qla_get_exlogin_status(vha, &size, &max_cnt);
  3307. if (rval != QLA_SUCCESS) {
  3308. ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
  3309. "Failed to get exlogin status.\n");
  3310. return rval;
  3311. }
  3312. temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
  3313. ha->exlogin_size = (size * temp);
  3314. ql_log(ql_log_info, vha, 0xd024,
  3315. "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
  3316. max_cnt, size, temp);
  3317. ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
  3318. ha->exlogin_size);
  3319. /* Get consistent memory for extended logins */
  3320. ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
  3321. ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
  3322. if (!ha->exlogin_buf) {
  3323. ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
  3324. "Failed to allocate memory for exlogin_buf_dma.\n");
  3325. return -ENOMEM;
  3326. }
  3327. /* Now configure the dma buffer */
  3328. rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
  3329. if (rval) {
  3330. ql_log(ql_log_fatal, vha, 0x00cf,
  3331. "Setup extended login buffer ****FAILED****.\n");
  3332. qla2x00_free_exlogin_buffer(ha);
  3333. }
  3334. return rval;
  3335. }
  3336. /*
  3337. * qla2x00_free_exlogin_buffer
  3338. *
  3339. * Input:
  3340. * ha = adapter block pointer
  3341. */
  3342. void
  3343. qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
  3344. {
  3345. if (ha->exlogin_buf) {
  3346. dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
  3347. ha->exlogin_buf, ha->exlogin_buf_dma);
  3348. ha->exlogin_buf = NULL;
  3349. ha->exlogin_size = 0;
  3350. }
  3351. }
  3352. int
  3353. qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
  3354. {
  3355. int rval;
  3356. uint16_t size, max_cnt, temp;
  3357. struct qla_hw_data *ha = vha->hw;
  3358. /* Return if we don't need to alloacate any extended logins */
  3359. if (!ql2xexchoffld)
  3360. return QLA_SUCCESS;
  3361. ql_log(ql_log_info, vha, 0xd014,
  3362. "Exchange offload count: %d.\n", ql2xexlogins);
  3363. max_cnt = 0;
  3364. rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
  3365. if (rval != QLA_SUCCESS) {
  3366. ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
  3367. "Failed to get exlogin status.\n");
  3368. return rval;
  3369. }
  3370. temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
  3371. ha->exchoffld_size = (size * temp);
  3372. ql_log(ql_log_info, vha, 0xd016,
  3373. "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
  3374. max_cnt, size, temp);
  3375. ql_log(ql_log_info, vha, 0xd017,
  3376. "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
  3377. /* Get consistent memory for extended logins */
  3378. ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
  3379. ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
  3380. if (!ha->exchoffld_buf) {
  3381. ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
  3382. "Failed to allocate memory for exchoffld_buf_dma.\n");
  3383. return -ENOMEM;
  3384. }
  3385. /* Now configure the dma buffer */
  3386. rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
  3387. if (rval) {
  3388. ql_log(ql_log_fatal, vha, 0xd02e,
  3389. "Setup exchange offload buffer ****FAILED****.\n");
  3390. qla2x00_free_exchoffld_buffer(ha);
  3391. }
  3392. return rval;
  3393. }
  3394. /*
  3395. * qla2x00_free_exchoffld_buffer
  3396. *
  3397. * Input:
  3398. * ha = adapter block pointer
  3399. */
  3400. void
  3401. qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
  3402. {
  3403. if (ha->exchoffld_buf) {
  3404. dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
  3405. ha->exchoffld_buf, ha->exchoffld_buf_dma);
  3406. ha->exchoffld_buf = NULL;
  3407. ha->exchoffld_size = 0;
  3408. }
  3409. }
  3410. /*
  3411. * qla2x00_free_fw_dump
  3412. * Frees fw dump stuff.
  3413. *
  3414. * Input:
  3415. * ha = adapter block pointer
  3416. */
  3417. static void
  3418. qla2x00_free_fw_dump(struct qla_hw_data *ha)
  3419. {
  3420. if (ha->fce)
  3421. dma_free_coherent(&ha->pdev->dev,
  3422. FCE_SIZE, ha->fce, ha->fce_dma);
  3423. if (ha->eft)
  3424. dma_free_coherent(&ha->pdev->dev,
  3425. EFT_SIZE, ha->eft, ha->eft_dma);
  3426. if (ha->fw_dump)
  3427. vfree(ha->fw_dump);
  3428. if (ha->fw_dump_template)
  3429. vfree(ha->fw_dump_template);
  3430. ha->fce = NULL;
  3431. ha->fce_dma = 0;
  3432. ha->eft = NULL;
  3433. ha->eft_dma = 0;
  3434. ha->fw_dumped = 0;
  3435. ha->fw_dump_cap_flags = 0;
  3436. ha->fw_dump_reading = 0;
  3437. ha->fw_dump = NULL;
  3438. ha->fw_dump_len = 0;
  3439. ha->fw_dump_template = NULL;
  3440. ha->fw_dump_template_len = 0;
  3441. }
  3442. /*
  3443. * qla2x00_mem_free
  3444. * Frees all adapter allocated memory.
  3445. *
  3446. * Input:
  3447. * ha = adapter block pointer.
  3448. */
  3449. static void
  3450. qla2x00_mem_free(struct qla_hw_data *ha)
  3451. {
  3452. qla2x00_free_fw_dump(ha);
  3453. if (ha->mctp_dump)
  3454. dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
  3455. ha->mctp_dump_dma);
  3456. if (ha->srb_mempool)
  3457. mempool_destroy(ha->srb_mempool);
  3458. if (ha->dcbx_tlv)
  3459. dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
  3460. ha->dcbx_tlv, ha->dcbx_tlv_dma);
  3461. if (ha->xgmac_data)
  3462. dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
  3463. ha->xgmac_data, ha->xgmac_data_dma);
  3464. if (ha->sns_cmd)
  3465. dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
  3466. ha->sns_cmd, ha->sns_cmd_dma);
  3467. if (ha->ct_sns)
  3468. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  3469. ha->ct_sns, ha->ct_sns_dma);
  3470. if (ha->sfp_data)
  3471. dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
  3472. if (ha->ms_iocb)
  3473. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  3474. if (ha->ex_init_cb)
  3475. dma_pool_free(ha->s_dma_pool,
  3476. ha->ex_init_cb, ha->ex_init_cb_dma);
  3477. if (ha->async_pd)
  3478. dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
  3479. if (ha->s_dma_pool)
  3480. dma_pool_destroy(ha->s_dma_pool);
  3481. if (ha->gid_list)
  3482. dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
  3483. ha->gid_list, ha->gid_list_dma);
  3484. if (IS_QLA82XX(ha)) {
  3485. if (!list_empty(&ha->gbl_dsd_list)) {
  3486. struct dsd_dma *dsd_ptr, *tdsd_ptr;
  3487. /* clean up allocated prev pool */
  3488. list_for_each_entry_safe(dsd_ptr,
  3489. tdsd_ptr, &ha->gbl_dsd_list, list) {
  3490. dma_pool_free(ha->dl_dma_pool,
  3491. dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
  3492. list_del(&dsd_ptr->list);
  3493. kfree(dsd_ptr);
  3494. }
  3495. }
  3496. }
  3497. if (ha->dl_dma_pool)
  3498. dma_pool_destroy(ha->dl_dma_pool);
  3499. if (ha->fcp_cmnd_dma_pool)
  3500. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  3501. if (ha->ctx_mempool)
  3502. mempool_destroy(ha->ctx_mempool);
  3503. qlt_mem_free(ha);
  3504. if (ha->init_cb)
  3505. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
  3506. ha->init_cb, ha->init_cb_dma);
  3507. vfree(ha->optrom_buffer);
  3508. kfree(ha->nvram);
  3509. kfree(ha->npiv_info);
  3510. kfree(ha->swl);
  3511. kfree(ha->loop_id_map);
  3512. ha->srb_mempool = NULL;
  3513. ha->ctx_mempool = NULL;
  3514. ha->sns_cmd = NULL;
  3515. ha->sns_cmd_dma = 0;
  3516. ha->ct_sns = NULL;
  3517. ha->ct_sns_dma = 0;
  3518. ha->ms_iocb = NULL;
  3519. ha->ms_iocb_dma = 0;
  3520. ha->init_cb = NULL;
  3521. ha->init_cb_dma = 0;
  3522. ha->ex_init_cb = NULL;
  3523. ha->ex_init_cb_dma = 0;
  3524. ha->async_pd = NULL;
  3525. ha->async_pd_dma = 0;
  3526. ha->s_dma_pool = NULL;
  3527. ha->dl_dma_pool = NULL;
  3528. ha->fcp_cmnd_dma_pool = NULL;
  3529. ha->gid_list = NULL;
  3530. ha->gid_list_dma = 0;
  3531. ha->tgt.atio_ring = NULL;
  3532. ha->tgt.atio_dma = 0;
  3533. ha->tgt.tgt_vp_map = NULL;
  3534. }
  3535. struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
  3536. struct qla_hw_data *ha)
  3537. {
  3538. struct Scsi_Host *host;
  3539. struct scsi_qla_host *vha = NULL;
  3540. host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
  3541. if (host == NULL) {
  3542. ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
  3543. "Failed to allocate host from the scsi layer, aborting.\n");
  3544. goto fail;
  3545. }
  3546. /* Clear our data area */
  3547. vha = shost_priv(host);
  3548. memset(vha, 0, sizeof(scsi_qla_host_t));
  3549. vha->host = host;
  3550. vha->host_no = host->host_no;
  3551. vha->hw = ha;
  3552. INIT_LIST_HEAD(&vha->vp_fcports);
  3553. INIT_LIST_HEAD(&vha->work_list);
  3554. INIT_LIST_HEAD(&vha->list);
  3555. INIT_LIST_HEAD(&vha->qla_cmd_list);
  3556. INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
  3557. INIT_LIST_HEAD(&vha->logo_list);
  3558. INIT_LIST_HEAD(&vha->plogi_ack_list);
  3559. spin_lock_init(&vha->work_lock);
  3560. spin_lock_init(&vha->cmd_list_lock);
  3561. init_waitqueue_head(&vha->vref_waitq);
  3562. sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
  3563. ql_dbg(ql_dbg_init, vha, 0x0041,
  3564. "Allocated the host=%p hw=%p vha=%p dev_name=%s",
  3565. vha->host, vha->hw, vha,
  3566. dev_name(&(ha->pdev->dev)));
  3567. return vha;
  3568. fail:
  3569. return vha;
  3570. }
  3571. static struct qla_work_evt *
  3572. qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
  3573. {
  3574. struct qla_work_evt *e;
  3575. uint8_t bail;
  3576. QLA_VHA_MARK_BUSY(vha, bail);
  3577. if (bail)
  3578. return NULL;
  3579. e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
  3580. if (!e) {
  3581. QLA_VHA_MARK_NOT_BUSY(vha);
  3582. return NULL;
  3583. }
  3584. INIT_LIST_HEAD(&e->list);
  3585. e->type = type;
  3586. e->flags = QLA_EVT_FLAG_FREE;
  3587. return e;
  3588. }
  3589. static int
  3590. qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
  3591. {
  3592. unsigned long flags;
  3593. spin_lock_irqsave(&vha->work_lock, flags);
  3594. list_add_tail(&e->list, &vha->work_list);
  3595. spin_unlock_irqrestore(&vha->work_lock, flags);
  3596. qla2xxx_wake_dpc(vha);
  3597. return QLA_SUCCESS;
  3598. }
  3599. int
  3600. qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
  3601. u32 data)
  3602. {
  3603. struct qla_work_evt *e;
  3604. e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
  3605. if (!e)
  3606. return QLA_FUNCTION_FAILED;
  3607. e->u.aen.code = code;
  3608. e->u.aen.data = data;
  3609. return qla2x00_post_work(vha, e);
  3610. }
  3611. int
  3612. qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
  3613. {
  3614. struct qla_work_evt *e;
  3615. e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
  3616. if (!e)
  3617. return QLA_FUNCTION_FAILED;
  3618. memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  3619. return qla2x00_post_work(vha, e);
  3620. }
  3621. #define qla2x00_post_async_work(name, type) \
  3622. int qla2x00_post_async_##name##_work( \
  3623. struct scsi_qla_host *vha, \
  3624. fc_port_t *fcport, uint16_t *data) \
  3625. { \
  3626. struct qla_work_evt *e; \
  3627. \
  3628. e = qla2x00_alloc_work(vha, type); \
  3629. if (!e) \
  3630. return QLA_FUNCTION_FAILED; \
  3631. \
  3632. e->u.logio.fcport = fcport; \
  3633. if (data) { \
  3634. e->u.logio.data[0] = data[0]; \
  3635. e->u.logio.data[1] = data[1]; \
  3636. } \
  3637. return qla2x00_post_work(vha, e); \
  3638. }
  3639. qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
  3640. qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
  3641. qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
  3642. qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
  3643. qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
  3644. qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
  3645. int
  3646. qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
  3647. {
  3648. struct qla_work_evt *e;
  3649. e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
  3650. if (!e)
  3651. return QLA_FUNCTION_FAILED;
  3652. e->u.uevent.code = code;
  3653. return qla2x00_post_work(vha, e);
  3654. }
  3655. static void
  3656. qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
  3657. {
  3658. char event_string[40];
  3659. char *envp[] = { event_string, NULL };
  3660. switch (code) {
  3661. case QLA_UEVENT_CODE_FW_DUMP:
  3662. snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
  3663. vha->host_no);
  3664. break;
  3665. default:
  3666. /* do nothing */
  3667. break;
  3668. }
  3669. kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
  3670. }
  3671. int
  3672. qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
  3673. uint32_t *data, int cnt)
  3674. {
  3675. struct qla_work_evt *e;
  3676. e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
  3677. if (!e)
  3678. return QLA_FUNCTION_FAILED;
  3679. e->u.aenfx.evtcode = evtcode;
  3680. e->u.aenfx.count = cnt;
  3681. memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
  3682. return qla2x00_post_work(vha, e);
  3683. }
  3684. void
  3685. qla2x00_do_work(struct scsi_qla_host *vha)
  3686. {
  3687. struct qla_work_evt *e, *tmp;
  3688. unsigned long flags;
  3689. LIST_HEAD(work);
  3690. spin_lock_irqsave(&vha->work_lock, flags);
  3691. list_splice_init(&vha->work_list, &work);
  3692. spin_unlock_irqrestore(&vha->work_lock, flags);
  3693. list_for_each_entry_safe(e, tmp, &work, list) {
  3694. list_del_init(&e->list);
  3695. switch (e->type) {
  3696. case QLA_EVT_AEN:
  3697. fc_host_post_event(vha->host, fc_get_event_number(),
  3698. e->u.aen.code, e->u.aen.data);
  3699. break;
  3700. case QLA_EVT_IDC_ACK:
  3701. qla81xx_idc_ack(vha, e->u.idc_ack.mb);
  3702. break;
  3703. case QLA_EVT_ASYNC_LOGIN:
  3704. qla2x00_async_login(vha, e->u.logio.fcport,
  3705. e->u.logio.data);
  3706. break;
  3707. case QLA_EVT_ASYNC_LOGIN_DONE:
  3708. qla2x00_async_login_done(vha, e->u.logio.fcport,
  3709. e->u.logio.data);
  3710. break;
  3711. case QLA_EVT_ASYNC_LOGOUT:
  3712. qla2x00_async_logout(vha, e->u.logio.fcport);
  3713. break;
  3714. case QLA_EVT_ASYNC_LOGOUT_DONE:
  3715. qla2x00_async_logout_done(vha, e->u.logio.fcport,
  3716. e->u.logio.data);
  3717. break;
  3718. case QLA_EVT_ASYNC_ADISC:
  3719. qla2x00_async_adisc(vha, e->u.logio.fcport,
  3720. e->u.logio.data);
  3721. break;
  3722. case QLA_EVT_ASYNC_ADISC_DONE:
  3723. qla2x00_async_adisc_done(vha, e->u.logio.fcport,
  3724. e->u.logio.data);
  3725. break;
  3726. case QLA_EVT_UEVENT:
  3727. qla2x00_uevent_emit(vha, e->u.uevent.code);
  3728. break;
  3729. case QLA_EVT_AENFX:
  3730. qlafx00_process_aen(vha, e);
  3731. break;
  3732. }
  3733. if (e->flags & QLA_EVT_FLAG_FREE)
  3734. kfree(e);
  3735. /* For each work completed decrement vha ref count */
  3736. QLA_VHA_MARK_NOT_BUSY(vha);
  3737. }
  3738. }
  3739. /* Relogins all the fcports of a vport
  3740. * Context: dpc thread
  3741. */
  3742. void qla2x00_relogin(struct scsi_qla_host *vha)
  3743. {
  3744. fc_port_t *fcport;
  3745. int status;
  3746. uint16_t next_loopid = 0;
  3747. struct qla_hw_data *ha = vha->hw;
  3748. uint16_t data[2];
  3749. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3750. /*
  3751. * If the port is not ONLINE then try to login
  3752. * to it if we haven't run out of retries.
  3753. */
  3754. if (atomic_read(&fcport->state) != FCS_ONLINE &&
  3755. fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
  3756. fcport->login_retry--;
  3757. if (fcport->flags & FCF_FABRIC_DEVICE) {
  3758. if (fcport->flags & FCF_FCP2_DEVICE)
  3759. ha->isp_ops->fabric_logout(vha,
  3760. fcport->loop_id,
  3761. fcport->d_id.b.domain,
  3762. fcport->d_id.b.area,
  3763. fcport->d_id.b.al_pa);
  3764. if (fcport->loop_id == FC_NO_LOOP_ID) {
  3765. fcport->loop_id = next_loopid =
  3766. ha->min_external_loopid;
  3767. status = qla2x00_find_new_loop_id(
  3768. vha, fcport);
  3769. if (status != QLA_SUCCESS) {
  3770. /* Ran out of IDs to use */
  3771. break;
  3772. }
  3773. }
  3774. if (IS_ALOGIO_CAPABLE(ha)) {
  3775. fcport->flags |= FCF_ASYNC_SENT;
  3776. data[0] = 0;
  3777. data[1] = QLA_LOGIO_LOGIN_RETRIED;
  3778. status = qla2x00_post_async_login_work(
  3779. vha, fcport, data);
  3780. if (status == QLA_SUCCESS)
  3781. continue;
  3782. /* Attempt a retry. */
  3783. status = 1;
  3784. } else {
  3785. status = qla2x00_fabric_login(vha,
  3786. fcport, &next_loopid);
  3787. if (status == QLA_SUCCESS) {
  3788. int status2;
  3789. uint8_t opts;
  3790. opts = 0;
  3791. if (fcport->flags &
  3792. FCF_FCP2_DEVICE)
  3793. opts |= BIT_1;
  3794. status2 =
  3795. qla2x00_get_port_database(
  3796. vha, fcport, opts);
  3797. if (status2 != QLA_SUCCESS)
  3798. status = 1;
  3799. }
  3800. }
  3801. } else
  3802. status = qla2x00_local_device_login(vha,
  3803. fcport);
  3804. if (status == QLA_SUCCESS) {
  3805. fcport->old_loop_id = fcport->loop_id;
  3806. ql_dbg(ql_dbg_disc, vha, 0x2003,
  3807. "Port login OK: logged in ID 0x%x.\n",
  3808. fcport->loop_id);
  3809. qla2x00_update_fcport(vha, fcport);
  3810. } else if (status == 1) {
  3811. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  3812. /* retry the login again */
  3813. ql_dbg(ql_dbg_disc, vha, 0x2007,
  3814. "Retrying %d login again loop_id 0x%x.\n",
  3815. fcport->login_retry, fcport->loop_id);
  3816. } else {
  3817. fcport->login_retry = 0;
  3818. }
  3819. if (fcport->login_retry == 0 && status != QLA_SUCCESS)
  3820. qla2x00_clear_loop_id(fcport);
  3821. }
  3822. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  3823. break;
  3824. }
  3825. }
  3826. /* Schedule work on any of the dpc-workqueues */
  3827. void
  3828. qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
  3829. {
  3830. struct qla_hw_data *ha = base_vha->hw;
  3831. switch (work_code) {
  3832. case MBA_IDC_AEN: /* 0x8200 */
  3833. if (ha->dpc_lp_wq)
  3834. queue_work(ha->dpc_lp_wq, &ha->idc_aen);
  3835. break;
  3836. case QLA83XX_NIC_CORE_RESET: /* 0x1 */
  3837. if (!ha->flags.nic_core_reset_hdlr_active) {
  3838. if (ha->dpc_hp_wq)
  3839. queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
  3840. } else
  3841. ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
  3842. "NIC Core reset is already active. Skip "
  3843. "scheduling it again.\n");
  3844. break;
  3845. case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
  3846. if (ha->dpc_hp_wq)
  3847. queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
  3848. break;
  3849. case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
  3850. if (ha->dpc_hp_wq)
  3851. queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
  3852. break;
  3853. default:
  3854. ql_log(ql_log_warn, base_vha, 0xb05f,
  3855. "Unknown work-code=0x%x.\n", work_code);
  3856. }
  3857. return;
  3858. }
  3859. /* Work: Perform NIC Core Unrecoverable state handling */
  3860. void
  3861. qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
  3862. {
  3863. struct qla_hw_data *ha =
  3864. container_of(work, struct qla_hw_data, nic_core_unrecoverable);
  3865. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  3866. uint32_t dev_state = 0;
  3867. qla83xx_idc_lock(base_vha, 0);
  3868. qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
  3869. qla83xx_reset_ownership(base_vha);
  3870. if (ha->flags.nic_core_reset_owner) {
  3871. ha->flags.nic_core_reset_owner = 0;
  3872. qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
  3873. QLA8XXX_DEV_FAILED);
  3874. ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
  3875. qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
  3876. }
  3877. qla83xx_idc_unlock(base_vha, 0);
  3878. }
  3879. /* Work: Execute IDC state handler */
  3880. void
  3881. qla83xx_idc_state_handler_work(struct work_struct *work)
  3882. {
  3883. struct qla_hw_data *ha =
  3884. container_of(work, struct qla_hw_data, idc_state_handler);
  3885. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  3886. uint32_t dev_state = 0;
  3887. qla83xx_idc_lock(base_vha, 0);
  3888. qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
  3889. if (dev_state == QLA8XXX_DEV_FAILED ||
  3890. dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
  3891. qla83xx_idc_state_handler(base_vha);
  3892. qla83xx_idc_unlock(base_vha, 0);
  3893. }
  3894. static int
  3895. qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
  3896. {
  3897. int rval = QLA_SUCCESS;
  3898. unsigned long heart_beat_wait = jiffies + (1 * HZ);
  3899. uint32_t heart_beat_counter1, heart_beat_counter2;
  3900. do {
  3901. if (time_after(jiffies, heart_beat_wait)) {
  3902. ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
  3903. "Nic Core f/w is not alive.\n");
  3904. rval = QLA_FUNCTION_FAILED;
  3905. break;
  3906. }
  3907. qla83xx_idc_lock(base_vha, 0);
  3908. qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
  3909. &heart_beat_counter1);
  3910. qla83xx_idc_unlock(base_vha, 0);
  3911. msleep(100);
  3912. qla83xx_idc_lock(base_vha, 0);
  3913. qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
  3914. &heart_beat_counter2);
  3915. qla83xx_idc_unlock(base_vha, 0);
  3916. } while (heart_beat_counter1 == heart_beat_counter2);
  3917. return rval;
  3918. }
  3919. /* Work: Perform NIC Core Reset handling */
  3920. void
  3921. qla83xx_nic_core_reset_work(struct work_struct *work)
  3922. {
  3923. struct qla_hw_data *ha =
  3924. container_of(work, struct qla_hw_data, nic_core_reset);
  3925. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  3926. uint32_t dev_state = 0;
  3927. if (IS_QLA2031(ha)) {
  3928. if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
  3929. ql_log(ql_log_warn, base_vha, 0xb081,
  3930. "Failed to dump mctp\n");
  3931. return;
  3932. }
  3933. if (!ha->flags.nic_core_reset_hdlr_active) {
  3934. if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
  3935. qla83xx_idc_lock(base_vha, 0);
  3936. qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
  3937. &dev_state);
  3938. qla83xx_idc_unlock(base_vha, 0);
  3939. if (dev_state != QLA8XXX_DEV_NEED_RESET) {
  3940. ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
  3941. "Nic Core f/w is alive.\n");
  3942. return;
  3943. }
  3944. }
  3945. ha->flags.nic_core_reset_hdlr_active = 1;
  3946. if (qla83xx_nic_core_reset(base_vha)) {
  3947. /* NIC Core reset failed. */
  3948. ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
  3949. "NIC Core reset failed.\n");
  3950. }
  3951. ha->flags.nic_core_reset_hdlr_active = 0;
  3952. }
  3953. }
  3954. /* Work: Handle 8200 IDC aens */
  3955. void
  3956. qla83xx_service_idc_aen(struct work_struct *work)
  3957. {
  3958. struct qla_hw_data *ha =
  3959. container_of(work, struct qla_hw_data, idc_aen);
  3960. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  3961. uint32_t dev_state, idc_control;
  3962. qla83xx_idc_lock(base_vha, 0);
  3963. qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
  3964. qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
  3965. qla83xx_idc_unlock(base_vha, 0);
  3966. if (dev_state == QLA8XXX_DEV_NEED_RESET) {
  3967. if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
  3968. ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
  3969. "Application requested NIC Core Reset.\n");
  3970. qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
  3971. } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
  3972. QLA_SUCCESS) {
  3973. ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
  3974. "Other protocol driver requested NIC Core Reset.\n");
  3975. qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
  3976. }
  3977. } else if (dev_state == QLA8XXX_DEV_FAILED ||
  3978. dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
  3979. qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
  3980. }
  3981. }
  3982. static void
  3983. qla83xx_wait_logic(void)
  3984. {
  3985. int i;
  3986. /* Yield CPU */
  3987. if (!in_interrupt()) {
  3988. /*
  3989. * Wait about 200ms before retrying again.
  3990. * This controls the number of retries for single
  3991. * lock operation.
  3992. */
  3993. msleep(100);
  3994. schedule();
  3995. } else {
  3996. for (i = 0; i < 20; i++)
  3997. cpu_relax(); /* This a nop instr on i386 */
  3998. }
  3999. }
  4000. static int
  4001. qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
  4002. {
  4003. int rval;
  4004. uint32_t data;
  4005. uint32_t idc_lck_rcvry_stage_mask = 0x3;
  4006. uint32_t idc_lck_rcvry_owner_mask = 0x3c;
  4007. struct qla_hw_data *ha = base_vha->hw;
  4008. ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
  4009. "Trying force recovery of the IDC lock.\n");
  4010. rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
  4011. if (rval)
  4012. return rval;
  4013. if ((data & idc_lck_rcvry_stage_mask) > 0) {
  4014. return QLA_SUCCESS;
  4015. } else {
  4016. data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
  4017. rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
  4018. data);
  4019. if (rval)
  4020. return rval;
  4021. msleep(200);
  4022. rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
  4023. &data);
  4024. if (rval)
  4025. return rval;
  4026. if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
  4027. data &= (IDC_LOCK_RECOVERY_STAGE2 |
  4028. ~(idc_lck_rcvry_stage_mask));
  4029. rval = qla83xx_wr_reg(base_vha,
  4030. QLA83XX_IDC_LOCK_RECOVERY, data);
  4031. if (rval)
  4032. return rval;
  4033. /* Forcefully perform IDC UnLock */
  4034. rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
  4035. &data);
  4036. if (rval)
  4037. return rval;
  4038. /* Clear lock-id by setting 0xff */
  4039. rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
  4040. 0xff);
  4041. if (rval)
  4042. return rval;
  4043. /* Clear lock-recovery by setting 0x0 */
  4044. rval = qla83xx_wr_reg(base_vha,
  4045. QLA83XX_IDC_LOCK_RECOVERY, 0x0);
  4046. if (rval)
  4047. return rval;
  4048. } else
  4049. return QLA_SUCCESS;
  4050. }
  4051. return rval;
  4052. }
  4053. static int
  4054. qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
  4055. {
  4056. int rval = QLA_SUCCESS;
  4057. uint32_t o_drv_lockid, n_drv_lockid;
  4058. unsigned long lock_recovery_timeout;
  4059. lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
  4060. retry_lockid:
  4061. rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
  4062. if (rval)
  4063. goto exit;
  4064. /* MAX wait time before forcing IDC Lock recovery = 2 secs */
  4065. if (time_after_eq(jiffies, lock_recovery_timeout)) {
  4066. if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
  4067. return QLA_SUCCESS;
  4068. else
  4069. return QLA_FUNCTION_FAILED;
  4070. }
  4071. rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
  4072. if (rval)
  4073. goto exit;
  4074. if (o_drv_lockid == n_drv_lockid) {
  4075. qla83xx_wait_logic();
  4076. goto retry_lockid;
  4077. } else
  4078. return QLA_SUCCESS;
  4079. exit:
  4080. return rval;
  4081. }
  4082. void
  4083. qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
  4084. {
  4085. uint16_t options = (requester_id << 15) | BIT_6;
  4086. uint32_t data;
  4087. uint32_t lock_owner;
  4088. struct qla_hw_data *ha = base_vha->hw;
  4089. /* IDC-lock implementation using driver-lock/lock-id remote registers */
  4090. retry_lock:
  4091. if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
  4092. == QLA_SUCCESS) {
  4093. if (data) {
  4094. /* Setting lock-id to our function-number */
  4095. qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
  4096. ha->portnum);
  4097. } else {
  4098. qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
  4099. &lock_owner);
  4100. ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
  4101. "Failed to acquire IDC lock, acquired by %d, "
  4102. "retrying...\n", lock_owner);
  4103. /* Retry/Perform IDC-Lock recovery */
  4104. if (qla83xx_idc_lock_recovery(base_vha)
  4105. == QLA_SUCCESS) {
  4106. qla83xx_wait_logic();
  4107. goto retry_lock;
  4108. } else
  4109. ql_log(ql_log_warn, base_vha, 0xb075,
  4110. "IDC Lock recovery FAILED.\n");
  4111. }
  4112. }
  4113. return;
  4114. /* XXX: IDC-lock implementation using access-control mbx */
  4115. retry_lock2:
  4116. if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
  4117. ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
  4118. "Failed to acquire IDC lock. retrying...\n");
  4119. /* Retry/Perform IDC-Lock recovery */
  4120. if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
  4121. qla83xx_wait_logic();
  4122. goto retry_lock2;
  4123. } else
  4124. ql_log(ql_log_warn, base_vha, 0xb076,
  4125. "IDC Lock recovery FAILED.\n");
  4126. }
  4127. return;
  4128. }
  4129. void
  4130. qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
  4131. {
  4132. #if 0
  4133. uint16_t options = (requester_id << 15) | BIT_7;
  4134. #endif
  4135. uint16_t retry;
  4136. uint32_t data;
  4137. struct qla_hw_data *ha = base_vha->hw;
  4138. /* IDC-unlock implementation using driver-unlock/lock-id
  4139. * remote registers
  4140. */
  4141. retry = 0;
  4142. retry_unlock:
  4143. if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
  4144. == QLA_SUCCESS) {
  4145. if (data == ha->portnum) {
  4146. qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
  4147. /* Clearing lock-id by setting 0xff */
  4148. qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
  4149. } else if (retry < 10) {
  4150. /* SV: XXX: IDC unlock retrying needed here? */
  4151. /* Retry for IDC-unlock */
  4152. qla83xx_wait_logic();
  4153. retry++;
  4154. ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
  4155. "Failed to release IDC lock, retrying=%d\n", retry);
  4156. goto retry_unlock;
  4157. }
  4158. } else if (retry < 10) {
  4159. /* Retry for IDC-unlock */
  4160. qla83xx_wait_logic();
  4161. retry++;
  4162. ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
  4163. "Failed to read drv-lockid, retrying=%d\n", retry);
  4164. goto retry_unlock;
  4165. }
  4166. return;
  4167. #if 0
  4168. /* XXX: IDC-unlock implementation using access-control mbx */
  4169. retry = 0;
  4170. retry_unlock2:
  4171. if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
  4172. if (retry < 10) {
  4173. /* Retry for IDC-unlock */
  4174. qla83xx_wait_logic();
  4175. retry++;
  4176. ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
  4177. "Failed to release IDC lock, retrying=%d\n", retry);
  4178. goto retry_unlock2;
  4179. }
  4180. }
  4181. return;
  4182. #endif
  4183. }
  4184. int
  4185. __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
  4186. {
  4187. int rval = QLA_SUCCESS;
  4188. struct qla_hw_data *ha = vha->hw;
  4189. uint32_t drv_presence;
  4190. rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
  4191. if (rval == QLA_SUCCESS) {
  4192. drv_presence |= (1 << ha->portnum);
  4193. rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
  4194. drv_presence);
  4195. }
  4196. return rval;
  4197. }
  4198. int
  4199. qla83xx_set_drv_presence(scsi_qla_host_t *vha)
  4200. {
  4201. int rval = QLA_SUCCESS;
  4202. qla83xx_idc_lock(vha, 0);
  4203. rval = __qla83xx_set_drv_presence(vha);
  4204. qla83xx_idc_unlock(vha, 0);
  4205. return rval;
  4206. }
  4207. int
  4208. __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
  4209. {
  4210. int rval = QLA_SUCCESS;
  4211. struct qla_hw_data *ha = vha->hw;
  4212. uint32_t drv_presence;
  4213. rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
  4214. if (rval == QLA_SUCCESS) {
  4215. drv_presence &= ~(1 << ha->portnum);
  4216. rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
  4217. drv_presence);
  4218. }
  4219. return rval;
  4220. }
  4221. int
  4222. qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
  4223. {
  4224. int rval = QLA_SUCCESS;
  4225. qla83xx_idc_lock(vha, 0);
  4226. rval = __qla83xx_clear_drv_presence(vha);
  4227. qla83xx_idc_unlock(vha, 0);
  4228. return rval;
  4229. }
  4230. static void
  4231. qla83xx_need_reset_handler(scsi_qla_host_t *vha)
  4232. {
  4233. struct qla_hw_data *ha = vha->hw;
  4234. uint32_t drv_ack, drv_presence;
  4235. unsigned long ack_timeout;
  4236. /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
  4237. ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
  4238. while (1) {
  4239. qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
  4240. qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
  4241. if ((drv_ack & drv_presence) == drv_presence)
  4242. break;
  4243. if (time_after_eq(jiffies, ack_timeout)) {
  4244. ql_log(ql_log_warn, vha, 0xb067,
  4245. "RESET ACK TIMEOUT! drv_presence=0x%x "
  4246. "drv_ack=0x%x\n", drv_presence, drv_ack);
  4247. /*
  4248. * The function(s) which did not ack in time are forced
  4249. * to withdraw any further participation in the IDC
  4250. * reset.
  4251. */
  4252. if (drv_ack != drv_presence)
  4253. qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
  4254. drv_ack);
  4255. break;
  4256. }
  4257. qla83xx_idc_unlock(vha, 0);
  4258. msleep(1000);
  4259. qla83xx_idc_lock(vha, 0);
  4260. }
  4261. qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
  4262. ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
  4263. }
  4264. static int
  4265. qla83xx_device_bootstrap(scsi_qla_host_t *vha)
  4266. {
  4267. int rval = QLA_SUCCESS;
  4268. uint32_t idc_control;
  4269. qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
  4270. ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
  4271. /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
  4272. __qla83xx_get_idc_control(vha, &idc_control);
  4273. idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
  4274. __qla83xx_set_idc_control(vha, 0);
  4275. qla83xx_idc_unlock(vha, 0);
  4276. rval = qla83xx_restart_nic_firmware(vha);
  4277. qla83xx_idc_lock(vha, 0);
  4278. if (rval != QLA_SUCCESS) {
  4279. ql_log(ql_log_fatal, vha, 0xb06a,
  4280. "Failed to restart NIC f/w.\n");
  4281. qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
  4282. ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
  4283. } else {
  4284. ql_dbg(ql_dbg_p3p, vha, 0xb06c,
  4285. "Success in restarting nic f/w.\n");
  4286. qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
  4287. ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
  4288. }
  4289. return rval;
  4290. }
  4291. /* Assumes idc_lock always held on entry */
  4292. int
  4293. qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
  4294. {
  4295. struct qla_hw_data *ha = base_vha->hw;
  4296. int rval = QLA_SUCCESS;
  4297. unsigned long dev_init_timeout;
  4298. uint32_t dev_state;
  4299. /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
  4300. dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
  4301. while (1) {
  4302. if (time_after_eq(jiffies, dev_init_timeout)) {
  4303. ql_log(ql_log_warn, base_vha, 0xb06e,
  4304. "Initialization TIMEOUT!\n");
  4305. /* Init timeout. Disable further NIC Core
  4306. * communication.
  4307. */
  4308. qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
  4309. QLA8XXX_DEV_FAILED);
  4310. ql_log(ql_log_info, base_vha, 0xb06f,
  4311. "HW State: FAILED.\n");
  4312. }
  4313. qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
  4314. switch (dev_state) {
  4315. case QLA8XXX_DEV_READY:
  4316. if (ha->flags.nic_core_reset_owner)
  4317. qla83xx_idc_audit(base_vha,
  4318. IDC_AUDIT_COMPLETION);
  4319. ha->flags.nic_core_reset_owner = 0;
  4320. ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
  4321. "Reset_owner reset by 0x%x.\n",
  4322. ha->portnum);
  4323. goto exit;
  4324. case QLA8XXX_DEV_COLD:
  4325. if (ha->flags.nic_core_reset_owner)
  4326. rval = qla83xx_device_bootstrap(base_vha);
  4327. else {
  4328. /* Wait for AEN to change device-state */
  4329. qla83xx_idc_unlock(base_vha, 0);
  4330. msleep(1000);
  4331. qla83xx_idc_lock(base_vha, 0);
  4332. }
  4333. break;
  4334. case QLA8XXX_DEV_INITIALIZING:
  4335. /* Wait for AEN to change device-state */
  4336. qla83xx_idc_unlock(base_vha, 0);
  4337. msleep(1000);
  4338. qla83xx_idc_lock(base_vha, 0);
  4339. break;
  4340. case QLA8XXX_DEV_NEED_RESET:
  4341. if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
  4342. qla83xx_need_reset_handler(base_vha);
  4343. else {
  4344. /* Wait for AEN to change device-state */
  4345. qla83xx_idc_unlock(base_vha, 0);
  4346. msleep(1000);
  4347. qla83xx_idc_lock(base_vha, 0);
  4348. }
  4349. /* reset timeout value after need reset handler */
  4350. dev_init_timeout = jiffies +
  4351. (ha->fcoe_dev_init_timeout * HZ);
  4352. break;
  4353. case QLA8XXX_DEV_NEED_QUIESCENT:
  4354. /* XXX: DEBUG for now */
  4355. qla83xx_idc_unlock(base_vha, 0);
  4356. msleep(1000);
  4357. qla83xx_idc_lock(base_vha, 0);
  4358. break;
  4359. case QLA8XXX_DEV_QUIESCENT:
  4360. /* XXX: DEBUG for now */
  4361. if (ha->flags.quiesce_owner)
  4362. goto exit;
  4363. qla83xx_idc_unlock(base_vha, 0);
  4364. msleep(1000);
  4365. qla83xx_idc_lock(base_vha, 0);
  4366. dev_init_timeout = jiffies +
  4367. (ha->fcoe_dev_init_timeout * HZ);
  4368. break;
  4369. case QLA8XXX_DEV_FAILED:
  4370. if (ha->flags.nic_core_reset_owner)
  4371. qla83xx_idc_audit(base_vha,
  4372. IDC_AUDIT_COMPLETION);
  4373. ha->flags.nic_core_reset_owner = 0;
  4374. __qla83xx_clear_drv_presence(base_vha);
  4375. qla83xx_idc_unlock(base_vha, 0);
  4376. qla8xxx_dev_failed_handler(base_vha);
  4377. rval = QLA_FUNCTION_FAILED;
  4378. qla83xx_idc_lock(base_vha, 0);
  4379. goto exit;
  4380. case QLA8XXX_BAD_VALUE:
  4381. qla83xx_idc_unlock(base_vha, 0);
  4382. msleep(1000);
  4383. qla83xx_idc_lock(base_vha, 0);
  4384. break;
  4385. default:
  4386. ql_log(ql_log_warn, base_vha, 0xb071,
  4387. "Unknown Device State: %x.\n", dev_state);
  4388. qla83xx_idc_unlock(base_vha, 0);
  4389. qla8xxx_dev_failed_handler(base_vha);
  4390. rval = QLA_FUNCTION_FAILED;
  4391. qla83xx_idc_lock(base_vha, 0);
  4392. goto exit;
  4393. }
  4394. }
  4395. exit:
  4396. return rval;
  4397. }
  4398. void
  4399. qla2x00_disable_board_on_pci_error(struct work_struct *work)
  4400. {
  4401. struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
  4402. board_disable);
  4403. struct pci_dev *pdev = ha->pdev;
  4404. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  4405. /* if UNLOAD flag is already set, then continue unload,
  4406. * where it was set first.
  4407. */
  4408. if (test_bit(UNLOADING, &base_vha->dpc_flags))
  4409. return;
  4410. ql_log(ql_log_warn, base_vha, 0x015b,
  4411. "Disabling adapter.\n");
  4412. set_bit(UNLOADING, &base_vha->dpc_flags);
  4413. qla2x00_delete_all_vps(ha, base_vha);
  4414. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  4415. qla2x00_dfs_remove(base_vha);
  4416. qla84xx_put_chip(base_vha);
  4417. if (base_vha->timer_active)
  4418. qla2x00_stop_timer(base_vha);
  4419. base_vha->flags.online = 0;
  4420. qla2x00_destroy_deferred_work(ha);
  4421. /*
  4422. * Do not try to stop beacon blink as it will issue a mailbox
  4423. * command.
  4424. */
  4425. qla2x00_free_sysfs_attr(base_vha, false);
  4426. fc_remove_host(base_vha->host);
  4427. scsi_remove_host(base_vha->host);
  4428. base_vha->flags.init_done = 0;
  4429. qla25xx_delete_queues(base_vha);
  4430. qla2x00_free_irqs(base_vha);
  4431. qla2x00_free_fcports(base_vha);
  4432. qla2x00_mem_free(ha);
  4433. qla82xx_md_free(base_vha);
  4434. qla2x00_free_queues(ha);
  4435. qla2x00_unmap_iobases(ha);
  4436. pci_release_selected_regions(ha->pdev, ha->bars);
  4437. pci_disable_pcie_error_reporting(pdev);
  4438. pci_disable_device(pdev);
  4439. /*
  4440. * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
  4441. */
  4442. }
  4443. /**************************************************************************
  4444. * qla2x00_do_dpc
  4445. * This kernel thread is a task that is schedule by the interrupt handler
  4446. * to perform the background processing for interrupts.
  4447. *
  4448. * Notes:
  4449. * This task always run in the context of a kernel thread. It
  4450. * is kick-off by the driver's detect code and starts up
  4451. * up one per adapter. It immediately goes to sleep and waits for
  4452. * some fibre event. When either the interrupt handler or
  4453. * the timer routine detects a event it will one of the task
  4454. * bits then wake us up.
  4455. **************************************************************************/
  4456. static int
  4457. qla2x00_do_dpc(void *data)
  4458. {
  4459. scsi_qla_host_t *base_vha;
  4460. struct qla_hw_data *ha;
  4461. ha = (struct qla_hw_data *)data;
  4462. base_vha = pci_get_drvdata(ha->pdev);
  4463. set_user_nice(current, MIN_NICE);
  4464. set_current_state(TASK_INTERRUPTIBLE);
  4465. while (!kthread_should_stop()) {
  4466. ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
  4467. "DPC handler sleeping.\n");
  4468. schedule();
  4469. if (!base_vha->flags.init_done || ha->flags.mbox_busy)
  4470. goto end_loop;
  4471. if (ha->flags.eeh_busy) {
  4472. ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
  4473. "eeh_busy=%d.\n", ha->flags.eeh_busy);
  4474. goto end_loop;
  4475. }
  4476. ha->dpc_active = 1;
  4477. ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
  4478. "DPC handler waking up, dpc_flags=0x%lx.\n",
  4479. base_vha->dpc_flags);
  4480. if (test_bit(UNLOADING, &base_vha->dpc_flags))
  4481. break;
  4482. qla2x00_do_work(base_vha);
  4483. if (IS_P3P_TYPE(ha)) {
  4484. if (IS_QLA8044(ha)) {
  4485. if (test_and_clear_bit(ISP_UNRECOVERABLE,
  4486. &base_vha->dpc_flags)) {
  4487. qla8044_idc_lock(ha);
  4488. qla8044_wr_direct(base_vha,
  4489. QLA8044_CRB_DEV_STATE_INDEX,
  4490. QLA8XXX_DEV_FAILED);
  4491. qla8044_idc_unlock(ha);
  4492. ql_log(ql_log_info, base_vha, 0x4004,
  4493. "HW State: FAILED.\n");
  4494. qla8044_device_state_handler(base_vha);
  4495. continue;
  4496. }
  4497. } else {
  4498. if (test_and_clear_bit(ISP_UNRECOVERABLE,
  4499. &base_vha->dpc_flags)) {
  4500. qla82xx_idc_lock(ha);
  4501. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  4502. QLA8XXX_DEV_FAILED);
  4503. qla82xx_idc_unlock(ha);
  4504. ql_log(ql_log_info, base_vha, 0x0151,
  4505. "HW State: FAILED.\n");
  4506. qla82xx_device_state_handler(base_vha);
  4507. continue;
  4508. }
  4509. }
  4510. if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
  4511. &base_vha->dpc_flags)) {
  4512. ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
  4513. "FCoE context reset scheduled.\n");
  4514. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  4515. &base_vha->dpc_flags))) {
  4516. if (qla82xx_fcoe_ctx_reset(base_vha)) {
  4517. /* FCoE-ctx reset failed.
  4518. * Escalate to chip-reset
  4519. */
  4520. set_bit(ISP_ABORT_NEEDED,
  4521. &base_vha->dpc_flags);
  4522. }
  4523. clear_bit(ABORT_ISP_ACTIVE,
  4524. &base_vha->dpc_flags);
  4525. }
  4526. ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
  4527. "FCoE context reset end.\n");
  4528. }
  4529. } else if (IS_QLAFX00(ha)) {
  4530. if (test_and_clear_bit(ISP_UNRECOVERABLE,
  4531. &base_vha->dpc_flags)) {
  4532. ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
  4533. "Firmware Reset Recovery\n");
  4534. if (qlafx00_reset_initialize(base_vha)) {
  4535. /* Failed. Abort isp later. */
  4536. if (!test_bit(UNLOADING,
  4537. &base_vha->dpc_flags)) {
  4538. set_bit(ISP_UNRECOVERABLE,
  4539. &base_vha->dpc_flags);
  4540. ql_dbg(ql_dbg_dpc, base_vha,
  4541. 0x4021,
  4542. "Reset Recovery Failed\n");
  4543. }
  4544. }
  4545. }
  4546. if (test_and_clear_bit(FX00_TARGET_SCAN,
  4547. &base_vha->dpc_flags)) {
  4548. ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
  4549. "ISPFx00 Target Scan scheduled\n");
  4550. if (qlafx00_rescan_isp(base_vha)) {
  4551. if (!test_bit(UNLOADING,
  4552. &base_vha->dpc_flags))
  4553. set_bit(ISP_UNRECOVERABLE,
  4554. &base_vha->dpc_flags);
  4555. ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
  4556. "ISPFx00 Target Scan Failed\n");
  4557. }
  4558. ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
  4559. "ISPFx00 Target Scan End\n");
  4560. }
  4561. if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
  4562. &base_vha->dpc_flags)) {
  4563. ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
  4564. "ISPFx00 Host Info resend scheduled\n");
  4565. qlafx00_fx_disc(base_vha,
  4566. &base_vha->hw->mr.fcport,
  4567. FXDISC_REG_HOST_INFO);
  4568. }
  4569. }
  4570. if (test_and_clear_bit(ISP_ABORT_NEEDED,
  4571. &base_vha->dpc_flags)) {
  4572. ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
  4573. "ISP abort scheduled.\n");
  4574. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  4575. &base_vha->dpc_flags))) {
  4576. if (ha->isp_ops->abort_isp(base_vha)) {
  4577. /* failed. retry later */
  4578. set_bit(ISP_ABORT_NEEDED,
  4579. &base_vha->dpc_flags);
  4580. }
  4581. clear_bit(ABORT_ISP_ACTIVE,
  4582. &base_vha->dpc_flags);
  4583. }
  4584. ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
  4585. "ISP abort end.\n");
  4586. }
  4587. if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
  4588. &base_vha->dpc_flags)) {
  4589. qla2x00_update_fcports(base_vha);
  4590. }
  4591. if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
  4592. int ret;
  4593. ret = qla2x00_send_change_request(base_vha, 0x3, 0);
  4594. if (ret != QLA_SUCCESS)
  4595. ql_log(ql_log_warn, base_vha, 0x121,
  4596. "Failed to enable receiving of RSCN "
  4597. "requests: 0x%x.\n", ret);
  4598. clear_bit(SCR_PENDING, &base_vha->dpc_flags);
  4599. }
  4600. if (IS_QLAFX00(ha))
  4601. goto loop_resync_check;
  4602. if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
  4603. ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
  4604. "Quiescence mode scheduled.\n");
  4605. if (IS_P3P_TYPE(ha)) {
  4606. if (IS_QLA82XX(ha))
  4607. qla82xx_device_state_handler(base_vha);
  4608. if (IS_QLA8044(ha))
  4609. qla8044_device_state_handler(base_vha);
  4610. clear_bit(ISP_QUIESCE_NEEDED,
  4611. &base_vha->dpc_flags);
  4612. if (!ha->flags.quiesce_owner) {
  4613. qla2x00_perform_loop_resync(base_vha);
  4614. if (IS_QLA82XX(ha)) {
  4615. qla82xx_idc_lock(ha);
  4616. qla82xx_clear_qsnt_ready(
  4617. base_vha);
  4618. qla82xx_idc_unlock(ha);
  4619. } else if (IS_QLA8044(ha)) {
  4620. qla8044_idc_lock(ha);
  4621. qla8044_clear_qsnt_ready(
  4622. base_vha);
  4623. qla8044_idc_unlock(ha);
  4624. }
  4625. }
  4626. } else {
  4627. clear_bit(ISP_QUIESCE_NEEDED,
  4628. &base_vha->dpc_flags);
  4629. qla2x00_quiesce_io(base_vha);
  4630. }
  4631. ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
  4632. "Quiescence mode end.\n");
  4633. }
  4634. if (test_and_clear_bit(RESET_MARKER_NEEDED,
  4635. &base_vha->dpc_flags) &&
  4636. (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
  4637. ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
  4638. "Reset marker scheduled.\n");
  4639. qla2x00_rst_aen(base_vha);
  4640. clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
  4641. ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
  4642. "Reset marker end.\n");
  4643. }
  4644. /* Retry each device up to login retry count */
  4645. if ((test_and_clear_bit(RELOGIN_NEEDED,
  4646. &base_vha->dpc_flags)) &&
  4647. !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
  4648. atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
  4649. ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
  4650. "Relogin scheduled.\n");
  4651. qla2x00_relogin(base_vha);
  4652. ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
  4653. "Relogin end.\n");
  4654. }
  4655. loop_resync_check:
  4656. if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
  4657. &base_vha->dpc_flags)) {
  4658. ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
  4659. "Loop resync scheduled.\n");
  4660. if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
  4661. &base_vha->dpc_flags))) {
  4662. qla2x00_loop_resync(base_vha);
  4663. clear_bit(LOOP_RESYNC_ACTIVE,
  4664. &base_vha->dpc_flags);
  4665. }
  4666. ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
  4667. "Loop resync end.\n");
  4668. }
  4669. if (IS_QLAFX00(ha))
  4670. goto intr_on_check;
  4671. if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
  4672. atomic_read(&base_vha->loop_state) == LOOP_READY) {
  4673. clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
  4674. qla2xxx_flash_npiv_conf(base_vha);
  4675. }
  4676. intr_on_check:
  4677. if (!ha->interrupts_on)
  4678. ha->isp_ops->enable_intrs(ha);
  4679. if (test_and_clear_bit(BEACON_BLINK_NEEDED,
  4680. &base_vha->dpc_flags)) {
  4681. if (ha->beacon_blink_led == 1)
  4682. ha->isp_ops->beacon_blink(base_vha);
  4683. }
  4684. if (!IS_QLAFX00(ha))
  4685. qla2x00_do_dpc_all_vps(base_vha);
  4686. ha->dpc_active = 0;
  4687. end_loop:
  4688. set_current_state(TASK_INTERRUPTIBLE);
  4689. } /* End of while(1) */
  4690. __set_current_state(TASK_RUNNING);
  4691. ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
  4692. "DPC handler exiting.\n");
  4693. /*
  4694. * Make sure that nobody tries to wake us up again.
  4695. */
  4696. ha->dpc_active = 0;
  4697. /* Cleanup any residual CTX SRBs. */
  4698. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  4699. return 0;
  4700. }
  4701. void
  4702. qla2xxx_wake_dpc(struct scsi_qla_host *vha)
  4703. {
  4704. struct qla_hw_data *ha = vha->hw;
  4705. struct task_struct *t = ha->dpc_thread;
  4706. if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
  4707. wake_up_process(t);
  4708. }
  4709. /*
  4710. * qla2x00_rst_aen
  4711. * Processes asynchronous reset.
  4712. *
  4713. * Input:
  4714. * ha = adapter block pointer.
  4715. */
  4716. static void
  4717. qla2x00_rst_aen(scsi_qla_host_t *vha)
  4718. {
  4719. if (vha->flags.online && !vha->flags.reset_active &&
  4720. !atomic_read(&vha->loop_down_timer) &&
  4721. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
  4722. do {
  4723. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4724. /*
  4725. * Issue marker command only when we are going to start
  4726. * the I/O.
  4727. */
  4728. vha->marker_needed = 1;
  4729. } while (!atomic_read(&vha->loop_down_timer) &&
  4730. (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
  4731. }
  4732. }
  4733. /**************************************************************************
  4734. * qla2x00_timer
  4735. *
  4736. * Description:
  4737. * One second timer
  4738. *
  4739. * Context: Interrupt
  4740. ***************************************************************************/
  4741. void
  4742. qla2x00_timer(scsi_qla_host_t *vha)
  4743. {
  4744. unsigned long cpu_flags = 0;
  4745. int start_dpc = 0;
  4746. int index;
  4747. srb_t *sp;
  4748. uint16_t w;
  4749. struct qla_hw_data *ha = vha->hw;
  4750. struct req_que *req;
  4751. if (ha->flags.eeh_busy) {
  4752. ql_dbg(ql_dbg_timer, vha, 0x6000,
  4753. "EEH = %d, restarting timer.\n",
  4754. ha->flags.eeh_busy);
  4755. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  4756. return;
  4757. }
  4758. /*
  4759. * Hardware read to raise pending EEH errors during mailbox waits. If
  4760. * the read returns -1 then disable the board.
  4761. */
  4762. if (!pci_channel_offline(ha->pdev)) {
  4763. pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
  4764. qla2x00_check_reg16_for_disconnect(vha, w);
  4765. }
  4766. /* Make sure qla82xx_watchdog is run only for physical port */
  4767. if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
  4768. if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
  4769. start_dpc++;
  4770. if (IS_QLA82XX(ha))
  4771. qla82xx_watchdog(vha);
  4772. else if (IS_QLA8044(ha))
  4773. qla8044_watchdog(vha);
  4774. }
  4775. if (!vha->vp_idx && IS_QLAFX00(ha))
  4776. qlafx00_timer_routine(vha);
  4777. /* Loop down handler. */
  4778. if (atomic_read(&vha->loop_down_timer) > 0 &&
  4779. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
  4780. !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
  4781. && vha->flags.online) {
  4782. if (atomic_read(&vha->loop_down_timer) ==
  4783. vha->loop_down_abort_time) {
  4784. ql_log(ql_log_info, vha, 0x6008,
  4785. "Loop down - aborting the queues before time expires.\n");
  4786. if (!IS_QLA2100(ha) && vha->link_down_timeout)
  4787. atomic_set(&vha->loop_state, LOOP_DEAD);
  4788. /*
  4789. * Schedule an ISP abort to return any FCP2-device
  4790. * commands.
  4791. */
  4792. /* NPIV - scan physical port only */
  4793. if (!vha->vp_idx) {
  4794. spin_lock_irqsave(&ha->hardware_lock,
  4795. cpu_flags);
  4796. req = ha->req_q_map[0];
  4797. for (index = 1;
  4798. index < req->num_outstanding_cmds;
  4799. index++) {
  4800. fc_port_t *sfcp;
  4801. sp = req->outstanding_cmds[index];
  4802. if (!sp)
  4803. continue;
  4804. if (sp->type != SRB_SCSI_CMD)
  4805. continue;
  4806. sfcp = sp->fcport;
  4807. if (!(sfcp->flags & FCF_FCP2_DEVICE))
  4808. continue;
  4809. if (IS_QLA82XX(ha))
  4810. set_bit(FCOE_CTX_RESET_NEEDED,
  4811. &vha->dpc_flags);
  4812. else
  4813. set_bit(ISP_ABORT_NEEDED,
  4814. &vha->dpc_flags);
  4815. break;
  4816. }
  4817. spin_unlock_irqrestore(&ha->hardware_lock,
  4818. cpu_flags);
  4819. }
  4820. start_dpc++;
  4821. }
  4822. /* if the loop has been down for 4 minutes, reinit adapter */
  4823. if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
  4824. if (!(vha->device_flags & DFLG_NO_CABLE)) {
  4825. ql_log(ql_log_warn, vha, 0x6009,
  4826. "Loop down - aborting ISP.\n");
  4827. if (IS_QLA82XX(ha))
  4828. set_bit(FCOE_CTX_RESET_NEEDED,
  4829. &vha->dpc_flags);
  4830. else
  4831. set_bit(ISP_ABORT_NEEDED,
  4832. &vha->dpc_flags);
  4833. }
  4834. }
  4835. ql_dbg(ql_dbg_timer, vha, 0x600a,
  4836. "Loop down - seconds remaining %d.\n",
  4837. atomic_read(&vha->loop_down_timer));
  4838. }
  4839. /* Check if beacon LED needs to be blinked for physical host only */
  4840. if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
  4841. /* There is no beacon_blink function for ISP82xx */
  4842. if (!IS_P3P_TYPE(ha)) {
  4843. set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
  4844. start_dpc++;
  4845. }
  4846. }
  4847. /* Process any deferred work. */
  4848. if (!list_empty(&vha->work_list))
  4849. start_dpc++;
  4850. /* Schedule the DPC routine if needed */
  4851. if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
  4852. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
  4853. test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
  4854. start_dpc ||
  4855. test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
  4856. test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
  4857. test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
  4858. test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
  4859. test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
  4860. test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
  4861. ql_dbg(ql_dbg_timer, vha, 0x600b,
  4862. "isp_abort_needed=%d loop_resync_needed=%d "
  4863. "fcport_update_needed=%d start_dpc=%d "
  4864. "reset_marker_needed=%d",
  4865. test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
  4866. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
  4867. test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
  4868. start_dpc,
  4869. test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
  4870. ql_dbg(ql_dbg_timer, vha, 0x600c,
  4871. "beacon_blink_needed=%d isp_unrecoverable=%d "
  4872. "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
  4873. "relogin_needed=%d.\n",
  4874. test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
  4875. test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
  4876. test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
  4877. test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
  4878. test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
  4879. qla2xxx_wake_dpc(vha);
  4880. }
  4881. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  4882. }
  4883. /* Firmware interface routines. */
  4884. #define FW_BLOBS 11
  4885. #define FW_ISP21XX 0
  4886. #define FW_ISP22XX 1
  4887. #define FW_ISP2300 2
  4888. #define FW_ISP2322 3
  4889. #define FW_ISP24XX 4
  4890. #define FW_ISP25XX 5
  4891. #define FW_ISP81XX 6
  4892. #define FW_ISP82XX 7
  4893. #define FW_ISP2031 8
  4894. #define FW_ISP8031 9
  4895. #define FW_ISP27XX 10
  4896. #define FW_FILE_ISP21XX "/*(DEBLOBBED)*/"
  4897. #define FW_FILE_ISP22XX "/*(DEBLOBBED)*/"
  4898. #define FW_FILE_ISP2300 "/*(DEBLOBBED)*/"
  4899. #define FW_FILE_ISP2322 "/*(DEBLOBBED)*/"
  4900. #define FW_FILE_ISP24XX "/*(DEBLOBBED)*/"
  4901. #define FW_FILE_ISP25XX "/*(DEBLOBBED)*/"
  4902. #define FW_FILE_ISP81XX "/*(DEBLOBBED)*/"
  4903. #define FW_FILE_ISP82XX "/*(DEBLOBBED)*/"
  4904. #define FW_FILE_ISP2031 "/*(DEBLOBBED)*/"
  4905. #define FW_FILE_ISP8031 "/*(DEBLOBBED)*/"
  4906. #define FW_FILE_ISP27XX "/*(DEBLOBBED)*/"
  4907. static DEFINE_MUTEX(qla_fw_lock);
  4908. static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
  4909. { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
  4910. { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
  4911. { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
  4912. { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
  4913. { .name = FW_FILE_ISP24XX, },
  4914. { .name = FW_FILE_ISP25XX, },
  4915. { .name = FW_FILE_ISP81XX, },
  4916. { .name = FW_FILE_ISP82XX, },
  4917. { .name = FW_FILE_ISP2031, },
  4918. { .name = FW_FILE_ISP8031, },
  4919. { .name = FW_FILE_ISP27XX, },
  4920. };
  4921. struct fw_blob *
  4922. qla2x00_request_firmware(scsi_qla_host_t *vha)
  4923. {
  4924. struct qla_hw_data *ha = vha->hw;
  4925. struct fw_blob *blob;
  4926. if (IS_QLA2100(ha)) {
  4927. blob = &qla_fw_blobs[FW_ISP21XX];
  4928. } else if (IS_QLA2200(ha)) {
  4929. blob = &qla_fw_blobs[FW_ISP22XX];
  4930. } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  4931. blob = &qla_fw_blobs[FW_ISP2300];
  4932. } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  4933. blob = &qla_fw_blobs[FW_ISP2322];
  4934. } else if (IS_QLA24XX_TYPE(ha)) {
  4935. blob = &qla_fw_blobs[FW_ISP24XX];
  4936. } else if (IS_QLA25XX(ha)) {
  4937. blob = &qla_fw_blobs[FW_ISP25XX];
  4938. } else if (IS_QLA81XX(ha)) {
  4939. blob = &qla_fw_blobs[FW_ISP81XX];
  4940. } else if (IS_QLA82XX(ha)) {
  4941. blob = &qla_fw_blobs[FW_ISP82XX];
  4942. } else if (IS_QLA2031(ha)) {
  4943. blob = &qla_fw_blobs[FW_ISP2031];
  4944. } else if (IS_QLA8031(ha)) {
  4945. blob = &qla_fw_blobs[FW_ISP8031];
  4946. } else if (IS_QLA27XX(ha)) {
  4947. blob = &qla_fw_blobs[FW_ISP27XX];
  4948. } else {
  4949. return NULL;
  4950. }
  4951. mutex_lock(&qla_fw_lock);
  4952. if (blob->fw)
  4953. goto out;
  4954. if (reject_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
  4955. ql_log(ql_log_warn, vha, 0x0063,
  4956. "Failed to load firmware image (%s).\n", blob->name);
  4957. blob->fw = NULL;
  4958. blob = NULL;
  4959. goto out;
  4960. }
  4961. out:
  4962. mutex_unlock(&qla_fw_lock);
  4963. return blob;
  4964. }
  4965. static void
  4966. qla2x00_release_firmware(void)
  4967. {
  4968. int idx;
  4969. mutex_lock(&qla_fw_lock);
  4970. for (idx = 0; idx < FW_BLOBS; idx++)
  4971. release_firmware(qla_fw_blobs[idx].fw);
  4972. mutex_unlock(&qla_fw_lock);
  4973. }
  4974. static pci_ers_result_t
  4975. qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
  4976. {
  4977. scsi_qla_host_t *vha = pci_get_drvdata(pdev);
  4978. struct qla_hw_data *ha = vha->hw;
  4979. ql_dbg(ql_dbg_aer, vha, 0x9000,
  4980. "PCI error detected, state %x.\n", state);
  4981. switch (state) {
  4982. case pci_channel_io_normal:
  4983. ha->flags.eeh_busy = 0;
  4984. return PCI_ERS_RESULT_CAN_RECOVER;
  4985. case pci_channel_io_frozen:
  4986. ha->flags.eeh_busy = 1;
  4987. /* For ISP82XX complete any pending mailbox cmd */
  4988. if (IS_QLA82XX(ha)) {
  4989. ha->flags.isp82xx_fw_hung = 1;
  4990. ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
  4991. qla82xx_clear_pending_mbx(vha);
  4992. }
  4993. qla2x00_free_irqs(vha);
  4994. pci_disable_device(pdev);
  4995. /* Return back all IOs */
  4996. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  4997. return PCI_ERS_RESULT_NEED_RESET;
  4998. case pci_channel_io_perm_failure:
  4999. ha->flags.pci_channel_io_perm_failure = 1;
  5000. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  5001. return PCI_ERS_RESULT_DISCONNECT;
  5002. }
  5003. return PCI_ERS_RESULT_NEED_RESET;
  5004. }
  5005. static pci_ers_result_t
  5006. qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
  5007. {
  5008. int risc_paused = 0;
  5009. uint32_t stat;
  5010. unsigned long flags;
  5011. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  5012. struct qla_hw_data *ha = base_vha->hw;
  5013. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  5014. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  5015. if (IS_QLA82XX(ha))
  5016. return PCI_ERS_RESULT_RECOVERED;
  5017. spin_lock_irqsave(&ha->hardware_lock, flags);
  5018. if (IS_QLA2100(ha) || IS_QLA2200(ha)){
  5019. stat = RD_REG_DWORD(&reg->hccr);
  5020. if (stat & HCCR_RISC_PAUSE)
  5021. risc_paused = 1;
  5022. } else if (IS_QLA23XX(ha)) {
  5023. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  5024. if (stat & HSR_RISC_PAUSED)
  5025. risc_paused = 1;
  5026. } else if (IS_FWI2_CAPABLE(ha)) {
  5027. stat = RD_REG_DWORD(&reg24->host_status);
  5028. if (stat & HSRX_RISC_PAUSED)
  5029. risc_paused = 1;
  5030. }
  5031. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  5032. if (risc_paused) {
  5033. ql_log(ql_log_info, base_vha, 0x9003,
  5034. "RISC paused -- mmio_enabled, Dumping firmware.\n");
  5035. ha->isp_ops->fw_dump(base_vha, 0);
  5036. return PCI_ERS_RESULT_NEED_RESET;
  5037. } else
  5038. return PCI_ERS_RESULT_RECOVERED;
  5039. }
  5040. static uint32_t
  5041. qla82xx_error_recovery(scsi_qla_host_t *base_vha)
  5042. {
  5043. uint32_t rval = QLA_FUNCTION_FAILED;
  5044. uint32_t drv_active = 0;
  5045. struct qla_hw_data *ha = base_vha->hw;
  5046. int fn;
  5047. struct pci_dev *other_pdev = NULL;
  5048. ql_dbg(ql_dbg_aer, base_vha, 0x9006,
  5049. "Entered %s.\n", __func__);
  5050. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  5051. if (base_vha->flags.online) {
  5052. /* Abort all outstanding commands,
  5053. * so as to be requeued later */
  5054. qla2x00_abort_isp_cleanup(base_vha);
  5055. }
  5056. fn = PCI_FUNC(ha->pdev->devfn);
  5057. while (fn > 0) {
  5058. fn--;
  5059. ql_dbg(ql_dbg_aer, base_vha, 0x9007,
  5060. "Finding pci device at function = 0x%x.\n", fn);
  5061. other_pdev =
  5062. pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
  5063. ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
  5064. fn));
  5065. if (!other_pdev)
  5066. continue;
  5067. if (atomic_read(&other_pdev->enable_cnt)) {
  5068. ql_dbg(ql_dbg_aer, base_vha, 0x9008,
  5069. "Found PCI func available and enable at 0x%x.\n",
  5070. fn);
  5071. pci_dev_put(other_pdev);
  5072. break;
  5073. }
  5074. pci_dev_put(other_pdev);
  5075. }
  5076. if (!fn) {
  5077. /* Reset owner */
  5078. ql_dbg(ql_dbg_aer, base_vha, 0x9009,
  5079. "This devfn is reset owner = 0x%x.\n",
  5080. ha->pdev->devfn);
  5081. qla82xx_idc_lock(ha);
  5082. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  5083. QLA8XXX_DEV_INITIALIZING);
  5084. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
  5085. QLA82XX_IDC_VERSION);
  5086. drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
  5087. ql_dbg(ql_dbg_aer, base_vha, 0x900a,
  5088. "drv_active = 0x%x.\n", drv_active);
  5089. qla82xx_idc_unlock(ha);
  5090. /* Reset if device is not already reset
  5091. * drv_active would be 0 if a reset has already been done
  5092. */
  5093. if (drv_active)
  5094. rval = qla82xx_start_firmware(base_vha);
  5095. else
  5096. rval = QLA_SUCCESS;
  5097. qla82xx_idc_lock(ha);
  5098. if (rval != QLA_SUCCESS) {
  5099. ql_log(ql_log_info, base_vha, 0x900b,
  5100. "HW State: FAILED.\n");
  5101. qla82xx_clear_drv_active(ha);
  5102. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  5103. QLA8XXX_DEV_FAILED);
  5104. } else {
  5105. ql_log(ql_log_info, base_vha, 0x900c,
  5106. "HW State: READY.\n");
  5107. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  5108. QLA8XXX_DEV_READY);
  5109. qla82xx_idc_unlock(ha);
  5110. ha->flags.isp82xx_fw_hung = 0;
  5111. rval = qla82xx_restart_isp(base_vha);
  5112. qla82xx_idc_lock(ha);
  5113. /* Clear driver state register */
  5114. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
  5115. qla82xx_set_drv_active(base_vha);
  5116. }
  5117. qla82xx_idc_unlock(ha);
  5118. } else {
  5119. ql_dbg(ql_dbg_aer, base_vha, 0x900d,
  5120. "This devfn is not reset owner = 0x%x.\n",
  5121. ha->pdev->devfn);
  5122. if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
  5123. QLA8XXX_DEV_READY)) {
  5124. ha->flags.isp82xx_fw_hung = 0;
  5125. rval = qla82xx_restart_isp(base_vha);
  5126. qla82xx_idc_lock(ha);
  5127. qla82xx_set_drv_active(base_vha);
  5128. qla82xx_idc_unlock(ha);
  5129. }
  5130. }
  5131. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  5132. return rval;
  5133. }
  5134. static pci_ers_result_t
  5135. qla2xxx_pci_slot_reset(struct pci_dev *pdev)
  5136. {
  5137. pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
  5138. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  5139. struct qla_hw_data *ha = base_vha->hw;
  5140. struct rsp_que *rsp;
  5141. int rc, retries = 10;
  5142. ql_dbg(ql_dbg_aer, base_vha, 0x9004,
  5143. "Slot Reset.\n");
  5144. /* Workaround: qla2xxx driver which access hardware earlier
  5145. * needs error state to be pci_channel_io_online.
  5146. * Otherwise mailbox command timesout.
  5147. */
  5148. pdev->error_state = pci_channel_io_normal;
  5149. pci_restore_state(pdev);
  5150. /* pci_restore_state() clears the saved_state flag of the device
  5151. * save restored state which resets saved_state flag
  5152. */
  5153. pci_save_state(pdev);
  5154. if (ha->mem_only)
  5155. rc = pci_enable_device_mem(pdev);
  5156. else
  5157. rc = pci_enable_device(pdev);
  5158. if (rc) {
  5159. ql_log(ql_log_warn, base_vha, 0x9005,
  5160. "Can't re-enable PCI device after reset.\n");
  5161. goto exit_slot_reset;
  5162. }
  5163. rsp = ha->rsp_q_map[0];
  5164. if (qla2x00_request_irqs(ha, rsp))
  5165. goto exit_slot_reset;
  5166. if (ha->isp_ops->pci_config(base_vha))
  5167. goto exit_slot_reset;
  5168. if (IS_QLA82XX(ha)) {
  5169. if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
  5170. ret = PCI_ERS_RESULT_RECOVERED;
  5171. goto exit_slot_reset;
  5172. } else
  5173. goto exit_slot_reset;
  5174. }
  5175. while (ha->flags.mbox_busy && retries--)
  5176. msleep(1000);
  5177. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  5178. if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
  5179. ret = PCI_ERS_RESULT_RECOVERED;
  5180. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  5181. exit_slot_reset:
  5182. ql_dbg(ql_dbg_aer, base_vha, 0x900e,
  5183. "slot_reset return %x.\n", ret);
  5184. return ret;
  5185. }
  5186. static void
  5187. qla2xxx_pci_resume(struct pci_dev *pdev)
  5188. {
  5189. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  5190. struct qla_hw_data *ha = base_vha->hw;
  5191. int ret;
  5192. ql_dbg(ql_dbg_aer, base_vha, 0x900f,
  5193. "pci_resume.\n");
  5194. ret = qla2x00_wait_for_hba_online(base_vha);
  5195. if (ret != QLA_SUCCESS) {
  5196. ql_log(ql_log_fatal, base_vha, 0x9002,
  5197. "The device failed to resume I/O from slot/link_reset.\n");
  5198. }
  5199. pci_cleanup_aer_uncorrect_error_status(pdev);
  5200. ha->flags.eeh_busy = 0;
  5201. }
  5202. static void
  5203. qla83xx_disable_laser(scsi_qla_host_t *vha)
  5204. {
  5205. uint32_t reg, data, fn;
  5206. struct qla_hw_data *ha = vha->hw;
  5207. struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
  5208. /* pci func #/port # */
  5209. ql_dbg(ql_dbg_init, vha, 0x004b,
  5210. "Disabling Laser for hba: %p\n", vha);
  5211. fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
  5212. (BIT_15|BIT_14|BIT_13|BIT_12));
  5213. fn = (fn >> 12);
  5214. if (fn & 1)
  5215. reg = PORT_1_2031;
  5216. else
  5217. reg = PORT_0_2031;
  5218. data = LASER_OFF_2031;
  5219. qla83xx_wr_reg(vha, reg, data);
  5220. }
  5221. static const struct pci_error_handlers qla2xxx_err_handler = {
  5222. .error_detected = qla2xxx_pci_error_detected,
  5223. .mmio_enabled = qla2xxx_pci_mmio_enabled,
  5224. .slot_reset = qla2xxx_pci_slot_reset,
  5225. .resume = qla2xxx_pci_resume,
  5226. };
  5227. static struct pci_device_id qla2xxx_pci_tbl[] = {
  5228. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
  5229. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
  5230. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
  5231. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
  5232. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
  5233. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
  5234. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
  5235. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
  5236. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
  5237. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
  5238. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
  5239. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
  5240. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
  5241. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
  5242. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
  5243. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
  5244. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
  5245. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
  5246. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
  5247. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
  5248. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
  5249. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
  5250. { 0 },
  5251. };
  5252. MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
  5253. static struct pci_driver qla2xxx_pci_driver = {
  5254. .name = QLA2XXX_DRIVER_NAME,
  5255. .driver = {
  5256. .owner = THIS_MODULE,
  5257. },
  5258. .id_table = qla2xxx_pci_tbl,
  5259. .probe = qla2x00_probe_one,
  5260. .remove = qla2x00_remove_one,
  5261. .shutdown = qla2x00_shutdown,
  5262. .err_handler = &qla2xxx_err_handler,
  5263. };
  5264. static const struct file_operations apidev_fops = {
  5265. .owner = THIS_MODULE,
  5266. .llseek = noop_llseek,
  5267. };
  5268. /**
  5269. * qla2x00_module_init - Module initialization.
  5270. **/
  5271. static int __init
  5272. qla2x00_module_init(void)
  5273. {
  5274. int ret = 0;
  5275. /* Allocate cache for SRBs. */
  5276. srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
  5277. SLAB_HWCACHE_ALIGN, NULL);
  5278. if (srb_cachep == NULL) {
  5279. ql_log(ql_log_fatal, NULL, 0x0001,
  5280. "Unable to allocate SRB cache...Failing load!.\n");
  5281. return -ENOMEM;
  5282. }
  5283. /* Initialize target kmem_cache and mem_pools */
  5284. ret = qlt_init();
  5285. if (ret < 0) {
  5286. kmem_cache_destroy(srb_cachep);
  5287. return ret;
  5288. } else if (ret > 0) {
  5289. /*
  5290. * If initiator mode is explictly disabled by qlt_init(),
  5291. * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
  5292. * performing scsi_scan_target() during LOOP UP event.
  5293. */
  5294. qla2xxx_transport_functions.disable_target_scan = 1;
  5295. qla2xxx_transport_vport_functions.disable_target_scan = 1;
  5296. }
  5297. /* Derive version string. */
  5298. strcpy(qla2x00_version_str, QLA2XXX_VERSION);
  5299. if (ql2xextended_error_logging)
  5300. strcat(qla2x00_version_str, "-debug");
  5301. qla2xxx_transport_template =
  5302. fc_attach_transport(&qla2xxx_transport_functions);
  5303. if (!qla2xxx_transport_template) {
  5304. kmem_cache_destroy(srb_cachep);
  5305. ql_log(ql_log_fatal, NULL, 0x0002,
  5306. "fc_attach_transport failed...Failing load!.\n");
  5307. qlt_exit();
  5308. return -ENODEV;
  5309. }
  5310. apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
  5311. if (apidev_major < 0) {
  5312. ql_log(ql_log_fatal, NULL, 0x0003,
  5313. "Unable to register char device %s.\n", QLA2XXX_APIDEV);
  5314. }
  5315. qla2xxx_transport_vport_template =
  5316. fc_attach_transport(&qla2xxx_transport_vport_functions);
  5317. if (!qla2xxx_transport_vport_template) {
  5318. kmem_cache_destroy(srb_cachep);
  5319. qlt_exit();
  5320. fc_release_transport(qla2xxx_transport_template);
  5321. ql_log(ql_log_fatal, NULL, 0x0004,
  5322. "fc_attach_transport vport failed...Failing load!.\n");
  5323. return -ENODEV;
  5324. }
  5325. ql_log(ql_log_info, NULL, 0x0005,
  5326. "QLogic Fibre Channel HBA Driver: %s.\n",
  5327. qla2x00_version_str);
  5328. ret = pci_register_driver(&qla2xxx_pci_driver);
  5329. if (ret) {
  5330. kmem_cache_destroy(srb_cachep);
  5331. qlt_exit();
  5332. fc_release_transport(qla2xxx_transport_template);
  5333. fc_release_transport(qla2xxx_transport_vport_template);
  5334. ql_log(ql_log_fatal, NULL, 0x0006,
  5335. "pci_register_driver failed...ret=%d Failing load!.\n",
  5336. ret);
  5337. }
  5338. return ret;
  5339. }
  5340. /**
  5341. * qla2x00_module_exit - Module cleanup.
  5342. **/
  5343. static void __exit
  5344. qla2x00_module_exit(void)
  5345. {
  5346. unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
  5347. pci_unregister_driver(&qla2xxx_pci_driver);
  5348. qla2x00_release_firmware();
  5349. kmem_cache_destroy(srb_cachep);
  5350. qlt_exit();
  5351. if (ctx_cachep)
  5352. kmem_cache_destroy(ctx_cachep);
  5353. fc_release_transport(qla2xxx_transport_template);
  5354. fc_release_transport(qla2xxx_transport_vport_template);
  5355. }
  5356. module_init(qla2x00_module_init);
  5357. module_exit(qla2x00_module_exit);
  5358. MODULE_AUTHOR("QLogic Corporation");
  5359. MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
  5360. MODULE_LICENSE("GPL");
  5361. MODULE_VERSION(QLA2XXX_VERSION);
  5362. /*(DEBLOBBED)*/