qla_mr.c 90 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2014 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/delay.h>
  9. #include <linux/ktime.h>
  10. #include <linux/pci.h>
  11. #include <linux/ratelimit.h>
  12. #include <linux/vmalloc.h>
  13. #include <scsi/scsi_tcq.h>
  14. #include <linux/utsname.h>
  15. /* QLAFX00 specific Mailbox implementation functions */
  16. /*
  17. * qlafx00_mailbox_command
  18. * Issue mailbox command and waits for completion.
  19. *
  20. * Input:
  21. * ha = adapter block pointer.
  22. * mcp = driver internal mbx struct pointer.
  23. *
  24. * Output:
  25. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  26. *
  27. * Returns:
  28. * 0 : QLA_SUCCESS = cmd performed success
  29. * 1 : QLA_FUNCTION_FAILED (error encountered)
  30. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  31. *
  32. * Context:
  33. * Kernel context.
  34. */
  35. static int
  36. qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
  37. {
  38. int rval;
  39. unsigned long flags = 0;
  40. device_reg_t *reg;
  41. uint8_t abort_active;
  42. uint8_t io_lock_on;
  43. uint16_t command = 0;
  44. uint32_t *iptr;
  45. uint32_t __iomem *optr;
  46. uint32_t cnt;
  47. uint32_t mboxes;
  48. unsigned long wait_time;
  49. struct qla_hw_data *ha = vha->hw;
  50. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  51. if (ha->pdev->error_state > pci_channel_io_frozen) {
  52. ql_log(ql_log_warn, vha, 0x115c,
  53. "error_state is greater than pci_channel_io_frozen, "
  54. "exiting.\n");
  55. return QLA_FUNCTION_TIMEOUT;
  56. }
  57. if (vha->device_flags & DFLG_DEV_FAILED) {
  58. ql_log(ql_log_warn, vha, 0x115f,
  59. "Device in failed state, exiting.\n");
  60. return QLA_FUNCTION_TIMEOUT;
  61. }
  62. reg = ha->iobase;
  63. io_lock_on = base_vha->flags.init_done;
  64. rval = QLA_SUCCESS;
  65. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  66. if (ha->flags.pci_channel_io_perm_failure) {
  67. ql_log(ql_log_warn, vha, 0x1175,
  68. "Perm failure on EEH timeout MBX, exiting.\n");
  69. return QLA_FUNCTION_TIMEOUT;
  70. }
  71. if (ha->flags.isp82xx_fw_hung) {
  72. /* Setting Link-Down error */
  73. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  74. ql_log(ql_log_warn, vha, 0x1176,
  75. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  76. rval = QLA_FUNCTION_FAILED;
  77. goto premature_exit;
  78. }
  79. /*
  80. * Wait for active mailbox commands to finish by waiting at most tov
  81. * seconds. This is to serialize actual issuing of mailbox cmds during
  82. * non ISP abort time.
  83. */
  84. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  85. /* Timeout occurred. Return error. */
  86. ql_log(ql_log_warn, vha, 0x1177,
  87. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  88. mcp->mb[0]);
  89. return QLA_FUNCTION_TIMEOUT;
  90. }
  91. ha->flags.mbox_busy = 1;
  92. /* Save mailbox command for debug */
  93. ha->mcp32 = mcp;
  94. ql_dbg(ql_dbg_mbx, vha, 0x1178,
  95. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  96. spin_lock_irqsave(&ha->hardware_lock, flags);
  97. /* Load mailbox registers. */
  98. optr = (uint32_t __iomem *)&reg->ispfx00.mailbox0;
  99. iptr = mcp->mb;
  100. command = mcp->mb[0];
  101. mboxes = mcp->out_mb;
  102. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  103. if (mboxes & BIT_0)
  104. WRT_REG_DWORD(optr, *iptr);
  105. mboxes >>= 1;
  106. optr++;
  107. iptr++;
  108. }
  109. /* Issue set host interrupt command to send cmd out. */
  110. ha->flags.mbox_int = 0;
  111. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  112. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
  113. (uint8_t *)mcp->mb, 16);
  114. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
  115. ((uint8_t *)mcp->mb + 0x10), 16);
  116. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
  117. ((uint8_t *)mcp->mb + 0x20), 8);
  118. /* Unlock mbx registers and wait for interrupt */
  119. ql_dbg(ql_dbg_mbx, vha, 0x1179,
  120. "Going to unlock irq & waiting for interrupts. "
  121. "jiffies=%lx.\n", jiffies);
  122. /* Wait for mbx cmd completion until timeout */
  123. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  124. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  125. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  126. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  127. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  128. } else {
  129. ql_dbg(ql_dbg_mbx, vha, 0x112c,
  130. "Cmd=%x Polling Mode.\n", command);
  131. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  132. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  133. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  134. while (!ha->flags.mbox_int) {
  135. if (time_after(jiffies, wait_time))
  136. break;
  137. /* Check for pending interrupts. */
  138. qla2x00_poll(ha->rsp_q_map[0]);
  139. if (!ha->flags.mbox_int &&
  140. !(IS_QLA2200(ha) &&
  141. command == MBC_LOAD_RISC_RAM_EXTENDED))
  142. usleep_range(10000, 11000);
  143. } /* while */
  144. ql_dbg(ql_dbg_mbx, vha, 0x112d,
  145. "Waited %d sec.\n",
  146. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  147. }
  148. /* Check whether we timed out */
  149. if (ha->flags.mbox_int) {
  150. uint32_t *iptr2;
  151. ql_dbg(ql_dbg_mbx, vha, 0x112e,
  152. "Cmd=%x completed.\n", command);
  153. /* Got interrupt. Clear the flag. */
  154. ha->flags.mbox_int = 0;
  155. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  156. if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
  157. rval = QLA_FUNCTION_FAILED;
  158. /* Load return mailbox registers. */
  159. iptr2 = mcp->mb;
  160. iptr = (uint32_t *)&ha->mailbox_out32[0];
  161. mboxes = mcp->in_mb;
  162. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  163. if (mboxes & BIT_0)
  164. *iptr2 = *iptr;
  165. mboxes >>= 1;
  166. iptr2++;
  167. iptr++;
  168. }
  169. } else {
  170. rval = QLA_FUNCTION_TIMEOUT;
  171. }
  172. ha->flags.mbox_busy = 0;
  173. /* Clean up */
  174. ha->mcp32 = NULL;
  175. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  176. ql_dbg(ql_dbg_mbx, vha, 0x113a,
  177. "checking for additional resp interrupt.\n");
  178. /* polling mode for non isp_abort commands. */
  179. qla2x00_poll(ha->rsp_q_map[0]);
  180. }
  181. if (rval == QLA_FUNCTION_TIMEOUT &&
  182. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  183. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  184. ha->flags.eeh_busy) {
  185. /* not in dpc. schedule it for dpc to take over. */
  186. ql_dbg(ql_dbg_mbx, vha, 0x115d,
  187. "Timeout, schedule isp_abort_needed.\n");
  188. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  189. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  190. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  191. ql_log(ql_log_info, base_vha, 0x115e,
  192. "Mailbox cmd timeout occurred, cmd=0x%x, "
  193. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  194. "abort.\n", command, mcp->mb[0],
  195. ha->flags.eeh_busy);
  196. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  197. qla2xxx_wake_dpc(vha);
  198. }
  199. } else if (!abort_active) {
  200. /* call abort directly since we are in the DPC thread */
  201. ql_dbg(ql_dbg_mbx, vha, 0x1160,
  202. "Timeout, calling abort_isp.\n");
  203. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  204. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  205. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  206. ql_log(ql_log_info, base_vha, 0x1161,
  207. "Mailbox cmd timeout occurred, cmd=0x%x, "
  208. "mb[0]=0x%x. Scheduling ISP abort ",
  209. command, mcp->mb[0]);
  210. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  211. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  212. if (ha->isp_ops->abort_isp(vha)) {
  213. /* Failed. retry later. */
  214. set_bit(ISP_ABORT_NEEDED,
  215. &vha->dpc_flags);
  216. }
  217. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  218. ql_dbg(ql_dbg_mbx, vha, 0x1162,
  219. "Finished abort_isp.\n");
  220. }
  221. }
  222. }
  223. premature_exit:
  224. /* Allow next mbx cmd to come in. */
  225. complete(&ha->mbx_cmd_comp);
  226. if (rval) {
  227. ql_log(ql_log_warn, base_vha, 0x1163,
  228. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, "
  229. "mb[3]=%x, cmd=%x ****.\n",
  230. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  231. } else {
  232. ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
  233. }
  234. return rval;
  235. }
  236. /*
  237. * qlafx00_driver_shutdown
  238. * Indicate a driver shutdown to firmware.
  239. *
  240. * Input:
  241. * ha = adapter block pointer.
  242. *
  243. * Returns:
  244. * local function return status code.
  245. *
  246. * Context:
  247. * Kernel context.
  248. */
  249. int
  250. qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
  251. {
  252. int rval;
  253. struct mbx_cmd_32 mc;
  254. struct mbx_cmd_32 *mcp = &mc;
  255. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
  256. "Entered %s.\n", __func__);
  257. mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
  258. mcp->out_mb = MBX_0;
  259. mcp->in_mb = MBX_0;
  260. if (tmo)
  261. mcp->tov = tmo;
  262. else
  263. mcp->tov = MBX_TOV_SECONDS;
  264. mcp->flags = 0;
  265. rval = qlafx00_mailbox_command(vha, mcp);
  266. if (rval != QLA_SUCCESS) {
  267. ql_dbg(ql_dbg_mbx, vha, 0x1167,
  268. "Failed=%x.\n", rval);
  269. } else {
  270. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
  271. "Done %s.\n", __func__);
  272. }
  273. return rval;
  274. }
  275. /*
  276. * qlafx00_get_firmware_state
  277. * Get adapter firmware state.
  278. *
  279. * Input:
  280. * ha = adapter block pointer.
  281. * TARGET_QUEUE_LOCK must be released.
  282. * ADAPTER_STATE_LOCK must be released.
  283. *
  284. * Returns:
  285. * qla7xxx local function return status code.
  286. *
  287. * Context:
  288. * Kernel context.
  289. */
  290. static int
  291. qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
  292. {
  293. int rval;
  294. struct mbx_cmd_32 mc;
  295. struct mbx_cmd_32 *mcp = &mc;
  296. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
  297. "Entered %s.\n", __func__);
  298. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  299. mcp->out_mb = MBX_0;
  300. mcp->in_mb = MBX_1|MBX_0;
  301. mcp->tov = MBX_TOV_SECONDS;
  302. mcp->flags = 0;
  303. rval = qlafx00_mailbox_command(vha, mcp);
  304. /* Return firmware states. */
  305. states[0] = mcp->mb[1];
  306. if (rval != QLA_SUCCESS) {
  307. ql_dbg(ql_dbg_mbx, vha, 0x116a,
  308. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  309. } else {
  310. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
  311. "Done %s.\n", __func__);
  312. }
  313. return rval;
  314. }
  315. /*
  316. * qlafx00_init_firmware
  317. * Initialize adapter firmware.
  318. *
  319. * Input:
  320. * ha = adapter block pointer.
  321. * dptr = Initialization control block pointer.
  322. * size = size of initialization control block.
  323. * TARGET_QUEUE_LOCK must be released.
  324. * ADAPTER_STATE_LOCK must be released.
  325. *
  326. * Returns:
  327. * qlafx00 local function return status code.
  328. *
  329. * Context:
  330. * Kernel context.
  331. */
  332. int
  333. qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  334. {
  335. int rval;
  336. struct mbx_cmd_32 mc;
  337. struct mbx_cmd_32 *mcp = &mc;
  338. struct qla_hw_data *ha = vha->hw;
  339. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
  340. "Entered %s.\n", __func__);
  341. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  342. mcp->mb[1] = 0;
  343. mcp->mb[2] = MSD(ha->init_cb_dma);
  344. mcp->mb[3] = LSD(ha->init_cb_dma);
  345. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  346. mcp->in_mb = MBX_0;
  347. mcp->buf_size = size;
  348. mcp->flags = MBX_DMA_OUT;
  349. mcp->tov = MBX_TOV_SECONDS;
  350. rval = qlafx00_mailbox_command(vha, mcp);
  351. if (rval != QLA_SUCCESS) {
  352. ql_dbg(ql_dbg_mbx, vha, 0x116d,
  353. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  354. } else {
  355. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
  356. "Done %s.\n", __func__);
  357. }
  358. return rval;
  359. }
  360. /*
  361. * qlafx00_mbx_reg_test
  362. */
  363. static int
  364. qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
  365. {
  366. int rval;
  367. struct mbx_cmd_32 mc;
  368. struct mbx_cmd_32 *mcp = &mc;
  369. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
  370. "Entered %s.\n", __func__);
  371. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  372. mcp->mb[1] = 0xAAAA;
  373. mcp->mb[2] = 0x5555;
  374. mcp->mb[3] = 0xAA55;
  375. mcp->mb[4] = 0x55AA;
  376. mcp->mb[5] = 0xA5A5;
  377. mcp->mb[6] = 0x5A5A;
  378. mcp->mb[7] = 0x2525;
  379. mcp->mb[8] = 0xBBBB;
  380. mcp->mb[9] = 0x6666;
  381. mcp->mb[10] = 0xBB66;
  382. mcp->mb[11] = 0x66BB;
  383. mcp->mb[12] = 0xB6B6;
  384. mcp->mb[13] = 0x6B6B;
  385. mcp->mb[14] = 0x3636;
  386. mcp->mb[15] = 0xCCCC;
  387. mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  388. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  389. mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  390. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  391. mcp->buf_size = 0;
  392. mcp->flags = MBX_DMA_OUT;
  393. mcp->tov = MBX_TOV_SECONDS;
  394. rval = qlafx00_mailbox_command(vha, mcp);
  395. if (rval == QLA_SUCCESS) {
  396. if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
  397. mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
  398. rval = QLA_FUNCTION_FAILED;
  399. if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
  400. mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
  401. rval = QLA_FUNCTION_FAILED;
  402. if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
  403. mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
  404. rval = QLA_FUNCTION_FAILED;
  405. if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
  406. mcp->mb[31] != 0xCCCC)
  407. rval = QLA_FUNCTION_FAILED;
  408. }
  409. if (rval != QLA_SUCCESS) {
  410. ql_dbg(ql_dbg_mbx, vha, 0x1170,
  411. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  412. } else {
  413. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
  414. "Done %s.\n", __func__);
  415. }
  416. return rval;
  417. }
  418. /**
  419. * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers.
  420. * @ha: HA context
  421. *
  422. * Returns 0 on success.
  423. */
  424. int
  425. qlafx00_pci_config(scsi_qla_host_t *vha)
  426. {
  427. uint16_t w;
  428. struct qla_hw_data *ha = vha->hw;
  429. pci_set_master(ha->pdev);
  430. pci_try_set_mwi(ha->pdev);
  431. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  432. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  433. w &= ~PCI_COMMAND_INTX_DISABLE;
  434. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  435. /* PCIe -- adjust Maximum Read Request Size (2048). */
  436. if (pci_is_pcie(ha->pdev))
  437. pcie_set_readrq(ha->pdev, 2048);
  438. ha->chip_revision = ha->pdev->revision;
  439. return QLA_SUCCESS;
  440. }
  441. /**
  442. * qlafx00_warm_reset() - Perform warm reset of iSA(CPUs being reset on SOC).
  443. * @ha: HA context
  444. *
  445. */
  446. static inline void
  447. qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
  448. {
  449. unsigned long flags = 0;
  450. struct qla_hw_data *ha = vha->hw;
  451. int i, core;
  452. uint32_t cnt;
  453. uint32_t reg_val;
  454. spin_lock_irqsave(&ha->hardware_lock, flags);
  455. QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0);
  456. QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0);
  457. /* stop the XOR DMA engines */
  458. QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02);
  459. QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02);
  460. QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02);
  461. QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02);
  462. /* stop the IDMA engines */
  463. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840);
  464. reg_val &= ~(1<<12);
  465. QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val);
  466. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844);
  467. reg_val &= ~(1<<12);
  468. QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val);
  469. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848);
  470. reg_val &= ~(1<<12);
  471. QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val);
  472. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C);
  473. reg_val &= ~(1<<12);
  474. QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val);
  475. for (i = 0; i < 100000; i++) {
  476. if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 &&
  477. (QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0)
  478. break;
  479. udelay(100);
  480. }
  481. /* Set all 4 cores in reset */
  482. for (i = 0; i < 4; i++) {
  483. QLAFX00_SET_HBA_SOC_REG(ha,
  484. (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
  485. QLAFX00_SET_HBA_SOC_REG(ha,
  486. (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
  487. }
  488. /* Reset all units in Fabric */
  489. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101));
  490. /* */
  491. QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1);
  492. QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0);
  493. /* Set all 4 core Memory Power Down Registers */
  494. for (i = 0; i < 5; i++) {
  495. QLAFX00_SET_HBA_SOC_REG(ha,
  496. (SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0));
  497. }
  498. /* Reset all interrupt control registers */
  499. for (i = 0; i < 115; i++) {
  500. QLAFX00_SET_HBA_SOC_REG(ha,
  501. (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
  502. }
  503. /* Reset Timers control registers. per core */
  504. for (core = 0; core < 4; core++)
  505. for (i = 0; i < 8; i++)
  506. QLAFX00_SET_HBA_SOC_REG(ha,
  507. (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
  508. /* Reset per core IRQ ack register */
  509. for (core = 0; core < 4; core++)
  510. QLAFX00_SET_HBA_SOC_REG(ha,
  511. (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
  512. /* Set Fabric control and config to defaults */
  513. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
  514. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
  515. /* Kick in Fabric units */
  516. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
  517. /* Kick in Core0 to start boot process */
  518. QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
  519. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  520. /* Wait 10secs for soft-reset to complete. */
  521. for (cnt = 10; cnt; cnt--) {
  522. msleep(1000);
  523. barrier();
  524. }
  525. }
  526. /**
  527. * qlafx00_soft_reset() - Soft Reset ISPFx00.
  528. * @ha: HA context
  529. *
  530. * Returns 0 on success.
  531. */
  532. void
  533. qlafx00_soft_reset(scsi_qla_host_t *vha)
  534. {
  535. struct qla_hw_data *ha = vha->hw;
  536. if (unlikely(pci_channel_offline(ha->pdev) &&
  537. ha->flags.pci_channel_io_perm_failure))
  538. return;
  539. ha->isp_ops->disable_intrs(ha);
  540. qlafx00_soc_cpu_reset(vha);
  541. }
  542. /**
  543. * qlafx00_chip_diag() - Test ISPFx00 for proper operation.
  544. * @ha: HA context
  545. *
  546. * Returns 0 on success.
  547. */
  548. int
  549. qlafx00_chip_diag(scsi_qla_host_t *vha)
  550. {
  551. int rval = 0;
  552. struct qla_hw_data *ha = vha->hw;
  553. struct req_que *req = ha->req_q_map[0];
  554. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  555. rval = qlafx00_mbx_reg_test(vha);
  556. if (rval) {
  557. ql_log(ql_log_warn, vha, 0x1165,
  558. "Failed mailbox send register test\n");
  559. } else {
  560. /* Flag a successful rval */
  561. rval = QLA_SUCCESS;
  562. }
  563. return rval;
  564. }
  565. void
  566. qlafx00_config_rings(struct scsi_qla_host *vha)
  567. {
  568. struct qla_hw_data *ha = vha->hw;
  569. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  570. WRT_REG_DWORD(&reg->req_q_in, 0);
  571. WRT_REG_DWORD(&reg->req_q_out, 0);
  572. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  573. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  574. /* PCI posting */
  575. RD_REG_DWORD(&reg->rsp_q_out);
  576. }
  577. char *
  578. qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str)
  579. {
  580. struct qla_hw_data *ha = vha->hw;
  581. if (pci_is_pcie(ha->pdev)) {
  582. strcpy(str, "PCIe iSA");
  583. return str;
  584. }
  585. return str;
  586. }
  587. char *
  588. qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
  589. {
  590. struct qla_hw_data *ha = vha->hw;
  591. snprintf(str, size, "%s", ha->mr.fw_version);
  592. return str;
  593. }
  594. void
  595. qlafx00_enable_intrs(struct qla_hw_data *ha)
  596. {
  597. unsigned long flags = 0;
  598. spin_lock_irqsave(&ha->hardware_lock, flags);
  599. ha->interrupts_on = 1;
  600. QLAFX00_ENABLE_ICNTRL_REG(ha);
  601. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  602. }
  603. void
  604. qlafx00_disable_intrs(struct qla_hw_data *ha)
  605. {
  606. unsigned long flags = 0;
  607. spin_lock_irqsave(&ha->hardware_lock, flags);
  608. ha->interrupts_on = 0;
  609. QLAFX00_DISABLE_ICNTRL_REG(ha);
  610. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  611. }
  612. int
  613. qlafx00_abort_target(fc_port_t *fcport, uint64_t l, int tag)
  614. {
  615. return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  616. }
  617. int
  618. qlafx00_lun_reset(fc_port_t *fcport, uint64_t l, int tag)
  619. {
  620. return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  621. }
  622. int
  623. qlafx00_loop_reset(scsi_qla_host_t *vha)
  624. {
  625. int ret;
  626. struct fc_port *fcport;
  627. struct qla_hw_data *ha = vha->hw;
  628. if (ql2xtargetreset) {
  629. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  630. if (fcport->port_type != FCT_TARGET)
  631. continue;
  632. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  633. if (ret != QLA_SUCCESS) {
  634. ql_dbg(ql_dbg_taskm, vha, 0x803d,
  635. "Bus Reset failed: Reset=%d "
  636. "d_id=%x.\n", ret, fcport->d_id.b24);
  637. }
  638. }
  639. }
  640. return QLA_SUCCESS;
  641. }
  642. int
  643. qlafx00_iospace_config(struct qla_hw_data *ha)
  644. {
  645. if (pci_request_selected_regions(ha->pdev, ha->bars,
  646. QLA2XXX_DRIVER_NAME)) {
  647. ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
  648. "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
  649. pci_name(ha->pdev));
  650. goto iospace_error_exit;
  651. }
  652. /* Use MMIO operations for all accesses. */
  653. if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
  654. ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
  655. "Invalid pci I/O region size (%s).\n",
  656. pci_name(ha->pdev));
  657. goto iospace_error_exit;
  658. }
  659. if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
  660. ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
  661. "Invalid PCI mem BAR0 region size (%s), aborting\n",
  662. pci_name(ha->pdev));
  663. goto iospace_error_exit;
  664. }
  665. ha->cregbase =
  666. ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
  667. if (!ha->cregbase) {
  668. ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
  669. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  670. goto iospace_error_exit;
  671. }
  672. if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
  673. ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
  674. "region #2 not an MMIO resource (%s), aborting\n",
  675. pci_name(ha->pdev));
  676. goto iospace_error_exit;
  677. }
  678. if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
  679. ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
  680. "Invalid PCI mem BAR2 region size (%s), aborting\n",
  681. pci_name(ha->pdev));
  682. goto iospace_error_exit;
  683. }
  684. ha->iobase =
  685. ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
  686. if (!ha->iobase) {
  687. ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
  688. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  689. goto iospace_error_exit;
  690. }
  691. /* Determine queue resources */
  692. ha->max_req_queues = ha->max_rsp_queues = 1;
  693. ql_log_pci(ql_log_info, ha->pdev, 0x012c,
  694. "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
  695. ha->bars, ha->cregbase, ha->iobase);
  696. return 0;
  697. iospace_error_exit:
  698. return -ENOMEM;
  699. }
  700. static void
  701. qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
  702. {
  703. struct qla_hw_data *ha = vha->hw;
  704. struct req_que *req = ha->req_q_map[0];
  705. struct rsp_que *rsp = ha->rsp_q_map[0];
  706. req->length_fx00 = req->length;
  707. req->ring_fx00 = req->ring;
  708. req->dma_fx00 = req->dma;
  709. rsp->length_fx00 = rsp->length;
  710. rsp->ring_fx00 = rsp->ring;
  711. rsp->dma_fx00 = rsp->dma;
  712. ql_dbg(ql_dbg_init, vha, 0x012d,
  713. "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
  714. "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
  715. req->length_fx00, (u64)req->dma_fx00);
  716. ql_dbg(ql_dbg_init, vha, 0x012e,
  717. "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
  718. "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
  719. rsp->length_fx00, (u64)rsp->dma_fx00);
  720. }
  721. static int
  722. qlafx00_config_queues(struct scsi_qla_host *vha)
  723. {
  724. struct qla_hw_data *ha = vha->hw;
  725. struct req_que *req = ha->req_q_map[0];
  726. struct rsp_que *rsp = ha->rsp_q_map[0];
  727. dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
  728. req->length = ha->req_que_len;
  729. req->ring = (void __force *)ha->iobase + ha->req_que_off;
  730. req->dma = bar2_hdl + ha->req_que_off;
  731. if ((!req->ring) || (req->length == 0)) {
  732. ql_log_pci(ql_log_info, ha->pdev, 0x012f,
  733. "Unable to allocate memory for req_ring\n");
  734. return QLA_FUNCTION_FAILED;
  735. }
  736. ql_dbg(ql_dbg_init, vha, 0x0130,
  737. "req: %p req_ring pointer %p req len 0x%x "
  738. "req off 0x%x\n, req->dma: 0x%llx",
  739. req, req->ring, req->length,
  740. ha->req_que_off, (u64)req->dma);
  741. rsp->length = ha->rsp_que_len;
  742. rsp->ring = (void __force *)ha->iobase + ha->rsp_que_off;
  743. rsp->dma = bar2_hdl + ha->rsp_que_off;
  744. if ((!rsp->ring) || (rsp->length == 0)) {
  745. ql_log_pci(ql_log_info, ha->pdev, 0x0131,
  746. "Unable to allocate memory for rsp_ring\n");
  747. return QLA_FUNCTION_FAILED;
  748. }
  749. ql_dbg(ql_dbg_init, vha, 0x0132,
  750. "rsp: %p rsp_ring pointer %p rsp len 0x%x "
  751. "rsp off 0x%x, rsp->dma: 0x%llx\n",
  752. rsp, rsp->ring, rsp->length,
  753. ha->rsp_que_off, (u64)rsp->dma);
  754. return QLA_SUCCESS;
  755. }
  756. static int
  757. qlafx00_init_fw_ready(scsi_qla_host_t *vha)
  758. {
  759. int rval = 0;
  760. unsigned long wtime;
  761. uint16_t wait_time; /* Wait time */
  762. struct qla_hw_data *ha = vha->hw;
  763. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  764. uint32_t aenmbx, aenmbx7 = 0;
  765. uint32_t pseudo_aen;
  766. uint32_t state[5];
  767. bool done = false;
  768. /* 30 seconds wait - Adjust if required */
  769. wait_time = 30;
  770. pseudo_aen = RD_REG_DWORD(&reg->pseudoaen);
  771. if (pseudo_aen == 1) {
  772. aenmbx7 = RD_REG_DWORD(&reg->initval7);
  773. ha->mbx_intr_code = MSW(aenmbx7);
  774. ha->rqstq_intr_code = LSW(aenmbx7);
  775. rval = qlafx00_driver_shutdown(vha, 10);
  776. if (rval != QLA_SUCCESS)
  777. qlafx00_soft_reset(vha);
  778. }
  779. /* wait time before firmware ready */
  780. wtime = jiffies + (wait_time * HZ);
  781. do {
  782. aenmbx = RD_REG_DWORD(&reg->aenmailbox0);
  783. barrier();
  784. ql_dbg(ql_dbg_mbx, vha, 0x0133,
  785. "aenmbx: 0x%x\n", aenmbx);
  786. switch (aenmbx) {
  787. case MBA_FW_NOT_STARTED:
  788. case MBA_FW_STARTING:
  789. break;
  790. case MBA_SYSTEM_ERR:
  791. case MBA_REQ_TRANSFER_ERR:
  792. case MBA_RSP_TRANSFER_ERR:
  793. case MBA_FW_INIT_FAILURE:
  794. qlafx00_soft_reset(vha);
  795. break;
  796. case MBA_FW_RESTART_CMPLT:
  797. /* Set the mbx and rqstq intr code */
  798. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  799. ha->mbx_intr_code = MSW(aenmbx7);
  800. ha->rqstq_intr_code = LSW(aenmbx7);
  801. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  802. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  803. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  804. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  805. WRT_REG_DWORD(&reg->aenmailbox0, 0);
  806. RD_REG_DWORD_RELAXED(&reg->aenmailbox0);
  807. ql_dbg(ql_dbg_init, vha, 0x0134,
  808. "f/w returned mbx_intr_code: 0x%x, "
  809. "rqstq_intr_code: 0x%x\n",
  810. ha->mbx_intr_code, ha->rqstq_intr_code);
  811. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  812. rval = QLA_SUCCESS;
  813. done = true;
  814. break;
  815. default:
  816. if ((aenmbx & 0xFF00) == MBA_FW_INIT_INPROGRESS)
  817. break;
  818. /* If fw is apparently not ready. In order to continue,
  819. * we might need to issue Mbox cmd, but the problem is
  820. * that the DoorBell vector values that come with the
  821. * 8060 AEN are most likely gone by now (and thus no
  822. * bell would be rung on the fw side when mbox cmd is
  823. * issued). We have to therefore grab the 8060 AEN
  824. * shadow regs (filled in by FW when the last 8060
  825. * AEN was being posted).
  826. * Do the following to determine what is needed in
  827. * order to get the FW ready:
  828. * 1. reload the 8060 AEN values from the shadow regs
  829. * 2. clear int status to get rid of possible pending
  830. * interrupts
  831. * 3. issue Get FW State Mbox cmd to determine fw state
  832. * Set the mbx and rqstq intr code from Shadow Regs
  833. */
  834. aenmbx7 = RD_REG_DWORD(&reg->initval7);
  835. ha->mbx_intr_code = MSW(aenmbx7);
  836. ha->rqstq_intr_code = LSW(aenmbx7);
  837. ha->req_que_off = RD_REG_DWORD(&reg->initval1);
  838. ha->rsp_que_off = RD_REG_DWORD(&reg->initval3);
  839. ha->req_que_len = RD_REG_DWORD(&reg->initval5);
  840. ha->rsp_que_len = RD_REG_DWORD(&reg->initval6);
  841. ql_dbg(ql_dbg_init, vha, 0x0135,
  842. "f/w returned mbx_intr_code: 0x%x, "
  843. "rqstq_intr_code: 0x%x\n",
  844. ha->mbx_intr_code, ha->rqstq_intr_code);
  845. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  846. /* Get the FW state */
  847. rval = qlafx00_get_firmware_state(vha, state);
  848. if (rval != QLA_SUCCESS) {
  849. /* Retry if timer has not expired */
  850. break;
  851. }
  852. if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
  853. /* Firmware is waiting to be
  854. * initialized by driver
  855. */
  856. rval = QLA_SUCCESS;
  857. done = true;
  858. break;
  859. }
  860. /* Issue driver shutdown and wait until f/w recovers.
  861. * Driver should continue to poll until 8060 AEN is
  862. * received indicating firmware recovery.
  863. */
  864. ql_dbg(ql_dbg_init, vha, 0x0136,
  865. "Sending Driver shutdown fw_state 0x%x\n",
  866. state[0]);
  867. rval = qlafx00_driver_shutdown(vha, 10);
  868. if (rval != QLA_SUCCESS) {
  869. rval = QLA_FUNCTION_FAILED;
  870. break;
  871. }
  872. msleep(500);
  873. wtime = jiffies + (wait_time * HZ);
  874. break;
  875. }
  876. if (!done) {
  877. if (time_after_eq(jiffies, wtime)) {
  878. ql_dbg(ql_dbg_init, vha, 0x0137,
  879. "Init f/w failed: aen[7]: 0x%x\n",
  880. RD_REG_DWORD(&reg->aenmailbox7));
  881. rval = QLA_FUNCTION_FAILED;
  882. done = true;
  883. break;
  884. }
  885. /* Delay for a while */
  886. msleep(500);
  887. }
  888. } while (!done);
  889. if (rval)
  890. ql_dbg(ql_dbg_init, vha, 0x0138,
  891. "%s **** FAILED ****.\n", __func__);
  892. else
  893. ql_dbg(ql_dbg_init, vha, 0x0139,
  894. "%s **** SUCCESS ****.\n", __func__);
  895. return rval;
  896. }
  897. /*
  898. * qlafx00_fw_ready() - Waits for firmware ready.
  899. * @ha: HA context
  900. *
  901. * Returns 0 on success.
  902. */
  903. int
  904. qlafx00_fw_ready(scsi_qla_host_t *vha)
  905. {
  906. int rval;
  907. unsigned long wtime;
  908. uint16_t wait_time; /* Wait time if loop is coming ready */
  909. uint32_t state[5];
  910. rval = QLA_SUCCESS;
  911. wait_time = 10;
  912. /* wait time before firmware ready */
  913. wtime = jiffies + (wait_time * HZ);
  914. /* Wait for ISP to finish init */
  915. if (!vha->flags.init_done)
  916. ql_dbg(ql_dbg_init, vha, 0x013a,
  917. "Waiting for init to complete...\n");
  918. do {
  919. rval = qlafx00_get_firmware_state(vha, state);
  920. if (rval == QLA_SUCCESS) {
  921. if (state[0] == FSTATE_FX00_INITIALIZED) {
  922. ql_dbg(ql_dbg_init, vha, 0x013b,
  923. "fw_state=%x\n", state[0]);
  924. rval = QLA_SUCCESS;
  925. break;
  926. }
  927. }
  928. rval = QLA_FUNCTION_FAILED;
  929. if (time_after_eq(jiffies, wtime))
  930. break;
  931. /* Delay for a while */
  932. msleep(500);
  933. ql_dbg(ql_dbg_init, vha, 0x013c,
  934. "fw_state=%x curr time=%lx.\n", state[0], jiffies);
  935. } while (1);
  936. if (rval)
  937. ql_dbg(ql_dbg_init, vha, 0x013d,
  938. "Firmware ready **** FAILED ****.\n");
  939. else
  940. ql_dbg(ql_dbg_init, vha, 0x013e,
  941. "Firmware ready **** SUCCESS ****.\n");
  942. return rval;
  943. }
  944. static int
  945. qlafx00_find_all_targets(scsi_qla_host_t *vha,
  946. struct list_head *new_fcports)
  947. {
  948. int rval;
  949. uint16_t tgt_id;
  950. fc_port_t *fcport, *new_fcport;
  951. int found;
  952. struct qla_hw_data *ha = vha->hw;
  953. rval = QLA_SUCCESS;
  954. if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
  955. return QLA_FUNCTION_FAILED;
  956. if ((atomic_read(&vha->loop_down_timer) ||
  957. STATE_TRANSITION(vha))) {
  958. atomic_set(&vha->loop_down_timer, 0);
  959. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  960. return QLA_FUNCTION_FAILED;
  961. }
  962. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
  963. "Listing Target bit map...\n");
  964. ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
  965. 0x2089, (uint8_t *)ha->gid_list, 32);
  966. /* Allocate temporary rmtport for any new rmtports discovered. */
  967. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  968. if (new_fcport == NULL)
  969. return QLA_MEMORY_ALLOC_FAILED;
  970. for_each_set_bit(tgt_id, (void *)ha->gid_list,
  971. QLAFX00_TGT_NODE_LIST_SIZE) {
  972. /* Send get target node info */
  973. new_fcport->tgt_id = tgt_id;
  974. rval = qlafx00_fx_disc(vha, new_fcport,
  975. FXDISC_GET_TGT_NODE_INFO);
  976. if (rval != QLA_SUCCESS) {
  977. ql_log(ql_log_warn, vha, 0x208a,
  978. "Target info scan failed -- assuming zero-entry "
  979. "result...\n");
  980. continue;
  981. }
  982. /* Locate matching device in database. */
  983. found = 0;
  984. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  985. if (memcmp(new_fcport->port_name,
  986. fcport->port_name, WWN_SIZE))
  987. continue;
  988. found++;
  989. /*
  990. * If tgt_id is same and state FCS_ONLINE, nothing
  991. * changed.
  992. */
  993. if (fcport->tgt_id == new_fcport->tgt_id &&
  994. atomic_read(&fcport->state) == FCS_ONLINE)
  995. break;
  996. /*
  997. * Tgt ID changed or device was marked to be updated.
  998. */
  999. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
  1000. "TGT-ID Change(%s): Present tgt id: "
  1001. "0x%x state: 0x%x "
  1002. "wwnn = %llx wwpn = %llx.\n",
  1003. __func__, fcport->tgt_id,
  1004. atomic_read(&fcport->state),
  1005. (unsigned long long)wwn_to_u64(fcport->node_name),
  1006. (unsigned long long)wwn_to_u64(fcport->port_name));
  1007. ql_log(ql_log_info, vha, 0x208c,
  1008. "TGT-ID Announce(%s): Discovered tgt "
  1009. "id 0x%x wwnn = %llx "
  1010. "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
  1011. (unsigned long long)
  1012. wwn_to_u64(new_fcport->node_name),
  1013. (unsigned long long)
  1014. wwn_to_u64(new_fcport->port_name));
  1015. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  1016. fcport->old_tgt_id = fcport->tgt_id;
  1017. fcport->tgt_id = new_fcport->tgt_id;
  1018. ql_log(ql_log_info, vha, 0x208d,
  1019. "TGT-ID: New fcport Added: %p\n", fcport);
  1020. qla2x00_update_fcport(vha, fcport);
  1021. } else {
  1022. ql_log(ql_log_info, vha, 0x208e,
  1023. " Existing TGT-ID %x did not get "
  1024. " offline event from firmware.\n",
  1025. fcport->old_tgt_id);
  1026. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1027. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1028. kfree(new_fcport);
  1029. return rval;
  1030. }
  1031. break;
  1032. }
  1033. if (found)
  1034. continue;
  1035. /* If device was not in our fcports list, then add it. */
  1036. list_add_tail(&new_fcport->list, new_fcports);
  1037. /* Allocate a new replacement fcport. */
  1038. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  1039. if (new_fcport == NULL)
  1040. return QLA_MEMORY_ALLOC_FAILED;
  1041. }
  1042. kfree(new_fcport);
  1043. return rval;
  1044. }
  1045. /*
  1046. * qlafx00_configure_all_targets
  1047. * Setup target devices with node ID's.
  1048. *
  1049. * Input:
  1050. * ha = adapter block pointer.
  1051. *
  1052. * Returns:
  1053. * 0 = success.
  1054. * BIT_0 = error
  1055. */
  1056. static int
  1057. qlafx00_configure_all_targets(scsi_qla_host_t *vha)
  1058. {
  1059. int rval;
  1060. fc_port_t *fcport, *rmptemp;
  1061. LIST_HEAD(new_fcports);
  1062. rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
  1063. FXDISC_GET_TGT_NODE_LIST);
  1064. if (rval != QLA_SUCCESS) {
  1065. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1066. return rval;
  1067. }
  1068. rval = qlafx00_find_all_targets(vha, &new_fcports);
  1069. if (rval != QLA_SUCCESS) {
  1070. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1071. return rval;
  1072. }
  1073. /*
  1074. * Delete all previous devices marked lost.
  1075. */
  1076. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1077. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1078. break;
  1079. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  1080. if (fcport->port_type != FCT_INITIATOR)
  1081. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1082. }
  1083. }
  1084. /*
  1085. * Add the new devices to our devices list.
  1086. */
  1087. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1088. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1089. break;
  1090. qla2x00_update_fcport(vha, fcport);
  1091. list_move_tail(&fcport->list, &vha->vp_fcports);
  1092. ql_log(ql_log_info, vha, 0x208f,
  1093. "Attach new target id 0x%x wwnn = %llx "
  1094. "wwpn = %llx.\n",
  1095. fcport->tgt_id,
  1096. (unsigned long long)wwn_to_u64(fcport->node_name),
  1097. (unsigned long long)wwn_to_u64(fcport->port_name));
  1098. }
  1099. /* Free all new device structures not processed. */
  1100. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1101. list_del(&fcport->list);
  1102. kfree(fcport);
  1103. }
  1104. return rval;
  1105. }
  1106. /*
  1107. * qlafx00_configure_devices
  1108. * Updates Fibre Channel Device Database with what is actually on loop.
  1109. *
  1110. * Input:
  1111. * ha = adapter block pointer.
  1112. *
  1113. * Returns:
  1114. * 0 = success.
  1115. * 1 = error.
  1116. * 2 = database was full and device was not configured.
  1117. */
  1118. int
  1119. qlafx00_configure_devices(scsi_qla_host_t *vha)
  1120. {
  1121. int rval;
  1122. unsigned long flags;
  1123. rval = QLA_SUCCESS;
  1124. flags = vha->dpc_flags;
  1125. ql_dbg(ql_dbg_disc, vha, 0x2090,
  1126. "Configure devices -- dpc flags =0x%lx\n", flags);
  1127. rval = qlafx00_configure_all_targets(vha);
  1128. if (rval == QLA_SUCCESS) {
  1129. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  1130. rval = QLA_FUNCTION_FAILED;
  1131. } else {
  1132. atomic_set(&vha->loop_state, LOOP_READY);
  1133. ql_log(ql_log_info, vha, 0x2091,
  1134. "Device Ready\n");
  1135. }
  1136. }
  1137. if (rval) {
  1138. ql_dbg(ql_dbg_disc, vha, 0x2092,
  1139. "%s *** FAILED ***.\n", __func__);
  1140. } else {
  1141. ql_dbg(ql_dbg_disc, vha, 0x2093,
  1142. "%s: exiting normally.\n", __func__);
  1143. }
  1144. return rval;
  1145. }
  1146. static void
  1147. qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp)
  1148. {
  1149. struct qla_hw_data *ha = vha->hw;
  1150. fc_port_t *fcport;
  1151. vha->flags.online = 0;
  1152. ha->mr.fw_hbt_en = 0;
  1153. if (!critemp) {
  1154. ha->flags.chip_reset_done = 0;
  1155. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1156. vha->qla_stats.total_isp_aborts++;
  1157. ql_log(ql_log_info, vha, 0x013f,
  1158. "Performing ISP error recovery - ha = %p.\n", ha);
  1159. ha->isp_ops->reset_chip(vha);
  1160. }
  1161. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  1162. atomic_set(&vha->loop_state, LOOP_DOWN);
  1163. atomic_set(&vha->loop_down_timer,
  1164. QLAFX00_LOOP_DOWN_TIME);
  1165. } else {
  1166. if (!atomic_read(&vha->loop_down_timer))
  1167. atomic_set(&vha->loop_down_timer,
  1168. QLAFX00_LOOP_DOWN_TIME);
  1169. }
  1170. /* Clear all async request states across all VPs. */
  1171. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1172. fcport->flags = 0;
  1173. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1174. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  1175. }
  1176. if (!ha->flags.eeh_busy) {
  1177. if (critemp) {
  1178. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  1179. } else {
  1180. /* Requeue all commands in outstanding command list. */
  1181. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  1182. }
  1183. }
  1184. qla2x00_free_irqs(vha);
  1185. if (critemp)
  1186. set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags);
  1187. else
  1188. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1189. /* Clear the Interrupts */
  1190. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1191. ql_log(ql_log_info, vha, 0x0140,
  1192. "%s Done done - ha=%p.\n", __func__, ha);
  1193. }
  1194. /**
  1195. * qlafx00_init_response_q_entries() - Initializes response queue entries.
  1196. * @ha: HA context
  1197. *
  1198. * Beginning of request ring has initialization control block already built
  1199. * by nvram config routine.
  1200. *
  1201. * Returns 0 on success.
  1202. */
  1203. void
  1204. qlafx00_init_response_q_entries(struct rsp_que *rsp)
  1205. {
  1206. uint16_t cnt;
  1207. response_t *pkt;
  1208. rsp->ring_ptr = rsp->ring;
  1209. rsp->ring_index = 0;
  1210. rsp->status_srb = NULL;
  1211. pkt = rsp->ring_ptr;
  1212. for (cnt = 0; cnt < rsp->length; cnt++) {
  1213. pkt->signature = RESPONSE_PROCESSED;
  1214. WRT_REG_DWORD((void __force __iomem *)&pkt->signature,
  1215. RESPONSE_PROCESSED);
  1216. pkt++;
  1217. }
  1218. }
  1219. int
  1220. qlafx00_rescan_isp(scsi_qla_host_t *vha)
  1221. {
  1222. uint32_t status = QLA_FUNCTION_FAILED;
  1223. struct qla_hw_data *ha = vha->hw;
  1224. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1225. uint32_t aenmbx7;
  1226. qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
  1227. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  1228. ha->mbx_intr_code = MSW(aenmbx7);
  1229. ha->rqstq_intr_code = LSW(aenmbx7);
  1230. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  1231. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  1232. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  1233. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  1234. ql_dbg(ql_dbg_disc, vha, 0x2094,
  1235. "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
  1236. " Req que offset 0x%x Rsp que offset 0x%x\n",
  1237. ha->mbx_intr_code, ha->rqstq_intr_code,
  1238. ha->req_que_off, ha->rsp_que_len);
  1239. /* Clear the Interrupts */
  1240. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1241. status = qla2x00_init_rings(vha);
  1242. if (!status) {
  1243. vha->flags.online = 1;
  1244. /* if no cable then assume it's good */
  1245. if ((vha->device_flags & DFLG_NO_CABLE))
  1246. status = 0;
  1247. /* Register system information */
  1248. if (qlafx00_fx_disc(vha,
  1249. &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
  1250. ql_dbg(ql_dbg_disc, vha, 0x2095,
  1251. "failed to register host info\n");
  1252. }
  1253. scsi_unblock_requests(vha->host);
  1254. return status;
  1255. }
  1256. void
  1257. qlafx00_timer_routine(scsi_qla_host_t *vha)
  1258. {
  1259. struct qla_hw_data *ha = vha->hw;
  1260. uint32_t fw_heart_beat;
  1261. uint32_t aenmbx0;
  1262. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1263. uint32_t tempc;
  1264. /* Check firmware health */
  1265. if (ha->mr.fw_hbt_cnt)
  1266. ha->mr.fw_hbt_cnt--;
  1267. else {
  1268. if ((!ha->flags.mr_reset_hdlr_active) &&
  1269. (!test_bit(UNLOADING, &vha->dpc_flags)) &&
  1270. (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
  1271. (ha->mr.fw_hbt_en)) {
  1272. fw_heart_beat = RD_REG_DWORD(&reg->fwheartbeat);
  1273. if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
  1274. ha->mr.old_fw_hbt_cnt = fw_heart_beat;
  1275. ha->mr.fw_hbt_miss_cnt = 0;
  1276. } else {
  1277. ha->mr.fw_hbt_miss_cnt++;
  1278. if (ha->mr.fw_hbt_miss_cnt ==
  1279. QLAFX00_HEARTBEAT_MISS_CNT) {
  1280. set_bit(ISP_ABORT_NEEDED,
  1281. &vha->dpc_flags);
  1282. qla2xxx_wake_dpc(vha);
  1283. ha->mr.fw_hbt_miss_cnt = 0;
  1284. }
  1285. }
  1286. }
  1287. ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
  1288. }
  1289. if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
  1290. /* Reset recovery to be performed in timer routine */
  1291. aenmbx0 = RD_REG_DWORD(&reg->aenmailbox0);
  1292. if (ha->mr.fw_reset_timer_exp) {
  1293. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1294. qla2xxx_wake_dpc(vha);
  1295. ha->mr.fw_reset_timer_exp = 0;
  1296. } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
  1297. /* Wake up DPC to rescan the targets */
  1298. set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
  1299. clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1300. qla2xxx_wake_dpc(vha);
  1301. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1302. } else if ((aenmbx0 == MBA_FW_STARTING) &&
  1303. (!ha->mr.fw_hbt_en)) {
  1304. ha->mr.fw_hbt_en = 1;
  1305. } else if (!ha->mr.fw_reset_timer_tick) {
  1306. if (aenmbx0 == ha->mr.old_aenmbx0_state)
  1307. ha->mr.fw_reset_timer_exp = 1;
  1308. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1309. } else if (aenmbx0 == 0xFFFFFFFF) {
  1310. uint32_t data0, data1;
  1311. data0 = QLAFX00_RD_REG(ha,
  1312. QLAFX00_BAR1_BASE_ADDR_REG);
  1313. data1 = QLAFX00_RD_REG(ha,
  1314. QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
  1315. data0 &= 0xffff0000;
  1316. data1 &= 0x0000ffff;
  1317. QLAFX00_WR_REG(ha,
  1318. QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
  1319. (data0 | data1));
  1320. } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
  1321. ha->mr.fw_reset_timer_tick =
  1322. QLAFX00_MAX_RESET_INTERVAL;
  1323. } else if (aenmbx0 == MBA_FW_RESET_FCT) {
  1324. ha->mr.fw_reset_timer_tick =
  1325. QLAFX00_MAX_RESET_INTERVAL;
  1326. }
  1327. if (ha->mr.old_aenmbx0_state != aenmbx0) {
  1328. ha->mr.old_aenmbx0_state = aenmbx0;
  1329. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1330. }
  1331. ha->mr.fw_reset_timer_tick--;
  1332. }
  1333. if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) {
  1334. /*
  1335. * Critical temperature recovery to be
  1336. * performed in timer routine
  1337. */
  1338. if (ha->mr.fw_critemp_timer_tick == 0) {
  1339. tempc = QLAFX00_GET_TEMPERATURE(ha);
  1340. ql_dbg(ql_dbg_timer, vha, 0x6012,
  1341. "ISPFx00(%s): Critical temp timer, "
  1342. "current SOC temperature: %d\n",
  1343. __func__, tempc);
  1344. if (tempc < ha->mr.critical_temperature) {
  1345. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1346. clear_bit(FX00_CRITEMP_RECOVERY,
  1347. &vha->dpc_flags);
  1348. qla2xxx_wake_dpc(vha);
  1349. }
  1350. ha->mr.fw_critemp_timer_tick =
  1351. QLAFX00_CRITEMP_INTERVAL;
  1352. } else {
  1353. ha->mr.fw_critemp_timer_tick--;
  1354. }
  1355. }
  1356. if (ha->mr.host_info_resend) {
  1357. /*
  1358. * Incomplete host info might be sent to firmware
  1359. * durinng system boot - info should be resend
  1360. */
  1361. if (ha->mr.hinfo_resend_timer_tick == 0) {
  1362. ha->mr.host_info_resend = false;
  1363. set_bit(FX00_HOST_INFO_RESEND, &vha->dpc_flags);
  1364. ha->mr.hinfo_resend_timer_tick =
  1365. QLAFX00_HINFO_RESEND_INTERVAL;
  1366. qla2xxx_wake_dpc(vha);
  1367. } else {
  1368. ha->mr.hinfo_resend_timer_tick--;
  1369. }
  1370. }
  1371. }
  1372. /*
  1373. * qlfx00a_reset_initialize
  1374. * Re-initialize after a iSA device reset.
  1375. *
  1376. * Input:
  1377. * ha = adapter block pointer.
  1378. *
  1379. * Returns:
  1380. * 0 = success
  1381. */
  1382. int
  1383. qlafx00_reset_initialize(scsi_qla_host_t *vha)
  1384. {
  1385. struct qla_hw_data *ha = vha->hw;
  1386. if (vha->device_flags & DFLG_DEV_FAILED) {
  1387. ql_dbg(ql_dbg_init, vha, 0x0142,
  1388. "Device in failed state\n");
  1389. return QLA_SUCCESS;
  1390. }
  1391. ha->flags.mr_reset_hdlr_active = 1;
  1392. if (vha->flags.online) {
  1393. scsi_block_requests(vha->host);
  1394. qlafx00_abort_isp_cleanup(vha, false);
  1395. }
  1396. ql_log(ql_log_info, vha, 0x0143,
  1397. "(%s): succeeded.\n", __func__);
  1398. ha->flags.mr_reset_hdlr_active = 0;
  1399. return QLA_SUCCESS;
  1400. }
  1401. /*
  1402. * qlafx00_abort_isp
  1403. * Resets ISP and aborts all outstanding commands.
  1404. *
  1405. * Input:
  1406. * ha = adapter block pointer.
  1407. *
  1408. * Returns:
  1409. * 0 = success
  1410. */
  1411. int
  1412. qlafx00_abort_isp(scsi_qla_host_t *vha)
  1413. {
  1414. struct qla_hw_data *ha = vha->hw;
  1415. if (vha->flags.online) {
  1416. if (unlikely(pci_channel_offline(ha->pdev) &&
  1417. ha->flags.pci_channel_io_perm_failure)) {
  1418. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  1419. return QLA_SUCCESS;
  1420. }
  1421. scsi_block_requests(vha->host);
  1422. qlafx00_abort_isp_cleanup(vha, false);
  1423. } else {
  1424. scsi_block_requests(vha->host);
  1425. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1426. vha->qla_stats.total_isp_aborts++;
  1427. ha->isp_ops->reset_chip(vha);
  1428. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1429. /* Clear the Interrupts */
  1430. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1431. }
  1432. ql_log(ql_log_info, vha, 0x0145,
  1433. "(%s): succeeded.\n", __func__);
  1434. return QLA_SUCCESS;
  1435. }
  1436. static inline fc_port_t*
  1437. qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
  1438. {
  1439. fc_port_t *fcport;
  1440. /* Check for matching device in remote port list. */
  1441. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1442. if (fcport->tgt_id == tgt_id) {
  1443. ql_dbg(ql_dbg_async, vha, 0x5072,
  1444. "Matching fcport(%p) found with TGT-ID: 0x%x "
  1445. "and Remote TGT_ID: 0x%x\n",
  1446. fcport, fcport->tgt_id, tgt_id);
  1447. return fcport;
  1448. }
  1449. }
  1450. return NULL;
  1451. }
  1452. static void
  1453. qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
  1454. {
  1455. fc_port_t *fcport;
  1456. ql_log(ql_log_info, vha, 0x5073,
  1457. "Detach TGT-ID: 0x%x\n", tgt_id);
  1458. fcport = qlafx00_get_fcport(vha, tgt_id);
  1459. if (!fcport)
  1460. return;
  1461. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1462. return;
  1463. }
  1464. int
  1465. qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
  1466. {
  1467. int rval = 0;
  1468. uint32_t aen_code, aen_data;
  1469. aen_code = FCH_EVT_VENDOR_UNIQUE;
  1470. aen_data = evt->u.aenfx.evtcode;
  1471. switch (evt->u.aenfx.evtcode) {
  1472. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  1473. if (evt->u.aenfx.mbx[1] == 0) {
  1474. if (evt->u.aenfx.mbx[2] == 1) {
  1475. if (!vha->flags.fw_tgt_reported)
  1476. vha->flags.fw_tgt_reported = 1;
  1477. atomic_set(&vha->loop_down_timer, 0);
  1478. atomic_set(&vha->loop_state, LOOP_UP);
  1479. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1480. qla2xxx_wake_dpc(vha);
  1481. } else if (evt->u.aenfx.mbx[2] == 2) {
  1482. qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
  1483. }
  1484. } else if (evt->u.aenfx.mbx[1] == 0xffff) {
  1485. if (evt->u.aenfx.mbx[2] == 1) {
  1486. if (!vha->flags.fw_tgt_reported)
  1487. vha->flags.fw_tgt_reported = 1;
  1488. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1489. } else if (evt->u.aenfx.mbx[2] == 2) {
  1490. vha->device_flags |= DFLG_NO_CABLE;
  1491. qla2x00_mark_all_devices_lost(vha, 1);
  1492. }
  1493. }
  1494. break;
  1495. case QLAFX00_MBA_LINK_UP:
  1496. aen_code = FCH_EVT_LINKUP;
  1497. aen_data = 0;
  1498. break;
  1499. case QLAFX00_MBA_LINK_DOWN:
  1500. aen_code = FCH_EVT_LINKDOWN;
  1501. aen_data = 0;
  1502. break;
  1503. case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
  1504. ql_log(ql_log_info, vha, 0x5082,
  1505. "Process critical temperature event "
  1506. "aenmb[0]: %x\n",
  1507. evt->u.aenfx.evtcode);
  1508. scsi_block_requests(vha->host);
  1509. qlafx00_abort_isp_cleanup(vha, true);
  1510. scsi_unblock_requests(vha->host);
  1511. break;
  1512. }
  1513. fc_host_post_event(vha->host, fc_get_event_number(),
  1514. aen_code, aen_data);
  1515. return rval;
  1516. }
  1517. static void
  1518. qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
  1519. {
  1520. u64 port_name = 0, node_name = 0;
  1521. port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
  1522. node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
  1523. fc_host_node_name(vha->host) = node_name;
  1524. fc_host_port_name(vha->host) = port_name;
  1525. if (!pinfo->port_type)
  1526. vha->hw->current_topology = ISP_CFG_F;
  1527. if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
  1528. atomic_set(&vha->loop_state, LOOP_READY);
  1529. else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
  1530. atomic_set(&vha->loop_state, LOOP_DOWN);
  1531. vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
  1532. }
  1533. static void
  1534. qla2x00_fxdisc_iocb_timeout(void *data)
  1535. {
  1536. srb_t *sp = (srb_t *)data;
  1537. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1538. complete(&lio->u.fxiocb.fxiocb_comp);
  1539. }
  1540. static void
  1541. qla2x00_fxdisc_sp_done(void *data, void *ptr, int res)
  1542. {
  1543. srb_t *sp = (srb_t *)ptr;
  1544. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1545. complete(&lio->u.fxiocb.fxiocb_comp);
  1546. }
  1547. int
  1548. qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
  1549. {
  1550. srb_t *sp;
  1551. struct srb_iocb *fdisc;
  1552. int rval = QLA_FUNCTION_FAILED;
  1553. struct qla_hw_data *ha = vha->hw;
  1554. struct host_system_info *phost_info;
  1555. struct register_host_info *preg_hsi;
  1556. struct new_utsname *p_sysid = NULL;
  1557. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1558. if (!sp)
  1559. goto done;
  1560. fdisc = &sp->u.iocb_cmd;
  1561. switch (fx_type) {
  1562. case FXDISC_GET_CONFIG_INFO:
  1563. fdisc->u.fxiocb.flags =
  1564. SRB_FXDISC_RESP_DMA_VALID;
  1565. fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
  1566. break;
  1567. case FXDISC_GET_PORT_INFO:
  1568. fdisc->u.fxiocb.flags =
  1569. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1570. fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
  1571. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
  1572. break;
  1573. case FXDISC_GET_TGT_NODE_INFO:
  1574. fdisc->u.fxiocb.flags =
  1575. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1576. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
  1577. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
  1578. break;
  1579. case FXDISC_GET_TGT_NODE_LIST:
  1580. fdisc->u.fxiocb.flags =
  1581. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1582. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
  1583. break;
  1584. case FXDISC_REG_HOST_INFO:
  1585. fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
  1586. fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
  1587. p_sysid = utsname();
  1588. if (!p_sysid) {
  1589. ql_log(ql_log_warn, vha, 0x303c,
  1590. "Not able to get the system information\n");
  1591. goto done_free_sp;
  1592. }
  1593. break;
  1594. case FXDISC_ABORT_IOCTL:
  1595. default:
  1596. break;
  1597. }
  1598. if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  1599. fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
  1600. fdisc->u.fxiocb.req_len,
  1601. &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
  1602. if (!fdisc->u.fxiocb.req_addr)
  1603. goto done_free_sp;
  1604. if (fx_type == FXDISC_REG_HOST_INFO) {
  1605. preg_hsi = (struct register_host_info *)
  1606. fdisc->u.fxiocb.req_addr;
  1607. phost_info = &preg_hsi->hsi;
  1608. memset(preg_hsi, 0, sizeof(struct register_host_info));
  1609. phost_info->os_type = OS_TYPE_LINUX;
  1610. strncpy(phost_info->sysname,
  1611. p_sysid->sysname, SYSNAME_LENGTH);
  1612. strncpy(phost_info->nodename,
  1613. p_sysid->nodename, NODENAME_LENGTH);
  1614. if (!strcmp(phost_info->nodename, "(none)"))
  1615. ha->mr.host_info_resend = true;
  1616. strncpy(phost_info->release,
  1617. p_sysid->release, RELEASE_LENGTH);
  1618. strncpy(phost_info->version,
  1619. p_sysid->version, VERSION_LENGTH);
  1620. strncpy(phost_info->machine,
  1621. p_sysid->machine, MACHINE_LENGTH);
  1622. strncpy(phost_info->domainname,
  1623. p_sysid->domainname, DOMNAME_LENGTH);
  1624. strncpy(phost_info->hostdriver,
  1625. QLA2XXX_VERSION, VERSION_LENGTH);
  1626. preg_hsi->utc = (uint64_t)ktime_get_real_seconds();
  1627. ql_dbg(ql_dbg_init, vha, 0x0149,
  1628. "ISP%04X: Host registration with firmware\n",
  1629. ha->pdev->device);
  1630. ql_dbg(ql_dbg_init, vha, 0x014a,
  1631. "os_type = '%d', sysname = '%s', nodname = '%s'\n",
  1632. phost_info->os_type,
  1633. phost_info->sysname,
  1634. phost_info->nodename);
  1635. ql_dbg(ql_dbg_init, vha, 0x014b,
  1636. "release = '%s', version = '%s'\n",
  1637. phost_info->release,
  1638. phost_info->version);
  1639. ql_dbg(ql_dbg_init, vha, 0x014c,
  1640. "machine = '%s' "
  1641. "domainname = '%s', hostdriver = '%s'\n",
  1642. phost_info->machine,
  1643. phost_info->domainname,
  1644. phost_info->hostdriver);
  1645. ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
  1646. (uint8_t *)phost_info,
  1647. sizeof(struct host_system_info));
  1648. }
  1649. }
  1650. if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  1651. fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
  1652. fdisc->u.fxiocb.rsp_len,
  1653. &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
  1654. if (!fdisc->u.fxiocb.rsp_addr)
  1655. goto done_unmap_req;
  1656. }
  1657. sp->type = SRB_FXIOCB_DCMD;
  1658. sp->name = "fxdisc";
  1659. qla2x00_init_timer(sp, FXDISC_TIMEOUT);
  1660. fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
  1661. fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
  1662. sp->done = qla2x00_fxdisc_sp_done;
  1663. rval = qla2x00_start_sp(sp);
  1664. if (rval != QLA_SUCCESS)
  1665. goto done_unmap_dma;
  1666. wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
  1667. if (fx_type == FXDISC_GET_CONFIG_INFO) {
  1668. struct config_info_data *pinfo =
  1669. (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
  1670. strcpy(vha->hw->model_number, pinfo->model_num);
  1671. strcpy(vha->hw->model_desc, pinfo->model_description);
  1672. memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
  1673. sizeof(vha->hw->mr.symbolic_name));
  1674. memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
  1675. sizeof(vha->hw->mr.serial_num));
  1676. memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
  1677. sizeof(vha->hw->mr.hw_version));
  1678. memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
  1679. sizeof(vha->hw->mr.fw_version));
  1680. strim(vha->hw->mr.fw_version);
  1681. memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
  1682. sizeof(vha->hw->mr.uboot_version));
  1683. memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
  1684. sizeof(vha->hw->mr.fru_serial_num));
  1685. vha->hw->mr.critical_temperature =
  1686. (pinfo->nominal_temp_value) ?
  1687. pinfo->nominal_temp_value : QLAFX00_CRITEMP_THRSHLD;
  1688. ha->mr.extended_io_enabled = (pinfo->enabled_capabilities &
  1689. QLAFX00_EXTENDED_IO_EN_MASK) != 0;
  1690. } else if (fx_type == FXDISC_GET_PORT_INFO) {
  1691. struct port_info_data *pinfo =
  1692. (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
  1693. memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
  1694. memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
  1695. vha->d_id.b.domain = pinfo->port_id[0];
  1696. vha->d_id.b.area = pinfo->port_id[1];
  1697. vha->d_id.b.al_pa = pinfo->port_id[2];
  1698. qlafx00_update_host_attr(vha, pinfo);
  1699. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
  1700. (uint8_t *)pinfo, 16);
  1701. } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
  1702. struct qlafx00_tgt_node_info *pinfo =
  1703. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1704. memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
  1705. memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
  1706. fcport->port_type = FCT_TARGET;
  1707. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
  1708. (uint8_t *)pinfo, 16);
  1709. } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
  1710. struct qlafx00_tgt_node_info *pinfo =
  1711. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1712. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
  1713. (uint8_t *)pinfo, 16);
  1714. memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
  1715. } else if (fx_type == FXDISC_ABORT_IOCTL)
  1716. fdisc->u.fxiocb.result =
  1717. (fdisc->u.fxiocb.result ==
  1718. cpu_to_le32(QLAFX00_IOCTL_ICOB_ABORT_SUCCESS)) ?
  1719. cpu_to_le32(QLA_SUCCESS) : cpu_to_le32(QLA_FUNCTION_FAILED);
  1720. rval = le32_to_cpu(fdisc->u.fxiocb.result);
  1721. done_unmap_dma:
  1722. if (fdisc->u.fxiocb.rsp_addr)
  1723. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
  1724. fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
  1725. done_unmap_req:
  1726. if (fdisc->u.fxiocb.req_addr)
  1727. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
  1728. fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
  1729. done_free_sp:
  1730. sp->free(vha, sp);
  1731. done:
  1732. return rval;
  1733. }
  1734. /*
  1735. * qlafx00_initialize_adapter
  1736. * Initialize board.
  1737. *
  1738. * Input:
  1739. * ha = adapter block pointer.
  1740. *
  1741. * Returns:
  1742. * 0 = success
  1743. */
  1744. int
  1745. qlafx00_initialize_adapter(scsi_qla_host_t *vha)
  1746. {
  1747. int rval;
  1748. struct qla_hw_data *ha = vha->hw;
  1749. uint32_t tempc;
  1750. /* Clear adapter flags. */
  1751. vha->flags.online = 0;
  1752. ha->flags.chip_reset_done = 0;
  1753. vha->flags.reset_active = 0;
  1754. ha->flags.pci_channel_io_perm_failure = 0;
  1755. ha->flags.eeh_busy = 0;
  1756. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1757. atomic_set(&vha->loop_state, LOOP_DOWN);
  1758. vha->device_flags = DFLG_NO_CABLE;
  1759. vha->dpc_flags = 0;
  1760. vha->flags.management_server_logged_in = 0;
  1761. ha->isp_abort_cnt = 0;
  1762. ha->beacon_blink_led = 0;
  1763. set_bit(0, ha->req_qid_map);
  1764. set_bit(0, ha->rsp_qid_map);
  1765. ql_dbg(ql_dbg_init, vha, 0x0147,
  1766. "Configuring PCI space...\n");
  1767. rval = ha->isp_ops->pci_config(vha);
  1768. if (rval) {
  1769. ql_log(ql_log_warn, vha, 0x0148,
  1770. "Unable to configure PCI space.\n");
  1771. return rval;
  1772. }
  1773. rval = qlafx00_init_fw_ready(vha);
  1774. if (rval != QLA_SUCCESS)
  1775. return rval;
  1776. qlafx00_save_queue_ptrs(vha);
  1777. rval = qlafx00_config_queues(vha);
  1778. if (rval != QLA_SUCCESS)
  1779. return rval;
  1780. /*
  1781. * Allocate the array of outstanding commands
  1782. * now that we know the firmware resources.
  1783. */
  1784. rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
  1785. if (rval != QLA_SUCCESS)
  1786. return rval;
  1787. rval = qla2x00_init_rings(vha);
  1788. ha->flags.chip_reset_done = 1;
  1789. tempc = QLAFX00_GET_TEMPERATURE(ha);
  1790. ql_dbg(ql_dbg_init, vha, 0x0152,
  1791. "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n",
  1792. __func__, tempc);
  1793. return rval;
  1794. }
  1795. uint32_t
  1796. qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
  1797. char *buf)
  1798. {
  1799. scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
  1800. int rval = QLA_FUNCTION_FAILED;
  1801. uint32_t state[1];
  1802. if (qla2x00_reset_active(vha))
  1803. ql_log(ql_log_warn, vha, 0x70ce,
  1804. "ISP reset active.\n");
  1805. else if (!vha->hw->flags.eeh_busy) {
  1806. rval = qlafx00_get_firmware_state(vha, state);
  1807. }
  1808. if (rval != QLA_SUCCESS)
  1809. memset(state, -1, sizeof(state));
  1810. return state[0];
  1811. }
  1812. void
  1813. qlafx00_get_host_speed(struct Scsi_Host *shost)
  1814. {
  1815. struct qla_hw_data *ha = ((struct scsi_qla_host *)
  1816. (shost_priv(shost)))->hw;
  1817. u32 speed = FC_PORTSPEED_UNKNOWN;
  1818. switch (ha->link_data_rate) {
  1819. case QLAFX00_PORT_SPEED_2G:
  1820. speed = FC_PORTSPEED_2GBIT;
  1821. break;
  1822. case QLAFX00_PORT_SPEED_4G:
  1823. speed = FC_PORTSPEED_4GBIT;
  1824. break;
  1825. case QLAFX00_PORT_SPEED_8G:
  1826. speed = FC_PORTSPEED_8GBIT;
  1827. break;
  1828. case QLAFX00_PORT_SPEED_10G:
  1829. speed = FC_PORTSPEED_10GBIT;
  1830. break;
  1831. }
  1832. fc_host_speed(shost) = speed;
  1833. }
  1834. /** QLAFX00 specific ISR implementation functions */
  1835. static inline void
  1836. qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1837. uint32_t sense_len, struct rsp_que *rsp, int res)
  1838. {
  1839. struct scsi_qla_host *vha = sp->fcport->vha;
  1840. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1841. uint32_t track_sense_len;
  1842. SET_FW_SENSE_LEN(sp, sense_len);
  1843. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1844. sense_len = SCSI_SENSE_BUFFERSIZE;
  1845. SET_CMD_SENSE_LEN(sp, sense_len);
  1846. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1847. track_sense_len = sense_len;
  1848. if (sense_len > par_sense_len)
  1849. sense_len = par_sense_len;
  1850. memcpy(cp->sense_buffer, sense_data, sense_len);
  1851. SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
  1852. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1853. track_sense_len -= sense_len;
  1854. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1855. ql_dbg(ql_dbg_io, vha, 0x304d,
  1856. "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
  1857. sense_len, par_sense_len, track_sense_len);
  1858. if (GET_FW_SENSE_LEN(sp) > 0) {
  1859. rsp->status_srb = sp;
  1860. cp->result = res;
  1861. }
  1862. if (sense_len) {
  1863. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
  1864. "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
  1865. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1866. cp);
  1867. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
  1868. cp->sense_buffer, sense_len);
  1869. }
  1870. }
  1871. static void
  1872. qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1873. struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
  1874. __le16 sstatus, __le16 cpstatus)
  1875. {
  1876. struct srb_iocb *tmf;
  1877. tmf = &sp->u.iocb_cmd;
  1878. if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
  1879. (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
  1880. cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
  1881. tmf->u.tmf.comp_status = cpstatus;
  1882. sp->done(vha, sp, 0);
  1883. }
  1884. static void
  1885. qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1886. struct abort_iocb_entry_fx00 *pkt)
  1887. {
  1888. const char func[] = "ABT_IOCB";
  1889. srb_t *sp;
  1890. struct srb_iocb *abt;
  1891. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1892. if (!sp)
  1893. return;
  1894. abt = &sp->u.iocb_cmd;
  1895. abt->u.abt.comp_status = pkt->tgt_id_sts;
  1896. sp->done(vha, sp, 0);
  1897. }
  1898. static void
  1899. qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1900. struct ioctl_iocb_entry_fx00 *pkt)
  1901. {
  1902. const char func[] = "IOSB_IOCB";
  1903. srb_t *sp;
  1904. struct fc_bsg_job *bsg_job;
  1905. struct srb_iocb *iocb_job;
  1906. int res;
  1907. struct qla_mt_iocb_rsp_fx00 fstatus;
  1908. uint8_t *fw_sts_ptr;
  1909. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1910. if (!sp)
  1911. return;
  1912. if (sp->type == SRB_FXIOCB_DCMD) {
  1913. iocb_job = &sp->u.iocb_cmd;
  1914. iocb_job->u.fxiocb.seq_number = pkt->seq_no;
  1915. iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
  1916. iocb_job->u.fxiocb.result = pkt->status;
  1917. if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
  1918. iocb_job->u.fxiocb.req_data =
  1919. pkt->dataword_r;
  1920. } else {
  1921. bsg_job = sp->u.bsg_job;
  1922. memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
  1923. fstatus.reserved_1 = pkt->reserved_0;
  1924. fstatus.func_type = pkt->comp_func_num;
  1925. fstatus.ioctl_flags = pkt->fw_iotcl_flags;
  1926. fstatus.ioctl_data = pkt->dataword_r;
  1927. fstatus.adapid = pkt->adapid;
  1928. fstatus.reserved_2 = pkt->dataword_r_extra;
  1929. fstatus.res_count = pkt->residuallen;
  1930. fstatus.status = pkt->status;
  1931. fstatus.seq_number = pkt->seq_no;
  1932. memcpy(fstatus.reserved_3,
  1933. pkt->reserved_2, 20 * sizeof(uint8_t));
  1934. fw_sts_ptr = ((uint8_t *)bsg_job->req->sense) +
  1935. sizeof(struct fc_bsg_reply);
  1936. memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
  1937. sizeof(struct qla_mt_iocb_rsp_fx00));
  1938. bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
  1939. sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
  1940. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1941. sp->fcport->vha, 0x5080,
  1942. (uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
  1943. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1944. sp->fcport->vha, 0x5074,
  1945. (uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
  1946. res = bsg_job->reply->result = DID_OK << 16;
  1947. bsg_job->reply->reply_payload_rcv_len =
  1948. bsg_job->reply_payload.payload_len;
  1949. }
  1950. sp->done(vha, sp, res);
  1951. }
  1952. /**
  1953. * qlafx00_status_entry() - Process a Status IOCB entry.
  1954. * @ha: SCSI driver HA context
  1955. * @pkt: Entry pointer
  1956. */
  1957. static void
  1958. qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1959. {
  1960. srb_t *sp;
  1961. fc_port_t *fcport;
  1962. struct scsi_cmnd *cp;
  1963. struct sts_entry_fx00 *sts;
  1964. __le16 comp_status;
  1965. __le16 scsi_status;
  1966. __le16 lscsi_status;
  1967. int32_t resid;
  1968. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1969. fw_resid_len;
  1970. uint8_t *rsp_info = NULL, *sense_data = NULL;
  1971. struct qla_hw_data *ha = vha->hw;
  1972. uint32_t hindex, handle;
  1973. uint16_t que;
  1974. struct req_que *req;
  1975. int logit = 1;
  1976. int res = 0;
  1977. sts = (struct sts_entry_fx00 *) pkt;
  1978. comp_status = sts->comp_status;
  1979. scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
  1980. hindex = sts->handle;
  1981. handle = LSW(hindex);
  1982. que = MSW(hindex);
  1983. req = ha->req_q_map[que];
  1984. /* Validate handle. */
  1985. if (handle < req->num_outstanding_cmds)
  1986. sp = req->outstanding_cmds[handle];
  1987. else
  1988. sp = NULL;
  1989. if (sp == NULL) {
  1990. ql_dbg(ql_dbg_io, vha, 0x3034,
  1991. "Invalid status handle (0x%x).\n", handle);
  1992. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1993. qla2xxx_wake_dpc(vha);
  1994. return;
  1995. }
  1996. if (sp->type == SRB_TM_CMD) {
  1997. req->outstanding_cmds[handle] = NULL;
  1998. qlafx00_tm_iocb_entry(vha, req, pkt, sp,
  1999. scsi_status, comp_status);
  2000. return;
  2001. }
  2002. /* Fast path completion. */
  2003. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  2004. qla2x00_process_completed_request(vha, req, handle);
  2005. return;
  2006. }
  2007. req->outstanding_cmds[handle] = NULL;
  2008. cp = GET_CMD_SP(sp);
  2009. if (cp == NULL) {
  2010. ql_dbg(ql_dbg_io, vha, 0x3048,
  2011. "Command already returned (0x%x/%p).\n",
  2012. handle, sp);
  2013. return;
  2014. }
  2015. lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
  2016. fcport = sp->fcport;
  2017. sense_len = par_sense_len = rsp_info_len = resid_len =
  2018. fw_resid_len = 0;
  2019. if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
  2020. sense_len = sts->sense_len;
  2021. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2022. | (uint16_t)SS_RESIDUAL_OVER)))
  2023. resid_len = le32_to_cpu(sts->residual_len);
  2024. if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
  2025. fw_resid_len = le32_to_cpu(sts->residual_len);
  2026. rsp_info = sense_data = sts->data;
  2027. par_sense_len = sizeof(sts->data);
  2028. /* Check for overrun. */
  2029. if (comp_status == CS_COMPLETE &&
  2030. scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
  2031. comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
  2032. /*
  2033. * Based on Host and scsi status generate status code for Linux
  2034. */
  2035. switch (le16_to_cpu(comp_status)) {
  2036. case CS_COMPLETE:
  2037. case CS_QUEUE_FULL:
  2038. if (scsi_status == 0) {
  2039. res = DID_OK << 16;
  2040. break;
  2041. }
  2042. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2043. | (uint16_t)SS_RESIDUAL_OVER))) {
  2044. resid = resid_len;
  2045. scsi_set_resid(cp, resid);
  2046. if (!lscsi_status &&
  2047. ((unsigned)(scsi_bufflen(cp) - resid) <
  2048. cp->underflow)) {
  2049. ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
  2050. "Mid-layer underflow "
  2051. "detected (0x%x of 0x%x bytes).\n",
  2052. resid, scsi_bufflen(cp));
  2053. res = DID_ERROR << 16;
  2054. break;
  2055. }
  2056. }
  2057. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2058. if (lscsi_status ==
  2059. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2060. ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
  2061. "QUEUE FULL detected.\n");
  2062. break;
  2063. }
  2064. logit = 0;
  2065. if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2066. break;
  2067. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2068. if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2069. break;
  2070. qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  2071. rsp, res);
  2072. break;
  2073. case CS_DATA_UNDERRUN:
  2074. /* Use F/W calculated residual length. */
  2075. if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2076. resid = fw_resid_len;
  2077. else
  2078. resid = resid_len;
  2079. scsi_set_resid(cp, resid);
  2080. if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
  2081. if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2082. && fw_resid_len != resid_len) {
  2083. ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
  2084. "Dropped frame(s) detected "
  2085. "(0x%x of 0x%x bytes).\n",
  2086. resid, scsi_bufflen(cp));
  2087. res = DID_ERROR << 16 |
  2088. le16_to_cpu(lscsi_status);
  2089. goto check_scsi_status;
  2090. }
  2091. if (!lscsi_status &&
  2092. ((unsigned)(scsi_bufflen(cp) - resid) <
  2093. cp->underflow)) {
  2094. ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
  2095. "Mid-layer underflow "
  2096. "detected (0x%x of 0x%x bytes, "
  2097. "cp->underflow: 0x%x).\n",
  2098. resid, scsi_bufflen(cp), cp->underflow);
  2099. res = DID_ERROR << 16;
  2100. break;
  2101. }
  2102. } else if (lscsi_status !=
  2103. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
  2104. lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
  2105. /*
  2106. * scsi status of task set and busy are considered
  2107. * to be task not completed.
  2108. */
  2109. ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
  2110. "Dropped frame(s) detected (0x%x "
  2111. "of 0x%x bytes).\n", resid,
  2112. scsi_bufflen(cp));
  2113. res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
  2114. goto check_scsi_status;
  2115. } else {
  2116. ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
  2117. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  2118. scsi_status, lscsi_status);
  2119. }
  2120. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2121. logit = 0;
  2122. check_scsi_status:
  2123. /*
  2124. * Check to see if SCSI Status is non zero. If so report SCSI
  2125. * Status.
  2126. */
  2127. if (lscsi_status != 0) {
  2128. if (lscsi_status ==
  2129. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2130. ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
  2131. "QUEUE FULL detected.\n");
  2132. logit = 1;
  2133. break;
  2134. }
  2135. if (lscsi_status !=
  2136. cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2137. break;
  2138. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2139. if (!(scsi_status &
  2140. cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2141. break;
  2142. qlafx00_handle_sense(sp, sense_data, par_sense_len,
  2143. sense_len, rsp, res);
  2144. }
  2145. break;
  2146. case CS_PORT_LOGGED_OUT:
  2147. case CS_PORT_CONFIG_CHG:
  2148. case CS_PORT_BUSY:
  2149. case CS_INCOMPLETE:
  2150. case CS_PORT_UNAVAILABLE:
  2151. case CS_TIMEOUT:
  2152. case CS_RESET:
  2153. /*
  2154. * We are going to have the fc class block the rport
  2155. * while we try to recover so instruct the mid layer
  2156. * to requeue until the class decides how to handle this.
  2157. */
  2158. res = DID_TRANSPORT_DISRUPTED << 16;
  2159. ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
  2160. "Port down status: port-state=0x%x.\n",
  2161. atomic_read(&fcport->state));
  2162. if (atomic_read(&fcport->state) == FCS_ONLINE)
  2163. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  2164. break;
  2165. case CS_ABORTED:
  2166. res = DID_RESET << 16;
  2167. break;
  2168. default:
  2169. res = DID_ERROR << 16;
  2170. break;
  2171. }
  2172. if (logit)
  2173. ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
  2174. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
  2175. "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
  2176. "rsp_info=%p resid=0x%x fw_resid=0x%x sense_len=0x%x, "
  2177. "par_sense_len=0x%x, rsp_info_len=0x%x\n",
  2178. comp_status, scsi_status, res, vha->host_no,
  2179. cp->device->id, cp->device->lun, fcport->tgt_id,
  2180. lscsi_status, cp->cmnd, scsi_bufflen(cp),
  2181. rsp_info, resid_len, fw_resid_len, sense_len,
  2182. par_sense_len, rsp_info_len);
  2183. if (rsp->status_srb == NULL)
  2184. sp->done(ha, sp, res);
  2185. }
  2186. /**
  2187. * qlafx00_status_cont_entry() - Process a Status Continuations entry.
  2188. * @ha: SCSI driver HA context
  2189. * @pkt: Entry pointer
  2190. *
  2191. * Extended sense data.
  2192. */
  2193. static void
  2194. qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  2195. {
  2196. uint8_t sense_sz = 0;
  2197. struct qla_hw_data *ha = rsp->hw;
  2198. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  2199. srb_t *sp = rsp->status_srb;
  2200. struct scsi_cmnd *cp;
  2201. uint32_t sense_len;
  2202. uint8_t *sense_ptr;
  2203. if (!sp) {
  2204. ql_dbg(ql_dbg_io, vha, 0x3037,
  2205. "no SP, sp = %p\n", sp);
  2206. return;
  2207. }
  2208. if (!GET_FW_SENSE_LEN(sp)) {
  2209. ql_dbg(ql_dbg_io, vha, 0x304b,
  2210. "no fw sense data, sp = %p\n", sp);
  2211. return;
  2212. }
  2213. cp = GET_CMD_SP(sp);
  2214. if (cp == NULL) {
  2215. ql_log(ql_log_warn, vha, 0x303b,
  2216. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2217. rsp->status_srb = NULL;
  2218. return;
  2219. }
  2220. if (!GET_CMD_SENSE_LEN(sp)) {
  2221. ql_dbg(ql_dbg_io, vha, 0x304c,
  2222. "no sense data, sp = %p\n", sp);
  2223. } else {
  2224. sense_len = GET_CMD_SENSE_LEN(sp);
  2225. sense_ptr = GET_CMD_SENSE_PTR(sp);
  2226. ql_dbg(ql_dbg_io, vha, 0x304f,
  2227. "sp=%p sense_len=0x%x sense_ptr=%p.\n",
  2228. sp, sense_len, sense_ptr);
  2229. if (sense_len > sizeof(pkt->data))
  2230. sense_sz = sizeof(pkt->data);
  2231. else
  2232. sense_sz = sense_len;
  2233. /* Move sense data. */
  2234. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
  2235. (uint8_t *)pkt, sizeof(sts_cont_entry_t));
  2236. memcpy(sense_ptr, pkt->data, sense_sz);
  2237. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
  2238. sense_ptr, sense_sz);
  2239. sense_len -= sense_sz;
  2240. sense_ptr += sense_sz;
  2241. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2242. SET_CMD_SENSE_LEN(sp, sense_len);
  2243. }
  2244. sense_len = GET_FW_SENSE_LEN(sp);
  2245. sense_len = (sense_len > sizeof(pkt->data)) ?
  2246. (sense_len - sizeof(pkt->data)) : 0;
  2247. SET_FW_SENSE_LEN(sp, sense_len);
  2248. /* Place command on done queue. */
  2249. if (sense_len == 0) {
  2250. rsp->status_srb = NULL;
  2251. sp->done(ha, sp, cp->result);
  2252. }
  2253. }
  2254. /**
  2255. * qlafx00_multistatus_entry() - Process Multi response queue entries.
  2256. * @ha: SCSI driver HA context
  2257. */
  2258. static void
  2259. qlafx00_multistatus_entry(struct scsi_qla_host *vha,
  2260. struct rsp_que *rsp, void *pkt)
  2261. {
  2262. srb_t *sp;
  2263. struct multi_sts_entry_fx00 *stsmfx;
  2264. struct qla_hw_data *ha = vha->hw;
  2265. uint32_t handle, hindex, handle_count, i;
  2266. uint16_t que;
  2267. struct req_que *req;
  2268. __le32 *handle_ptr;
  2269. stsmfx = (struct multi_sts_entry_fx00 *) pkt;
  2270. handle_count = stsmfx->handle_count;
  2271. if (handle_count > MAX_HANDLE_COUNT) {
  2272. ql_dbg(ql_dbg_io, vha, 0x3035,
  2273. "Invalid handle count (0x%x).\n", handle_count);
  2274. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2275. qla2xxx_wake_dpc(vha);
  2276. return;
  2277. }
  2278. handle_ptr = &stsmfx->handles[0];
  2279. for (i = 0; i < handle_count; i++) {
  2280. hindex = le32_to_cpu(*handle_ptr);
  2281. handle = LSW(hindex);
  2282. que = MSW(hindex);
  2283. req = ha->req_q_map[que];
  2284. /* Validate handle. */
  2285. if (handle < req->num_outstanding_cmds)
  2286. sp = req->outstanding_cmds[handle];
  2287. else
  2288. sp = NULL;
  2289. if (sp == NULL) {
  2290. ql_dbg(ql_dbg_io, vha, 0x3044,
  2291. "Invalid status handle (0x%x).\n", handle);
  2292. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2293. qla2xxx_wake_dpc(vha);
  2294. return;
  2295. }
  2296. qla2x00_process_completed_request(vha, req, handle);
  2297. handle_ptr++;
  2298. }
  2299. }
  2300. /**
  2301. * qlafx00_error_entry() - Process an error entry.
  2302. * @ha: SCSI driver HA context
  2303. * @pkt: Entry pointer
  2304. */
  2305. static void
  2306. qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
  2307. struct sts_entry_fx00 *pkt, uint8_t estatus, uint8_t etype)
  2308. {
  2309. srb_t *sp;
  2310. struct qla_hw_data *ha = vha->hw;
  2311. const char func[] = "ERROR-IOCB";
  2312. uint16_t que = 0;
  2313. struct req_que *req = NULL;
  2314. int res = DID_ERROR << 16;
  2315. ql_dbg(ql_dbg_async, vha, 0x507f,
  2316. "type of error status in response: 0x%x\n", estatus);
  2317. req = ha->req_q_map[que];
  2318. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2319. if (sp) {
  2320. sp->done(ha, sp, res);
  2321. return;
  2322. }
  2323. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2324. qla2xxx_wake_dpc(vha);
  2325. }
  2326. /**
  2327. * qlafx00_process_response_queue() - Process response queue entries.
  2328. * @ha: SCSI driver HA context
  2329. */
  2330. static void
  2331. qlafx00_process_response_queue(struct scsi_qla_host *vha,
  2332. struct rsp_que *rsp)
  2333. {
  2334. struct sts_entry_fx00 *pkt;
  2335. response_t *lptr;
  2336. uint16_t lreq_q_in = 0;
  2337. uint16_t lreq_q_out = 0;
  2338. lreq_q_in = RD_REG_DWORD(rsp->rsp_q_in);
  2339. lreq_q_out = rsp->ring_index;
  2340. while (lreq_q_in != lreq_q_out) {
  2341. lptr = rsp->ring_ptr;
  2342. memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
  2343. sizeof(rsp->rsp_pkt));
  2344. pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
  2345. rsp->ring_index++;
  2346. lreq_q_out++;
  2347. if (rsp->ring_index == rsp->length) {
  2348. lreq_q_out = 0;
  2349. rsp->ring_index = 0;
  2350. rsp->ring_ptr = rsp->ring;
  2351. } else {
  2352. rsp->ring_ptr++;
  2353. }
  2354. if (pkt->entry_status != 0 &&
  2355. pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
  2356. qlafx00_error_entry(vha, rsp,
  2357. (struct sts_entry_fx00 *)pkt, pkt->entry_status,
  2358. pkt->entry_type);
  2359. continue;
  2360. }
  2361. switch (pkt->entry_type) {
  2362. case STATUS_TYPE_FX00:
  2363. qlafx00_status_entry(vha, rsp, pkt);
  2364. break;
  2365. case STATUS_CONT_TYPE_FX00:
  2366. qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2367. break;
  2368. case MULTI_STATUS_TYPE_FX00:
  2369. qlafx00_multistatus_entry(vha, rsp, pkt);
  2370. break;
  2371. case ABORT_IOCB_TYPE_FX00:
  2372. qlafx00_abort_iocb_entry(vha, rsp->req,
  2373. (struct abort_iocb_entry_fx00 *)pkt);
  2374. break;
  2375. case IOCTL_IOSB_TYPE_FX00:
  2376. qlafx00_ioctl_iosb_entry(vha, rsp->req,
  2377. (struct ioctl_iocb_entry_fx00 *)pkt);
  2378. break;
  2379. default:
  2380. /* Type Not Supported. */
  2381. ql_dbg(ql_dbg_async, vha, 0x5081,
  2382. "Received unknown response pkt type %x "
  2383. "entry status=%x.\n",
  2384. pkt->entry_type, pkt->entry_status);
  2385. break;
  2386. }
  2387. }
  2388. /* Adjust ring index */
  2389. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2390. }
  2391. /**
  2392. * qlafx00_async_event() - Process aynchronous events.
  2393. * @ha: SCSI driver HA context
  2394. */
  2395. static void
  2396. qlafx00_async_event(scsi_qla_host_t *vha)
  2397. {
  2398. struct qla_hw_data *ha = vha->hw;
  2399. struct device_reg_fx00 __iomem *reg;
  2400. int data_size = 1;
  2401. reg = &ha->iobase->ispfx00;
  2402. /* Setup to process RIO completion. */
  2403. switch (ha->aenmb[0]) {
  2404. case QLAFX00_MBA_SYSTEM_ERR: /* System Error */
  2405. ql_log(ql_log_warn, vha, 0x5079,
  2406. "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
  2407. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2408. break;
  2409. case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */
  2410. ql_dbg(ql_dbg_async, vha, 0x5076,
  2411. "Asynchronous FW shutdown requested.\n");
  2412. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2413. qla2xxx_wake_dpc(vha);
  2414. break;
  2415. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  2416. ha->aenmb[1] = RD_REG_DWORD(&reg->aenmailbox1);
  2417. ha->aenmb[2] = RD_REG_DWORD(&reg->aenmailbox2);
  2418. ha->aenmb[3] = RD_REG_DWORD(&reg->aenmailbox3);
  2419. ql_dbg(ql_dbg_async, vha, 0x5077,
  2420. "Asynchronous port Update received "
  2421. "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
  2422. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
  2423. data_size = 4;
  2424. break;
  2425. case QLAFX00_MBA_TEMP_OVER: /* Over temperature event */
  2426. ql_log(ql_log_info, vha, 0x5085,
  2427. "Asynchronous over temperature event received "
  2428. "aenmb[0]: %x\n",
  2429. ha->aenmb[0]);
  2430. break;
  2431. case QLAFX00_MBA_TEMP_NORM: /* Normal temperature event */
  2432. ql_log(ql_log_info, vha, 0x5086,
  2433. "Asynchronous normal temperature event received "
  2434. "aenmb[0]: %x\n",
  2435. ha->aenmb[0]);
  2436. break;
  2437. case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
  2438. ql_log(ql_log_info, vha, 0x5083,
  2439. "Asynchronous critical temperature event received "
  2440. "aenmb[0]: %x\n",
  2441. ha->aenmb[0]);
  2442. break;
  2443. default:
  2444. ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
  2445. ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
  2446. ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
  2447. ha->aenmb[4] = RD_REG_WORD(&reg->aenmailbox4);
  2448. ha->aenmb[5] = RD_REG_WORD(&reg->aenmailbox5);
  2449. ha->aenmb[6] = RD_REG_WORD(&reg->aenmailbox6);
  2450. ha->aenmb[7] = RD_REG_WORD(&reg->aenmailbox7);
  2451. ql_dbg(ql_dbg_async, vha, 0x5078,
  2452. "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
  2453. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
  2454. ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
  2455. break;
  2456. }
  2457. qlafx00_post_aenfx_work(vha, ha->aenmb[0],
  2458. (uint32_t *)ha->aenmb, data_size);
  2459. }
  2460. /**
  2461. *
  2462. * qlafx00x_mbx_completion() - Process mailbox command completions.
  2463. * @ha: SCSI driver HA context
  2464. * @mb16: Mailbox16 register
  2465. */
  2466. static void
  2467. qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
  2468. {
  2469. uint16_t cnt;
  2470. uint32_t __iomem *wptr;
  2471. struct qla_hw_data *ha = vha->hw;
  2472. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  2473. if (!ha->mcp32)
  2474. ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
  2475. /* Load return mailbox registers. */
  2476. ha->flags.mbox_int = 1;
  2477. ha->mailbox_out32[0] = mb0;
  2478. wptr = (uint32_t __iomem *)&reg->mailbox17;
  2479. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2480. ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr);
  2481. wptr++;
  2482. }
  2483. }
  2484. /**
  2485. * qlafx00_intr_handler() - Process interrupts for the ISPFX00.
  2486. * @irq:
  2487. * @dev_id: SCSI driver HA context
  2488. *
  2489. * Called by system whenever the host adapter generates an interrupt.
  2490. *
  2491. * Returns handled flag.
  2492. */
  2493. irqreturn_t
  2494. qlafx00_intr_handler(int irq, void *dev_id)
  2495. {
  2496. scsi_qla_host_t *vha;
  2497. struct qla_hw_data *ha;
  2498. struct device_reg_fx00 __iomem *reg;
  2499. int status;
  2500. unsigned long iter;
  2501. uint32_t stat;
  2502. uint32_t mb[8];
  2503. struct rsp_que *rsp;
  2504. unsigned long flags;
  2505. uint32_t clr_intr = 0;
  2506. uint32_t intr_stat = 0;
  2507. rsp = (struct rsp_que *) dev_id;
  2508. if (!rsp) {
  2509. ql_log(ql_log_info, NULL, 0x507d,
  2510. "%s: NULL response queue pointer.\n", __func__);
  2511. return IRQ_NONE;
  2512. }
  2513. ha = rsp->hw;
  2514. reg = &ha->iobase->ispfx00;
  2515. status = 0;
  2516. if (unlikely(pci_channel_offline(ha->pdev)))
  2517. return IRQ_HANDLED;
  2518. spin_lock_irqsave(&ha->hardware_lock, flags);
  2519. vha = pci_get_drvdata(ha->pdev);
  2520. for (iter = 50; iter--; clr_intr = 0) {
  2521. stat = QLAFX00_RD_INTR_REG(ha);
  2522. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2523. break;
  2524. intr_stat = stat & QLAFX00_HST_INT_STS_BITS;
  2525. if (!intr_stat)
  2526. break;
  2527. if (stat & QLAFX00_INTR_MB_CMPLT) {
  2528. mb[0] = RD_REG_WORD(&reg->mailbox16);
  2529. qlafx00_mbx_completion(vha, mb[0]);
  2530. status |= MBX_INTERRUPT;
  2531. clr_intr |= QLAFX00_INTR_MB_CMPLT;
  2532. }
  2533. if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) {
  2534. ha->aenmb[0] = RD_REG_WORD(&reg->aenmailbox0);
  2535. qlafx00_async_event(vha);
  2536. clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
  2537. }
  2538. if (intr_stat & QLAFX00_INTR_RSP_CMPLT) {
  2539. qlafx00_process_response_queue(vha, rsp);
  2540. clr_intr |= QLAFX00_INTR_RSP_CMPLT;
  2541. }
  2542. QLAFX00_CLR_INTR_REG(ha, clr_intr);
  2543. QLAFX00_RD_INTR_REG(ha);
  2544. }
  2545. qla2x00_handle_mbx_completion(ha, status);
  2546. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2547. return IRQ_HANDLED;
  2548. }
  2549. /** QLAFX00 specific IOCB implementation functions */
  2550. static inline cont_a64_entry_t *
  2551. qlafx00_prep_cont_type1_iocb(struct req_que *req,
  2552. cont_a64_entry_t *lcont_pkt)
  2553. {
  2554. cont_a64_entry_t *cont_pkt;
  2555. /* Adjust ring index. */
  2556. req->ring_index++;
  2557. if (req->ring_index == req->length) {
  2558. req->ring_index = 0;
  2559. req->ring_ptr = req->ring;
  2560. } else {
  2561. req->ring_ptr++;
  2562. }
  2563. cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
  2564. /* Load packet defaults. */
  2565. lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
  2566. return cont_pkt;
  2567. }
  2568. static inline void
  2569. qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
  2570. uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
  2571. {
  2572. uint16_t avail_dsds;
  2573. __le32 *cur_dsd;
  2574. scsi_qla_host_t *vha;
  2575. struct scsi_cmnd *cmd;
  2576. struct scatterlist *sg;
  2577. int i, cont;
  2578. struct req_que *req;
  2579. cont_a64_entry_t lcont_pkt;
  2580. cont_a64_entry_t *cont_pkt;
  2581. vha = sp->fcport->vha;
  2582. req = vha->req;
  2583. cmd = GET_CMD_SP(sp);
  2584. cont = 0;
  2585. cont_pkt = NULL;
  2586. /* Update entry type to indicate Command Type 3 IOCB */
  2587. lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
  2588. /* No data transfer */
  2589. if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
  2590. lcmd_pkt->byte_count = cpu_to_le32(0);
  2591. return;
  2592. }
  2593. /* Set transfer direction */
  2594. if (cmd->sc_data_direction == DMA_TO_DEVICE) {
  2595. lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
  2596. vha->qla_stats.output_bytes += scsi_bufflen(cmd);
  2597. } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
  2598. lcmd_pkt->cntrl_flags = TMF_READ_DATA;
  2599. vha->qla_stats.input_bytes += scsi_bufflen(cmd);
  2600. }
  2601. /* One DSD is available in the Command Type 3 IOCB */
  2602. avail_dsds = 1;
  2603. cur_dsd = (__le32 *)&lcmd_pkt->dseg_0_address;
  2604. /* Load data segments */
  2605. scsi_for_each_sg(cmd, sg, tot_dsds, i) {
  2606. dma_addr_t sle_dma;
  2607. /* Allocate additional continuation packets? */
  2608. if (avail_dsds == 0) {
  2609. /*
  2610. * Five DSDs are available in the Continuation
  2611. * Type 1 IOCB.
  2612. */
  2613. memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
  2614. cont_pkt =
  2615. qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
  2616. cur_dsd = (__le32 *)lcont_pkt.dseg_0_address;
  2617. avail_dsds = 5;
  2618. cont = 1;
  2619. }
  2620. sle_dma = sg_dma_address(sg);
  2621. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2622. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2623. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2624. avail_dsds--;
  2625. if (avail_dsds == 0 && cont == 1) {
  2626. cont = 0;
  2627. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2628. REQUEST_ENTRY_SIZE);
  2629. }
  2630. }
  2631. if (avail_dsds != 0 && cont == 1) {
  2632. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2633. REQUEST_ENTRY_SIZE);
  2634. }
  2635. }
  2636. /**
  2637. * qlafx00_start_scsi() - Send a SCSI command to the ISP
  2638. * @sp: command to send to the ISP
  2639. *
  2640. * Returns non-zero if a failure occurred, else zero.
  2641. */
  2642. int
  2643. qlafx00_start_scsi(srb_t *sp)
  2644. {
  2645. int nseg;
  2646. unsigned long flags;
  2647. uint32_t index;
  2648. uint32_t handle;
  2649. uint16_t cnt;
  2650. uint16_t req_cnt;
  2651. uint16_t tot_dsds;
  2652. struct req_que *req = NULL;
  2653. struct rsp_que *rsp = NULL;
  2654. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  2655. struct scsi_qla_host *vha = sp->fcport->vha;
  2656. struct qla_hw_data *ha = vha->hw;
  2657. struct cmd_type_7_fx00 *cmd_pkt;
  2658. struct cmd_type_7_fx00 lcmd_pkt;
  2659. struct scsi_lun llun;
  2660. /* Setup device pointers. */
  2661. rsp = ha->rsp_q_map[0];
  2662. req = vha->req;
  2663. /* So we know we haven't pci_map'ed anything yet */
  2664. tot_dsds = 0;
  2665. /* Acquire ring specific lock */
  2666. spin_lock_irqsave(&ha->hardware_lock, flags);
  2667. /* Check for room in outstanding command list. */
  2668. handle = req->current_outstanding_cmd;
  2669. for (index = 1; index < req->num_outstanding_cmds; index++) {
  2670. handle++;
  2671. if (handle == req->num_outstanding_cmds)
  2672. handle = 1;
  2673. if (!req->outstanding_cmds[handle])
  2674. break;
  2675. }
  2676. if (index == req->num_outstanding_cmds)
  2677. goto queuing_error;
  2678. /* Map the sg table so we have an accurate count of sg entries needed */
  2679. if (scsi_sg_count(cmd)) {
  2680. nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
  2681. scsi_sg_count(cmd), cmd->sc_data_direction);
  2682. if (unlikely(!nseg))
  2683. goto queuing_error;
  2684. } else
  2685. nseg = 0;
  2686. tot_dsds = nseg;
  2687. req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
  2688. if (req->cnt < (req_cnt + 2)) {
  2689. cnt = RD_REG_DWORD_RELAXED(req->req_q_out);
  2690. if (req->ring_index < cnt)
  2691. req->cnt = cnt - req->ring_index;
  2692. else
  2693. req->cnt = req->length -
  2694. (req->ring_index - cnt);
  2695. if (req->cnt < (req_cnt + 2))
  2696. goto queuing_error;
  2697. }
  2698. /* Build command packet. */
  2699. req->current_outstanding_cmd = handle;
  2700. req->outstanding_cmds[handle] = sp;
  2701. sp->handle = handle;
  2702. cmd->host_scribble = (unsigned char *)(unsigned long)handle;
  2703. req->cnt -= req_cnt;
  2704. cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
  2705. memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
  2706. lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle);
  2707. lcmd_pkt.reserved_0 = 0;
  2708. lcmd_pkt.port_path_ctrl = 0;
  2709. lcmd_pkt.reserved_1 = 0;
  2710. lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
  2711. lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
  2712. int_to_scsilun(cmd->device->lun, &llun);
  2713. host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
  2714. sizeof(lcmd_pkt.lun));
  2715. /* Load SCSI command packet. */
  2716. host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
  2717. lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
  2718. /* Build IOCB segments */
  2719. qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
  2720. /* Set total data segment count. */
  2721. lcmd_pkt.entry_count = (uint8_t)req_cnt;
  2722. /* Specify response queue number where completion should happen */
  2723. lcmd_pkt.entry_status = (uint8_t) rsp->id;
  2724. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
  2725. (uint8_t *)cmd->cmnd, cmd->cmd_len);
  2726. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
  2727. (uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
  2728. memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
  2729. wmb();
  2730. /* Adjust ring index. */
  2731. req->ring_index++;
  2732. if (req->ring_index == req->length) {
  2733. req->ring_index = 0;
  2734. req->ring_ptr = req->ring;
  2735. } else
  2736. req->ring_ptr++;
  2737. sp->flags |= SRB_DMA_VALID;
  2738. /* Set chip new ring index. */
  2739. WRT_REG_DWORD(req->req_q_in, req->ring_index);
  2740. QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
  2741. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2742. return QLA_SUCCESS;
  2743. queuing_error:
  2744. if (tot_dsds)
  2745. scsi_dma_unmap(cmd);
  2746. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2747. return QLA_FUNCTION_FAILED;
  2748. }
  2749. void
  2750. qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
  2751. {
  2752. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2753. scsi_qla_host_t *vha = sp->fcport->vha;
  2754. struct req_que *req = vha->req;
  2755. struct tsk_mgmt_entry_fx00 tm_iocb;
  2756. struct scsi_lun llun;
  2757. memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
  2758. tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
  2759. tm_iocb.entry_count = 1;
  2760. tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2761. tm_iocb.reserved_0 = 0;
  2762. tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
  2763. tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
  2764. if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
  2765. int_to_scsilun(fxio->u.tmf.lun, &llun);
  2766. host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
  2767. sizeof(struct scsi_lun));
  2768. }
  2769. memcpy((void *)ptm_iocb, &tm_iocb,
  2770. sizeof(struct tsk_mgmt_entry_fx00));
  2771. wmb();
  2772. }
  2773. void
  2774. qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
  2775. {
  2776. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2777. scsi_qla_host_t *vha = sp->fcport->vha;
  2778. struct req_que *req = vha->req;
  2779. struct abort_iocb_entry_fx00 abt_iocb;
  2780. memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
  2781. abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
  2782. abt_iocb.entry_count = 1;
  2783. abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2784. abt_iocb.abort_handle =
  2785. cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl));
  2786. abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
  2787. abt_iocb.req_que_no = cpu_to_le16(req->id);
  2788. memcpy((void *)pabt_iocb, &abt_iocb,
  2789. sizeof(struct abort_iocb_entry_fx00));
  2790. wmb();
  2791. }
  2792. void
  2793. qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
  2794. {
  2795. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2796. struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
  2797. struct fc_bsg_job *bsg_job;
  2798. struct fxdisc_entry_fx00 fx_iocb;
  2799. uint8_t entry_cnt = 1;
  2800. memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
  2801. fx_iocb.entry_type = FX00_IOCB_TYPE;
  2802. fx_iocb.handle = cpu_to_le32(sp->handle);
  2803. fx_iocb.entry_count = entry_cnt;
  2804. if (sp->type == SRB_FXIOCB_DCMD) {
  2805. fx_iocb.func_num =
  2806. sp->u.iocb_cmd.u.fxiocb.req_func_type;
  2807. fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
  2808. fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
  2809. fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
  2810. fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
  2811. fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
  2812. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  2813. fx_iocb.req_dsdcnt = cpu_to_le16(1);
  2814. fx_iocb.req_xfrcnt =
  2815. cpu_to_le16(fxio->u.fxiocb.req_len);
  2816. fx_iocb.dseg_rq_address[0] =
  2817. cpu_to_le32(LSD(fxio->u.fxiocb.req_dma_handle));
  2818. fx_iocb.dseg_rq_address[1] =
  2819. cpu_to_le32(MSD(fxio->u.fxiocb.req_dma_handle));
  2820. fx_iocb.dseg_rq_len =
  2821. cpu_to_le32(fxio->u.fxiocb.req_len);
  2822. }
  2823. if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  2824. fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
  2825. fx_iocb.rsp_xfrcnt =
  2826. cpu_to_le16(fxio->u.fxiocb.rsp_len);
  2827. fx_iocb.dseg_rsp_address[0] =
  2828. cpu_to_le32(LSD(fxio->u.fxiocb.rsp_dma_handle));
  2829. fx_iocb.dseg_rsp_address[1] =
  2830. cpu_to_le32(MSD(fxio->u.fxiocb.rsp_dma_handle));
  2831. fx_iocb.dseg_rsp_len =
  2832. cpu_to_le32(fxio->u.fxiocb.rsp_len);
  2833. }
  2834. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
  2835. fx_iocb.dataword = fxio->u.fxiocb.req_data;
  2836. }
  2837. fx_iocb.flags = fxio->u.fxiocb.flags;
  2838. } else {
  2839. struct scatterlist *sg;
  2840. bsg_job = sp->u.bsg_job;
  2841. piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
  2842. &bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  2843. fx_iocb.func_num = piocb_rqst->func_type;
  2844. fx_iocb.adapid = piocb_rqst->adapid;
  2845. fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
  2846. fx_iocb.reserved_0 = piocb_rqst->reserved_0;
  2847. fx_iocb.reserved_1 = piocb_rqst->reserved_1;
  2848. fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
  2849. fx_iocb.dataword = piocb_rqst->dataword;
  2850. fx_iocb.req_xfrcnt = piocb_rqst->req_len;
  2851. fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
  2852. if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
  2853. int avail_dsds, tot_dsds;
  2854. cont_a64_entry_t lcont_pkt;
  2855. cont_a64_entry_t *cont_pkt = NULL;
  2856. __le32 *cur_dsd;
  2857. int index = 0, cont = 0;
  2858. fx_iocb.req_dsdcnt =
  2859. cpu_to_le16(bsg_job->request_payload.sg_cnt);
  2860. tot_dsds =
  2861. bsg_job->request_payload.sg_cnt;
  2862. cur_dsd = (__le32 *)&fx_iocb.dseg_rq_address[0];
  2863. avail_dsds = 1;
  2864. for_each_sg(bsg_job->request_payload.sg_list, sg,
  2865. tot_dsds, index) {
  2866. dma_addr_t sle_dma;
  2867. /* Allocate additional continuation packets? */
  2868. if (avail_dsds == 0) {
  2869. /*
  2870. * Five DSDs are available in the Cont.
  2871. * Type 1 IOCB.
  2872. */
  2873. memset(&lcont_pkt, 0,
  2874. REQUEST_ENTRY_SIZE);
  2875. cont_pkt =
  2876. qlafx00_prep_cont_type1_iocb(
  2877. sp->fcport->vha->req,
  2878. &lcont_pkt);
  2879. cur_dsd = (__le32 *)
  2880. lcont_pkt.dseg_0_address;
  2881. avail_dsds = 5;
  2882. cont = 1;
  2883. entry_cnt++;
  2884. }
  2885. sle_dma = sg_dma_address(sg);
  2886. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2887. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2888. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2889. avail_dsds--;
  2890. if (avail_dsds == 0 && cont == 1) {
  2891. cont = 0;
  2892. memcpy_toio(
  2893. (void __iomem *)cont_pkt,
  2894. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2895. ql_dump_buffer(
  2896. ql_dbg_user + ql_dbg_verbose,
  2897. sp->fcport->vha, 0x3042,
  2898. (uint8_t *)&lcont_pkt,
  2899. REQUEST_ENTRY_SIZE);
  2900. }
  2901. }
  2902. if (avail_dsds != 0 && cont == 1) {
  2903. memcpy_toio((void __iomem *)cont_pkt,
  2904. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2905. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2906. sp->fcport->vha, 0x3043,
  2907. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2908. }
  2909. }
  2910. if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
  2911. int avail_dsds, tot_dsds;
  2912. cont_a64_entry_t lcont_pkt;
  2913. cont_a64_entry_t *cont_pkt = NULL;
  2914. __le32 *cur_dsd;
  2915. int index = 0, cont = 0;
  2916. fx_iocb.rsp_dsdcnt =
  2917. cpu_to_le16(bsg_job->reply_payload.sg_cnt);
  2918. tot_dsds = bsg_job->reply_payload.sg_cnt;
  2919. cur_dsd = (__le32 *)&fx_iocb.dseg_rsp_address[0];
  2920. avail_dsds = 1;
  2921. for_each_sg(bsg_job->reply_payload.sg_list, sg,
  2922. tot_dsds, index) {
  2923. dma_addr_t sle_dma;
  2924. /* Allocate additional continuation packets? */
  2925. if (avail_dsds == 0) {
  2926. /*
  2927. * Five DSDs are available in the Cont.
  2928. * Type 1 IOCB.
  2929. */
  2930. memset(&lcont_pkt, 0,
  2931. REQUEST_ENTRY_SIZE);
  2932. cont_pkt =
  2933. qlafx00_prep_cont_type1_iocb(
  2934. sp->fcport->vha->req,
  2935. &lcont_pkt);
  2936. cur_dsd = (__le32 *)
  2937. lcont_pkt.dseg_0_address;
  2938. avail_dsds = 5;
  2939. cont = 1;
  2940. entry_cnt++;
  2941. }
  2942. sle_dma = sg_dma_address(sg);
  2943. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2944. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2945. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2946. avail_dsds--;
  2947. if (avail_dsds == 0 && cont == 1) {
  2948. cont = 0;
  2949. memcpy_toio((void __iomem *)cont_pkt,
  2950. &lcont_pkt,
  2951. REQUEST_ENTRY_SIZE);
  2952. ql_dump_buffer(
  2953. ql_dbg_user + ql_dbg_verbose,
  2954. sp->fcport->vha, 0x3045,
  2955. (uint8_t *)&lcont_pkt,
  2956. REQUEST_ENTRY_SIZE);
  2957. }
  2958. }
  2959. if (avail_dsds != 0 && cont == 1) {
  2960. memcpy_toio((void __iomem *)cont_pkt,
  2961. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2962. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2963. sp->fcport->vha, 0x3046,
  2964. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2965. }
  2966. }
  2967. if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
  2968. fx_iocb.dataword = piocb_rqst->dataword;
  2969. fx_iocb.flags = piocb_rqst->flags;
  2970. fx_iocb.entry_count = entry_cnt;
  2971. }
  2972. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2973. sp->fcport->vha, 0x3047,
  2974. (uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
  2975. memcpy_toio((void __iomem *)pfxiocb, &fx_iocb,
  2976. sizeof(struct fxdisc_entry_fx00));
  2977. wmb();
  2978. }