mpt3sas_base.c 159 KB

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  1. /*
  2. * This is the Fusion MPT base driver providing common API layer interface
  3. * for access to MPT (Message Passing Technology) firmware.
  4. *
  5. * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
  6. * Copyright (C) 2012-2014 LSI Corporation
  7. * Copyright (C) 2013-2014 Avago Technologies
  8. * (mailto: MPT-FusionLinux.pdl@avagotech.com)
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License
  12. * as published by the Free Software Foundation; either version 2
  13. * of the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * NO WARRANTY
  21. * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  22. * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  23. * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  24. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  25. * solely responsible for determining the appropriateness of using and
  26. * distributing the Program and assumes all risks associated with its
  27. * exercise of rights under this Agreement, including but not limited to
  28. * the risks and costs of program errors, damage to or loss of data,
  29. * programs or equipment, and unavailability or interruption of operations.
  30. * DISCLAIMER OF LIABILITY
  31. * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  32. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  34. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  35. * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  36. * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  37. * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  38. * You should have received a copy of the GNU General Public License
  39. * along with this program; if not, write to the Free Software
  40. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
  41. * USA.
  42. */
  43. #include <linux/kernel.h>
  44. #include <linux/module.h>
  45. #include <linux/errno.h>
  46. #include <linux/init.h>
  47. #include <linux/slab.h>
  48. #include <linux/types.h>
  49. #include <linux/pci.h>
  50. #include <linux/kdev_t.h>
  51. #include <linux/blkdev.h>
  52. #include <linux/delay.h>
  53. #include <linux/interrupt.h>
  54. #include <linux/dma-mapping.h>
  55. #include <linux/io.h>
  56. #include <linux/time.h>
  57. #include <linux/ktime.h>
  58. #include <linux/kthread.h>
  59. #include <linux/aer.h>
  60. #include "mpt3sas_base.h"
  61. static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
  62. #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
  63. /* maximum controller queue depth */
  64. #define MAX_HBA_QUEUE_DEPTH 30000
  65. #define MAX_CHAIN_DEPTH 100000
  66. static int max_queue_depth = -1;
  67. module_param(max_queue_depth, int, 0);
  68. MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
  69. static int max_sgl_entries = -1;
  70. module_param(max_sgl_entries, int, 0);
  71. MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
  72. static int msix_disable = -1;
  73. module_param(msix_disable, int, 0);
  74. MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
  75. static int smp_affinity_enable = 1;
  76. module_param(smp_affinity_enable, int, S_IRUGO);
  77. MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disbale Default: enable(1)");
  78. static int max_msix_vectors = -1;
  79. module_param(max_msix_vectors, int, 0);
  80. MODULE_PARM_DESC(max_msix_vectors,
  81. " max msix vectors");
  82. static int mpt3sas_fwfault_debug;
  83. MODULE_PARM_DESC(mpt3sas_fwfault_debug,
  84. " enable detection of firmware fault and halt firmware - (default=0)");
  85. static int
  86. _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
  87. /**
  88. * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
  89. *
  90. */
  91. static int
  92. _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
  93. {
  94. int ret = param_set_int(val, kp);
  95. struct MPT3SAS_ADAPTER *ioc;
  96. if (ret)
  97. return ret;
  98. /* global ioc spinlock to protect controller list on list operations */
  99. pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
  100. spin_lock(&gioc_lock);
  101. list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
  102. ioc->fwfault_debug = mpt3sas_fwfault_debug;
  103. spin_unlock(&gioc_lock);
  104. return 0;
  105. }
  106. module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
  107. param_get_int, &mpt3sas_fwfault_debug, 0644);
  108. /**
  109. * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
  110. * @arg: input argument, used to derive ioc
  111. *
  112. * Return 0 if controller is removed from pci subsystem.
  113. * Return -1 for other case.
  114. */
  115. static int mpt3sas_remove_dead_ioc_func(void *arg)
  116. {
  117. struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
  118. struct pci_dev *pdev;
  119. if ((ioc == NULL))
  120. return -1;
  121. pdev = ioc->pdev;
  122. if ((pdev == NULL))
  123. return -1;
  124. pci_stop_and_remove_bus_device_locked(pdev);
  125. return 0;
  126. }
  127. /**
  128. * _base_fault_reset_work - workq handling ioc fault conditions
  129. * @work: input argument, used to derive ioc
  130. * Context: sleep.
  131. *
  132. * Return nothing.
  133. */
  134. static void
  135. _base_fault_reset_work(struct work_struct *work)
  136. {
  137. struct MPT3SAS_ADAPTER *ioc =
  138. container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
  139. unsigned long flags;
  140. u32 doorbell;
  141. int rc;
  142. struct task_struct *p;
  143. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  144. if (ioc->shost_recovery || ioc->pci_error_recovery)
  145. goto rearm_timer;
  146. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  147. doorbell = mpt3sas_base_get_iocstate(ioc, 0);
  148. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
  149. pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
  150. ioc->name);
  151. /* It may be possible that EEH recovery can resolve some of
  152. * pci bus failure issues rather removing the dead ioc function
  153. * by considering controller is in a non-operational state. So
  154. * here priority is given to the EEH recovery. If it doesn't
  155. * not resolve this issue, mpt3sas driver will consider this
  156. * controller to non-operational state and remove the dead ioc
  157. * function.
  158. */
  159. if (ioc->non_operational_loop++ < 5) {
  160. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
  161. flags);
  162. goto rearm_timer;
  163. }
  164. /*
  165. * Call _scsih_flush_pending_cmds callback so that we flush all
  166. * pending commands back to OS. This call is required to aovid
  167. * deadlock at block layer. Dead IOC will fail to do diag reset,
  168. * and this call is safe since dead ioc will never return any
  169. * command back from HW.
  170. */
  171. ioc->schedule_dead_ioc_flush_running_cmds(ioc);
  172. /*
  173. * Set remove_host flag early since kernel thread will
  174. * take some time to execute.
  175. */
  176. ioc->remove_host = 1;
  177. /*Remove the Dead Host */
  178. p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
  179. "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
  180. if (IS_ERR(p))
  181. pr_err(MPT3SAS_FMT
  182. "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
  183. ioc->name, __func__);
  184. else
  185. pr_err(MPT3SAS_FMT
  186. "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
  187. ioc->name, __func__);
  188. return; /* don't rearm timer */
  189. }
  190. ioc->non_operational_loop = 0;
  191. if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
  192. rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
  193. pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
  194. __func__, (rc == 0) ? "success" : "failed");
  195. doorbell = mpt3sas_base_get_iocstate(ioc, 0);
  196. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  197. mpt3sas_base_fault_info(ioc, doorbell &
  198. MPI2_DOORBELL_DATA_MASK);
  199. if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
  200. MPI2_IOC_STATE_OPERATIONAL)
  201. return; /* don't rearm timer */
  202. }
  203. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  204. rearm_timer:
  205. if (ioc->fault_reset_work_q)
  206. queue_delayed_work(ioc->fault_reset_work_q,
  207. &ioc->fault_reset_work,
  208. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  209. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  210. }
  211. /**
  212. * mpt3sas_base_start_watchdog - start the fault_reset_work_q
  213. * @ioc: per adapter object
  214. * Context: sleep.
  215. *
  216. * Return nothing.
  217. */
  218. void
  219. mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
  220. {
  221. unsigned long flags;
  222. if (ioc->fault_reset_work_q)
  223. return;
  224. /* initialize fault polling */
  225. INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
  226. snprintf(ioc->fault_reset_work_q_name,
  227. sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
  228. ioc->driver_name, ioc->id);
  229. ioc->fault_reset_work_q =
  230. create_singlethread_workqueue(ioc->fault_reset_work_q_name);
  231. if (!ioc->fault_reset_work_q) {
  232. pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
  233. ioc->name, __func__, __LINE__);
  234. return;
  235. }
  236. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  237. if (ioc->fault_reset_work_q)
  238. queue_delayed_work(ioc->fault_reset_work_q,
  239. &ioc->fault_reset_work,
  240. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  241. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  242. }
  243. /**
  244. * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
  245. * @ioc: per adapter object
  246. * Context: sleep.
  247. *
  248. * Return nothing.
  249. */
  250. void
  251. mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
  252. {
  253. unsigned long flags;
  254. struct workqueue_struct *wq;
  255. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  256. wq = ioc->fault_reset_work_q;
  257. ioc->fault_reset_work_q = NULL;
  258. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  259. if (wq) {
  260. if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
  261. flush_workqueue(wq);
  262. destroy_workqueue(wq);
  263. }
  264. }
  265. /**
  266. * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
  267. * @ioc: per adapter object
  268. * @fault_code: fault code
  269. *
  270. * Return nothing.
  271. */
  272. void
  273. mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
  274. {
  275. pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
  276. ioc->name, fault_code);
  277. }
  278. /**
  279. * mpt3sas_halt_firmware - halt's mpt controller firmware
  280. * @ioc: per adapter object
  281. *
  282. * For debugging timeout related issues. Writing 0xCOFFEE00
  283. * to the doorbell register will halt controller firmware. With
  284. * the purpose to stop both driver and firmware, the enduser can
  285. * obtain a ring buffer from controller UART.
  286. */
  287. void
  288. mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
  289. {
  290. u32 doorbell;
  291. if (!ioc->fwfault_debug)
  292. return;
  293. dump_stack();
  294. doorbell = readl(&ioc->chip->Doorbell);
  295. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  296. mpt3sas_base_fault_info(ioc , doorbell);
  297. else {
  298. writel(0xC0FFEE00, &ioc->chip->Doorbell);
  299. pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
  300. ioc->name);
  301. }
  302. if (ioc->fwfault_debug == 2)
  303. for (;;)
  304. ;
  305. else
  306. panic("panic in %s\n", __func__);
  307. }
  308. /**
  309. * _base_sas_ioc_info - verbose translation of the ioc status
  310. * @ioc: per adapter object
  311. * @mpi_reply: reply mf payload returned from firmware
  312. * @request_hdr: request mf
  313. *
  314. * Return nothing.
  315. */
  316. static void
  317. _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
  318. MPI2RequestHeader_t *request_hdr)
  319. {
  320. u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
  321. MPI2_IOCSTATUS_MASK;
  322. char *desc = NULL;
  323. u16 frame_sz;
  324. char *func_str = NULL;
  325. /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
  326. if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
  327. request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
  328. request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
  329. return;
  330. if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
  331. return;
  332. switch (ioc_status) {
  333. /****************************************************************************
  334. * Common IOCStatus values for all replies
  335. ****************************************************************************/
  336. case MPI2_IOCSTATUS_INVALID_FUNCTION:
  337. desc = "invalid function";
  338. break;
  339. case MPI2_IOCSTATUS_BUSY:
  340. desc = "busy";
  341. break;
  342. case MPI2_IOCSTATUS_INVALID_SGL:
  343. desc = "invalid sgl";
  344. break;
  345. case MPI2_IOCSTATUS_INTERNAL_ERROR:
  346. desc = "internal error";
  347. break;
  348. case MPI2_IOCSTATUS_INVALID_VPID:
  349. desc = "invalid vpid";
  350. break;
  351. case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
  352. desc = "insufficient resources";
  353. break;
  354. case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
  355. desc = "insufficient power";
  356. break;
  357. case MPI2_IOCSTATUS_INVALID_FIELD:
  358. desc = "invalid field";
  359. break;
  360. case MPI2_IOCSTATUS_INVALID_STATE:
  361. desc = "invalid state";
  362. break;
  363. case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
  364. desc = "op state not supported";
  365. break;
  366. /****************************************************************************
  367. * Config IOCStatus values
  368. ****************************************************************************/
  369. case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
  370. desc = "config invalid action";
  371. break;
  372. case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
  373. desc = "config invalid type";
  374. break;
  375. case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
  376. desc = "config invalid page";
  377. break;
  378. case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
  379. desc = "config invalid data";
  380. break;
  381. case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
  382. desc = "config no defaults";
  383. break;
  384. case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
  385. desc = "config cant commit";
  386. break;
  387. /****************************************************************************
  388. * SCSI IO Reply
  389. ****************************************************************************/
  390. case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
  391. case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
  392. case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
  393. case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
  394. case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
  395. case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
  396. case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
  397. case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
  398. case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
  399. case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
  400. case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
  401. case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
  402. break;
  403. /****************************************************************************
  404. * For use by SCSI Initiator and SCSI Target end-to-end data protection
  405. ****************************************************************************/
  406. case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
  407. desc = "eedp guard error";
  408. break;
  409. case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
  410. desc = "eedp ref tag error";
  411. break;
  412. case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
  413. desc = "eedp app tag error";
  414. break;
  415. /****************************************************************************
  416. * SCSI Target values
  417. ****************************************************************************/
  418. case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
  419. desc = "target invalid io index";
  420. break;
  421. case MPI2_IOCSTATUS_TARGET_ABORTED:
  422. desc = "target aborted";
  423. break;
  424. case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
  425. desc = "target no conn retryable";
  426. break;
  427. case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
  428. desc = "target no connection";
  429. break;
  430. case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
  431. desc = "target xfer count mismatch";
  432. break;
  433. case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
  434. desc = "target data offset error";
  435. break;
  436. case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
  437. desc = "target too much write data";
  438. break;
  439. case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
  440. desc = "target iu too short";
  441. break;
  442. case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
  443. desc = "target ack nak timeout";
  444. break;
  445. case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
  446. desc = "target nak received";
  447. break;
  448. /****************************************************************************
  449. * Serial Attached SCSI values
  450. ****************************************************************************/
  451. case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
  452. desc = "smp request failed";
  453. break;
  454. case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
  455. desc = "smp data overrun";
  456. break;
  457. /****************************************************************************
  458. * Diagnostic Buffer Post / Diagnostic Release values
  459. ****************************************************************************/
  460. case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
  461. desc = "diagnostic released";
  462. break;
  463. default:
  464. break;
  465. }
  466. if (!desc)
  467. return;
  468. switch (request_hdr->Function) {
  469. case MPI2_FUNCTION_CONFIG:
  470. frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
  471. func_str = "config_page";
  472. break;
  473. case MPI2_FUNCTION_SCSI_TASK_MGMT:
  474. frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
  475. func_str = "task_mgmt";
  476. break;
  477. case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
  478. frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
  479. func_str = "sas_iounit_ctl";
  480. break;
  481. case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
  482. frame_sz = sizeof(Mpi2SepRequest_t);
  483. func_str = "enclosure";
  484. break;
  485. case MPI2_FUNCTION_IOC_INIT:
  486. frame_sz = sizeof(Mpi2IOCInitRequest_t);
  487. func_str = "ioc_init";
  488. break;
  489. case MPI2_FUNCTION_PORT_ENABLE:
  490. frame_sz = sizeof(Mpi2PortEnableRequest_t);
  491. func_str = "port_enable";
  492. break;
  493. case MPI2_FUNCTION_SMP_PASSTHROUGH:
  494. frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
  495. func_str = "smp_passthru";
  496. break;
  497. default:
  498. frame_sz = 32;
  499. func_str = "unknown";
  500. break;
  501. }
  502. pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
  503. ioc->name, desc, ioc_status, request_hdr, func_str);
  504. _debug_dump_mf(request_hdr, frame_sz/4);
  505. }
  506. /**
  507. * _base_display_event_data - verbose translation of firmware asyn events
  508. * @ioc: per adapter object
  509. * @mpi_reply: reply mf payload returned from firmware
  510. *
  511. * Return nothing.
  512. */
  513. static void
  514. _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
  515. Mpi2EventNotificationReply_t *mpi_reply)
  516. {
  517. char *desc = NULL;
  518. u16 event;
  519. if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
  520. return;
  521. event = le16_to_cpu(mpi_reply->Event);
  522. switch (event) {
  523. case MPI2_EVENT_LOG_DATA:
  524. desc = "Log Data";
  525. break;
  526. case MPI2_EVENT_STATE_CHANGE:
  527. desc = "Status Change";
  528. break;
  529. case MPI2_EVENT_HARD_RESET_RECEIVED:
  530. desc = "Hard Reset Received";
  531. break;
  532. case MPI2_EVENT_EVENT_CHANGE:
  533. desc = "Event Change";
  534. break;
  535. case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
  536. desc = "Device Status Change";
  537. break;
  538. case MPI2_EVENT_IR_OPERATION_STATUS:
  539. if (!ioc->hide_ir_msg)
  540. desc = "IR Operation Status";
  541. break;
  542. case MPI2_EVENT_SAS_DISCOVERY:
  543. {
  544. Mpi2EventDataSasDiscovery_t *event_data =
  545. (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
  546. pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
  547. (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
  548. "start" : "stop");
  549. if (event_data->DiscoveryStatus)
  550. pr_info("discovery_status(0x%08x)",
  551. le32_to_cpu(event_data->DiscoveryStatus));
  552. pr_info("\n");
  553. return;
  554. }
  555. case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
  556. desc = "SAS Broadcast Primitive";
  557. break;
  558. case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
  559. desc = "SAS Init Device Status Change";
  560. break;
  561. case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
  562. desc = "SAS Init Table Overflow";
  563. break;
  564. case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
  565. desc = "SAS Topology Change List";
  566. break;
  567. case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
  568. desc = "SAS Enclosure Device Status Change";
  569. break;
  570. case MPI2_EVENT_IR_VOLUME:
  571. if (!ioc->hide_ir_msg)
  572. desc = "IR Volume";
  573. break;
  574. case MPI2_EVENT_IR_PHYSICAL_DISK:
  575. if (!ioc->hide_ir_msg)
  576. desc = "IR Physical Disk";
  577. break;
  578. case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
  579. if (!ioc->hide_ir_msg)
  580. desc = "IR Configuration Change List";
  581. break;
  582. case MPI2_EVENT_LOG_ENTRY_ADDED:
  583. if (!ioc->hide_ir_msg)
  584. desc = "Log Entry Added";
  585. break;
  586. case MPI2_EVENT_TEMP_THRESHOLD:
  587. desc = "Temperature Threshold";
  588. break;
  589. case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
  590. desc = "Active cable exception";
  591. break;
  592. }
  593. if (!desc)
  594. return;
  595. pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
  596. }
  597. /**
  598. * _base_sas_log_info - verbose translation of firmware log info
  599. * @ioc: per adapter object
  600. * @log_info: log info
  601. *
  602. * Return nothing.
  603. */
  604. static void
  605. _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
  606. {
  607. union loginfo_type {
  608. u32 loginfo;
  609. struct {
  610. u32 subcode:16;
  611. u32 code:8;
  612. u32 originator:4;
  613. u32 bus_type:4;
  614. } dw;
  615. };
  616. union loginfo_type sas_loginfo;
  617. char *originator_str = NULL;
  618. sas_loginfo.loginfo = log_info;
  619. if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
  620. return;
  621. /* each nexus loss loginfo */
  622. if (log_info == 0x31170000)
  623. return;
  624. /* eat the loginfos associated with task aborts */
  625. if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
  626. 0x31140000 || log_info == 0x31130000))
  627. return;
  628. switch (sas_loginfo.dw.originator) {
  629. case 0:
  630. originator_str = "IOP";
  631. break;
  632. case 1:
  633. originator_str = "PL";
  634. break;
  635. case 2:
  636. if (!ioc->hide_ir_msg)
  637. originator_str = "IR";
  638. else
  639. originator_str = "WarpDrive";
  640. break;
  641. }
  642. pr_warn(MPT3SAS_FMT
  643. "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
  644. ioc->name, log_info,
  645. originator_str, sas_loginfo.dw.code,
  646. sas_loginfo.dw.subcode);
  647. }
  648. /**
  649. * _base_display_reply_info -
  650. * @ioc: per adapter object
  651. * @smid: system request message index
  652. * @msix_index: MSIX table index supplied by the OS
  653. * @reply: reply message frame(lower 32bit addr)
  654. *
  655. * Return nothing.
  656. */
  657. static void
  658. _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  659. u32 reply)
  660. {
  661. MPI2DefaultReply_t *mpi_reply;
  662. u16 ioc_status;
  663. u32 loginfo = 0;
  664. mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
  665. if (unlikely(!mpi_reply)) {
  666. pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
  667. ioc->name, __FILE__, __LINE__, __func__);
  668. return;
  669. }
  670. ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
  671. if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
  672. (ioc->logging_level & MPT_DEBUG_REPLY)) {
  673. _base_sas_ioc_info(ioc , mpi_reply,
  674. mpt3sas_base_get_msg_frame(ioc, smid));
  675. }
  676. if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
  677. loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
  678. _base_sas_log_info(ioc, loginfo);
  679. }
  680. if (ioc_status || loginfo) {
  681. ioc_status &= MPI2_IOCSTATUS_MASK;
  682. mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
  683. }
  684. }
  685. /**
  686. * mpt3sas_base_done - base internal command completion routine
  687. * @ioc: per adapter object
  688. * @smid: system request message index
  689. * @msix_index: MSIX table index supplied by the OS
  690. * @reply: reply message frame(lower 32bit addr)
  691. *
  692. * Return 1 meaning mf should be freed from _base_interrupt
  693. * 0 means the mf is freed from this function.
  694. */
  695. u8
  696. mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  697. u32 reply)
  698. {
  699. MPI2DefaultReply_t *mpi_reply;
  700. mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
  701. if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
  702. return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
  703. if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
  704. return 1;
  705. ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
  706. if (mpi_reply) {
  707. ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
  708. memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
  709. }
  710. ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
  711. complete(&ioc->base_cmds.done);
  712. return 1;
  713. }
  714. /**
  715. * _base_async_event - main callback handler for firmware asyn events
  716. * @ioc: per adapter object
  717. * @msix_index: MSIX table index supplied by the OS
  718. * @reply: reply message frame(lower 32bit addr)
  719. *
  720. * Return 1 meaning mf should be freed from _base_interrupt
  721. * 0 means the mf is freed from this function.
  722. */
  723. static u8
  724. _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
  725. {
  726. Mpi2EventNotificationReply_t *mpi_reply;
  727. Mpi2EventAckRequest_t *ack_request;
  728. u16 smid;
  729. struct _event_ack_list *delayed_event_ack;
  730. mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
  731. if (!mpi_reply)
  732. return 1;
  733. if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
  734. return 1;
  735. _base_display_event_data(ioc, mpi_reply);
  736. if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
  737. goto out;
  738. smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
  739. if (!smid) {
  740. delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
  741. GFP_ATOMIC);
  742. if (!delayed_event_ack)
  743. goto out;
  744. INIT_LIST_HEAD(&delayed_event_ack->list);
  745. delayed_event_ack->Event = mpi_reply->Event;
  746. delayed_event_ack->EventContext = mpi_reply->EventContext;
  747. list_add_tail(&delayed_event_ack->list,
  748. &ioc->delayed_event_ack_list);
  749. dewtprintk(ioc, pr_info(MPT3SAS_FMT
  750. "DELAYED: EVENT ACK: event (0x%04x)\n",
  751. ioc->name, le16_to_cpu(mpi_reply->Event)));
  752. goto out;
  753. }
  754. ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
  755. memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
  756. ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
  757. ack_request->Event = mpi_reply->Event;
  758. ack_request->EventContext = mpi_reply->EventContext;
  759. ack_request->VF_ID = 0; /* TODO */
  760. ack_request->VP_ID = 0;
  761. mpt3sas_base_put_smid_default(ioc, smid);
  762. out:
  763. /* scsih callback handler */
  764. mpt3sas_scsih_event_callback(ioc, msix_index, reply);
  765. /* ctl callback handler */
  766. mpt3sas_ctl_event_callback(ioc, msix_index, reply);
  767. return 1;
  768. }
  769. /**
  770. * _base_get_cb_idx - obtain the callback index
  771. * @ioc: per adapter object
  772. * @smid: system request message index
  773. *
  774. * Return callback index.
  775. */
  776. static u8
  777. _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  778. {
  779. int i;
  780. u8 cb_idx;
  781. if (smid < ioc->hi_priority_smid) {
  782. i = smid - 1;
  783. cb_idx = ioc->scsi_lookup[i].cb_idx;
  784. } else if (smid < ioc->internal_smid) {
  785. i = smid - ioc->hi_priority_smid;
  786. cb_idx = ioc->hpr_lookup[i].cb_idx;
  787. } else if (smid <= ioc->hba_queue_depth) {
  788. i = smid - ioc->internal_smid;
  789. cb_idx = ioc->internal_lookup[i].cb_idx;
  790. } else
  791. cb_idx = 0xFF;
  792. return cb_idx;
  793. }
  794. /**
  795. * _base_mask_interrupts - disable interrupts
  796. * @ioc: per adapter object
  797. *
  798. * Disabling ResetIRQ, Reply and Doorbell Interrupts
  799. *
  800. * Return nothing.
  801. */
  802. static void
  803. _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
  804. {
  805. u32 him_register;
  806. ioc->mask_interrupts = 1;
  807. him_register = readl(&ioc->chip->HostInterruptMask);
  808. him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
  809. writel(him_register, &ioc->chip->HostInterruptMask);
  810. readl(&ioc->chip->HostInterruptMask);
  811. }
  812. /**
  813. * _base_unmask_interrupts - enable interrupts
  814. * @ioc: per adapter object
  815. *
  816. * Enabling only Reply Interrupts
  817. *
  818. * Return nothing.
  819. */
  820. static void
  821. _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
  822. {
  823. u32 him_register;
  824. him_register = readl(&ioc->chip->HostInterruptMask);
  825. him_register &= ~MPI2_HIM_RIM;
  826. writel(him_register, &ioc->chip->HostInterruptMask);
  827. ioc->mask_interrupts = 0;
  828. }
  829. union reply_descriptor {
  830. u64 word;
  831. struct {
  832. u32 low;
  833. u32 high;
  834. } u;
  835. };
  836. /**
  837. * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
  838. * @irq: irq number (not used)
  839. * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
  840. * @r: pt_regs pointer (not used)
  841. *
  842. * Return IRQ_HANDLE if processed, else IRQ_NONE.
  843. */
  844. static irqreturn_t
  845. _base_interrupt(int irq, void *bus_id)
  846. {
  847. struct adapter_reply_queue *reply_q = bus_id;
  848. union reply_descriptor rd;
  849. u32 completed_cmds;
  850. u8 request_desript_type;
  851. u16 smid;
  852. u8 cb_idx;
  853. u32 reply;
  854. u8 msix_index = reply_q->msix_index;
  855. struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
  856. Mpi2ReplyDescriptorsUnion_t *rpf;
  857. u8 rc;
  858. if (ioc->mask_interrupts)
  859. return IRQ_NONE;
  860. if (!atomic_add_unless(&reply_q->busy, 1, 1))
  861. return IRQ_NONE;
  862. rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
  863. request_desript_type = rpf->Default.ReplyFlags
  864. & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  865. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
  866. atomic_dec(&reply_q->busy);
  867. return IRQ_NONE;
  868. }
  869. completed_cmds = 0;
  870. cb_idx = 0xFF;
  871. do {
  872. rd.word = le64_to_cpu(rpf->Words);
  873. if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
  874. goto out;
  875. reply = 0;
  876. smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
  877. if (request_desript_type ==
  878. MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
  879. request_desript_type ==
  880. MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
  881. cb_idx = _base_get_cb_idx(ioc, smid);
  882. if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
  883. (likely(mpt_callbacks[cb_idx] != NULL))) {
  884. rc = mpt_callbacks[cb_idx](ioc, smid,
  885. msix_index, 0);
  886. if (rc)
  887. mpt3sas_base_free_smid(ioc, smid);
  888. }
  889. } else if (request_desript_type ==
  890. MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
  891. reply = le32_to_cpu(
  892. rpf->AddressReply.ReplyFrameAddress);
  893. if (reply > ioc->reply_dma_max_address ||
  894. reply < ioc->reply_dma_min_address)
  895. reply = 0;
  896. if (smid) {
  897. cb_idx = _base_get_cb_idx(ioc, smid);
  898. if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
  899. (likely(mpt_callbacks[cb_idx] != NULL))) {
  900. rc = mpt_callbacks[cb_idx](ioc, smid,
  901. msix_index, reply);
  902. if (reply)
  903. _base_display_reply_info(ioc,
  904. smid, msix_index, reply);
  905. if (rc)
  906. mpt3sas_base_free_smid(ioc,
  907. smid);
  908. }
  909. } else {
  910. _base_async_event(ioc, msix_index, reply);
  911. }
  912. /* reply free queue handling */
  913. if (reply) {
  914. ioc->reply_free_host_index =
  915. (ioc->reply_free_host_index ==
  916. (ioc->reply_free_queue_depth - 1)) ?
  917. 0 : ioc->reply_free_host_index + 1;
  918. ioc->reply_free[ioc->reply_free_host_index] =
  919. cpu_to_le32(reply);
  920. wmb();
  921. writel(ioc->reply_free_host_index,
  922. &ioc->chip->ReplyFreeHostIndex);
  923. }
  924. }
  925. rpf->Words = cpu_to_le64(ULLONG_MAX);
  926. reply_q->reply_post_host_index =
  927. (reply_q->reply_post_host_index ==
  928. (ioc->reply_post_queue_depth - 1)) ? 0 :
  929. reply_q->reply_post_host_index + 1;
  930. request_desript_type =
  931. reply_q->reply_post_free[reply_q->reply_post_host_index].
  932. Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  933. completed_cmds++;
  934. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
  935. goto out;
  936. if (!reply_q->reply_post_host_index)
  937. rpf = reply_q->reply_post_free;
  938. else
  939. rpf++;
  940. } while (1);
  941. out:
  942. if (!completed_cmds) {
  943. atomic_dec(&reply_q->busy);
  944. return IRQ_NONE;
  945. }
  946. wmb();
  947. if (ioc->is_warpdrive) {
  948. writel(reply_q->reply_post_host_index,
  949. ioc->reply_post_host_index[msix_index]);
  950. atomic_dec(&reply_q->busy);
  951. return IRQ_HANDLED;
  952. }
  953. /* Update Reply Post Host Index.
  954. * For those HBA's which support combined reply queue feature
  955. * 1. Get the correct Supplemental Reply Post Host Index Register.
  956. * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
  957. * Index Register address bank i.e replyPostRegisterIndex[],
  958. * 2. Then update this register with new reply host index value
  959. * in ReplyPostIndex field and the MSIxIndex field with
  960. * msix_index value reduced to a value between 0 and 7,
  961. * using a modulo 8 operation. Since each Supplemental Reply Post
  962. * Host Index Register supports 8 MSI-X vectors.
  963. *
  964. * For other HBA's just update the Reply Post Host Index register with
  965. * new reply host index value in ReplyPostIndex Field and msix_index
  966. * value in MSIxIndex field.
  967. */
  968. if (ioc->msix96_vector)
  969. writel(reply_q->reply_post_host_index | ((msix_index & 7) <<
  970. MPI2_RPHI_MSIX_INDEX_SHIFT),
  971. ioc->replyPostRegisterIndex[msix_index/8]);
  972. else
  973. writel(reply_q->reply_post_host_index | (msix_index <<
  974. MPI2_RPHI_MSIX_INDEX_SHIFT),
  975. &ioc->chip->ReplyPostHostIndex);
  976. atomic_dec(&reply_q->busy);
  977. return IRQ_HANDLED;
  978. }
  979. /**
  980. * _base_is_controller_msix_enabled - is controller support muli-reply queues
  981. * @ioc: per adapter object
  982. *
  983. */
  984. static inline int
  985. _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
  986. {
  987. return (ioc->facts.IOCCapabilities &
  988. MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
  989. }
  990. /**
  991. * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
  992. * @ioc: per adapter object
  993. * Context: non ISR conext
  994. *
  995. * Called when a Task Management request has completed.
  996. *
  997. * Return nothing.
  998. */
  999. void
  1000. mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc)
  1001. {
  1002. struct adapter_reply_queue *reply_q;
  1003. /* If MSIX capability is turned off
  1004. * then multi-queues are not enabled
  1005. */
  1006. if (!_base_is_controller_msix_enabled(ioc))
  1007. return;
  1008. list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
  1009. if (ioc->shost_recovery || ioc->remove_host ||
  1010. ioc->pci_error_recovery)
  1011. return;
  1012. /* TMs are on msix_index == 0 */
  1013. if (reply_q->msix_index == 0)
  1014. continue;
  1015. synchronize_irq(reply_q->vector);
  1016. }
  1017. }
  1018. /**
  1019. * mpt3sas_base_release_callback_handler - clear interrupt callback handler
  1020. * @cb_idx: callback index
  1021. *
  1022. * Return nothing.
  1023. */
  1024. void
  1025. mpt3sas_base_release_callback_handler(u8 cb_idx)
  1026. {
  1027. mpt_callbacks[cb_idx] = NULL;
  1028. }
  1029. /**
  1030. * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
  1031. * @cb_func: callback function
  1032. *
  1033. * Returns cb_func.
  1034. */
  1035. u8
  1036. mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
  1037. {
  1038. u8 cb_idx;
  1039. for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
  1040. if (mpt_callbacks[cb_idx] == NULL)
  1041. break;
  1042. mpt_callbacks[cb_idx] = cb_func;
  1043. return cb_idx;
  1044. }
  1045. /**
  1046. * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
  1047. *
  1048. * Return nothing.
  1049. */
  1050. void
  1051. mpt3sas_base_initialize_callback_handler(void)
  1052. {
  1053. u8 cb_idx;
  1054. for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
  1055. mpt3sas_base_release_callback_handler(cb_idx);
  1056. }
  1057. /**
  1058. * _base_build_zero_len_sge - build zero length sg entry
  1059. * @ioc: per adapter object
  1060. * @paddr: virtual address for SGE
  1061. *
  1062. * Create a zero length scatter gather entry to insure the IOCs hardware has
  1063. * something to use if the target device goes brain dead and tries
  1064. * to send data even when none is asked for.
  1065. *
  1066. * Return nothing.
  1067. */
  1068. static void
  1069. _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
  1070. {
  1071. u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
  1072. MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
  1073. MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
  1074. MPI2_SGE_FLAGS_SHIFT);
  1075. ioc->base_add_sg_single(paddr, flags_length, -1);
  1076. }
  1077. /**
  1078. * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
  1079. * @paddr: virtual address for SGE
  1080. * @flags_length: SGE flags and data transfer length
  1081. * @dma_addr: Physical address
  1082. *
  1083. * Return nothing.
  1084. */
  1085. static void
  1086. _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  1087. {
  1088. Mpi2SGESimple32_t *sgel = paddr;
  1089. flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
  1090. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  1091. sgel->FlagsLength = cpu_to_le32(flags_length);
  1092. sgel->Address = cpu_to_le32(dma_addr);
  1093. }
  1094. /**
  1095. * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
  1096. * @paddr: virtual address for SGE
  1097. * @flags_length: SGE flags and data transfer length
  1098. * @dma_addr: Physical address
  1099. *
  1100. * Return nothing.
  1101. */
  1102. static void
  1103. _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  1104. {
  1105. Mpi2SGESimple64_t *sgel = paddr;
  1106. flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
  1107. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  1108. sgel->FlagsLength = cpu_to_le32(flags_length);
  1109. sgel->Address = cpu_to_le64(dma_addr);
  1110. }
  1111. /**
  1112. * _base_get_chain_buffer_tracker - obtain chain tracker
  1113. * @ioc: per adapter object
  1114. * @smid: smid associated to an IO request
  1115. *
  1116. * Returns chain tracker(from ioc->free_chain_list)
  1117. */
  1118. static struct chain_tracker *
  1119. _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  1120. {
  1121. struct chain_tracker *chain_req;
  1122. unsigned long flags;
  1123. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1124. if (list_empty(&ioc->free_chain_list)) {
  1125. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1126. dfailprintk(ioc, pr_warn(MPT3SAS_FMT
  1127. "chain buffers not available\n", ioc->name));
  1128. return NULL;
  1129. }
  1130. chain_req = list_entry(ioc->free_chain_list.next,
  1131. struct chain_tracker, tracker_list);
  1132. list_del_init(&chain_req->tracker_list);
  1133. list_add_tail(&chain_req->tracker_list,
  1134. &ioc->scsi_lookup[smid - 1].chain_list);
  1135. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1136. return chain_req;
  1137. }
  1138. /**
  1139. * _base_build_sg - build generic sg
  1140. * @ioc: per adapter object
  1141. * @psge: virtual address for SGE
  1142. * @data_out_dma: physical address for WRITES
  1143. * @data_out_sz: data xfer size for WRITES
  1144. * @data_in_dma: physical address for READS
  1145. * @data_in_sz: data xfer size for READS
  1146. *
  1147. * Return nothing.
  1148. */
  1149. static void
  1150. _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
  1151. dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
  1152. size_t data_in_sz)
  1153. {
  1154. u32 sgl_flags;
  1155. if (!data_out_sz && !data_in_sz) {
  1156. _base_build_zero_len_sge(ioc, psge);
  1157. return;
  1158. }
  1159. if (data_out_sz && data_in_sz) {
  1160. /* WRITE sgel first */
  1161. sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
  1162. MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
  1163. sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
  1164. ioc->base_add_sg_single(psge, sgl_flags |
  1165. data_out_sz, data_out_dma);
  1166. /* incr sgel */
  1167. psge += ioc->sge_size;
  1168. /* READ sgel last */
  1169. sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
  1170. MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
  1171. MPI2_SGE_FLAGS_END_OF_LIST);
  1172. sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
  1173. ioc->base_add_sg_single(psge, sgl_flags |
  1174. data_in_sz, data_in_dma);
  1175. } else if (data_out_sz) /* WRITE */ {
  1176. sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
  1177. MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
  1178. MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
  1179. sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
  1180. ioc->base_add_sg_single(psge, sgl_flags |
  1181. data_out_sz, data_out_dma);
  1182. } else if (data_in_sz) /* READ */ {
  1183. sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
  1184. MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
  1185. MPI2_SGE_FLAGS_END_OF_LIST);
  1186. sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
  1187. ioc->base_add_sg_single(psge, sgl_flags |
  1188. data_in_sz, data_in_dma);
  1189. }
  1190. }
  1191. /* IEEE format sgls */
  1192. /**
  1193. * _base_add_sg_single_ieee - add sg element for IEEE format
  1194. * @paddr: virtual address for SGE
  1195. * @flags: SGE flags
  1196. * @chain_offset: number of 128 byte elements from start of segment
  1197. * @length: data transfer length
  1198. * @dma_addr: Physical address
  1199. *
  1200. * Return nothing.
  1201. */
  1202. static void
  1203. _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
  1204. dma_addr_t dma_addr)
  1205. {
  1206. Mpi25IeeeSgeChain64_t *sgel = paddr;
  1207. sgel->Flags = flags;
  1208. sgel->NextChainOffset = chain_offset;
  1209. sgel->Length = cpu_to_le32(length);
  1210. sgel->Address = cpu_to_le64(dma_addr);
  1211. }
  1212. /**
  1213. * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
  1214. * @ioc: per adapter object
  1215. * @paddr: virtual address for SGE
  1216. *
  1217. * Create a zero length scatter gather entry to insure the IOCs hardware has
  1218. * something to use if the target device goes brain dead and tries
  1219. * to send data even when none is asked for.
  1220. *
  1221. * Return nothing.
  1222. */
  1223. static void
  1224. _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
  1225. {
  1226. u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
  1227. MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
  1228. MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
  1229. _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
  1230. }
  1231. /**
  1232. * _base_build_sg_scmd - main sg creation routine
  1233. * @ioc: per adapter object
  1234. * @scmd: scsi command
  1235. * @smid: system request message index
  1236. * Context: none.
  1237. *
  1238. * The main routine that builds scatter gather table from a given
  1239. * scsi request sent via the .queuecommand main handler.
  1240. *
  1241. * Returns 0 success, anything else error
  1242. */
  1243. static int
  1244. _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
  1245. struct scsi_cmnd *scmd, u16 smid)
  1246. {
  1247. Mpi2SCSIIORequest_t *mpi_request;
  1248. dma_addr_t chain_dma;
  1249. struct scatterlist *sg_scmd;
  1250. void *sg_local, *chain;
  1251. u32 chain_offset;
  1252. u32 chain_length;
  1253. u32 chain_flags;
  1254. int sges_left;
  1255. u32 sges_in_segment;
  1256. u32 sgl_flags;
  1257. u32 sgl_flags_last_element;
  1258. u32 sgl_flags_end_buffer;
  1259. struct chain_tracker *chain_req;
  1260. mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
  1261. /* init scatter gather flags */
  1262. sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
  1263. if (scmd->sc_data_direction == DMA_TO_DEVICE)
  1264. sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
  1265. sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
  1266. << MPI2_SGE_FLAGS_SHIFT;
  1267. sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
  1268. MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
  1269. << MPI2_SGE_FLAGS_SHIFT;
  1270. sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
  1271. sg_scmd = scsi_sglist(scmd);
  1272. sges_left = scsi_dma_map(scmd);
  1273. if (sges_left < 0) {
  1274. sdev_printk(KERN_ERR, scmd->device,
  1275. "pci_map_sg failed: request for %d bytes!\n",
  1276. scsi_bufflen(scmd));
  1277. return -ENOMEM;
  1278. }
  1279. sg_local = &mpi_request->SGL;
  1280. sges_in_segment = ioc->max_sges_in_main_message;
  1281. if (sges_left <= sges_in_segment)
  1282. goto fill_in_last_segment;
  1283. mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
  1284. (sges_in_segment * ioc->sge_size))/4;
  1285. /* fill in main message segment when there is a chain following */
  1286. while (sges_in_segment) {
  1287. if (sges_in_segment == 1)
  1288. ioc->base_add_sg_single(sg_local,
  1289. sgl_flags_last_element | sg_dma_len(sg_scmd),
  1290. sg_dma_address(sg_scmd));
  1291. else
  1292. ioc->base_add_sg_single(sg_local, sgl_flags |
  1293. sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
  1294. sg_scmd = sg_next(sg_scmd);
  1295. sg_local += ioc->sge_size;
  1296. sges_left--;
  1297. sges_in_segment--;
  1298. }
  1299. /* initializing the chain flags and pointers */
  1300. chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
  1301. chain_req = _base_get_chain_buffer_tracker(ioc, smid);
  1302. if (!chain_req)
  1303. return -1;
  1304. chain = chain_req->chain_buffer;
  1305. chain_dma = chain_req->chain_buffer_dma;
  1306. do {
  1307. sges_in_segment = (sges_left <=
  1308. ioc->max_sges_in_chain_message) ? sges_left :
  1309. ioc->max_sges_in_chain_message;
  1310. chain_offset = (sges_left == sges_in_segment) ?
  1311. 0 : (sges_in_segment * ioc->sge_size)/4;
  1312. chain_length = sges_in_segment * ioc->sge_size;
  1313. if (chain_offset) {
  1314. chain_offset = chain_offset <<
  1315. MPI2_SGE_CHAIN_OFFSET_SHIFT;
  1316. chain_length += ioc->sge_size;
  1317. }
  1318. ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
  1319. chain_length, chain_dma);
  1320. sg_local = chain;
  1321. if (!chain_offset)
  1322. goto fill_in_last_segment;
  1323. /* fill in chain segments */
  1324. while (sges_in_segment) {
  1325. if (sges_in_segment == 1)
  1326. ioc->base_add_sg_single(sg_local,
  1327. sgl_flags_last_element |
  1328. sg_dma_len(sg_scmd),
  1329. sg_dma_address(sg_scmd));
  1330. else
  1331. ioc->base_add_sg_single(sg_local, sgl_flags |
  1332. sg_dma_len(sg_scmd),
  1333. sg_dma_address(sg_scmd));
  1334. sg_scmd = sg_next(sg_scmd);
  1335. sg_local += ioc->sge_size;
  1336. sges_left--;
  1337. sges_in_segment--;
  1338. }
  1339. chain_req = _base_get_chain_buffer_tracker(ioc, smid);
  1340. if (!chain_req)
  1341. return -1;
  1342. chain = chain_req->chain_buffer;
  1343. chain_dma = chain_req->chain_buffer_dma;
  1344. } while (1);
  1345. fill_in_last_segment:
  1346. /* fill the last segment */
  1347. while (sges_left) {
  1348. if (sges_left == 1)
  1349. ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
  1350. sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
  1351. else
  1352. ioc->base_add_sg_single(sg_local, sgl_flags |
  1353. sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
  1354. sg_scmd = sg_next(sg_scmd);
  1355. sg_local += ioc->sge_size;
  1356. sges_left--;
  1357. }
  1358. return 0;
  1359. }
  1360. /**
  1361. * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
  1362. * @ioc: per adapter object
  1363. * @scmd: scsi command
  1364. * @smid: system request message index
  1365. * Context: none.
  1366. *
  1367. * The main routine that builds scatter gather table from a given
  1368. * scsi request sent via the .queuecommand main handler.
  1369. *
  1370. * Returns 0 success, anything else error
  1371. */
  1372. static int
  1373. _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
  1374. struct scsi_cmnd *scmd, u16 smid)
  1375. {
  1376. Mpi2SCSIIORequest_t *mpi_request;
  1377. dma_addr_t chain_dma;
  1378. struct scatterlist *sg_scmd;
  1379. void *sg_local, *chain;
  1380. u32 chain_offset;
  1381. u32 chain_length;
  1382. int sges_left;
  1383. u32 sges_in_segment;
  1384. u8 simple_sgl_flags;
  1385. u8 simple_sgl_flags_last;
  1386. u8 chain_sgl_flags;
  1387. struct chain_tracker *chain_req;
  1388. mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
  1389. /* init scatter gather flags */
  1390. simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
  1391. MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
  1392. simple_sgl_flags_last = simple_sgl_flags |
  1393. MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
  1394. chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
  1395. MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
  1396. sg_scmd = scsi_sglist(scmd);
  1397. sges_left = scsi_dma_map(scmd);
  1398. if (sges_left < 0) {
  1399. sdev_printk(KERN_ERR, scmd->device,
  1400. "pci_map_sg failed: request for %d bytes!\n",
  1401. scsi_bufflen(scmd));
  1402. return -ENOMEM;
  1403. }
  1404. sg_local = &mpi_request->SGL;
  1405. sges_in_segment = (ioc->request_sz -
  1406. offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
  1407. if (sges_left <= sges_in_segment)
  1408. goto fill_in_last_segment;
  1409. mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
  1410. (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
  1411. /* fill in main message segment when there is a chain following */
  1412. while (sges_in_segment > 1) {
  1413. _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
  1414. sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
  1415. sg_scmd = sg_next(sg_scmd);
  1416. sg_local += ioc->sge_size_ieee;
  1417. sges_left--;
  1418. sges_in_segment--;
  1419. }
  1420. /* initializing the pointers */
  1421. chain_req = _base_get_chain_buffer_tracker(ioc, smid);
  1422. if (!chain_req)
  1423. return -1;
  1424. chain = chain_req->chain_buffer;
  1425. chain_dma = chain_req->chain_buffer_dma;
  1426. do {
  1427. sges_in_segment = (sges_left <=
  1428. ioc->max_sges_in_chain_message) ? sges_left :
  1429. ioc->max_sges_in_chain_message;
  1430. chain_offset = (sges_left == sges_in_segment) ?
  1431. 0 : sges_in_segment;
  1432. chain_length = sges_in_segment * ioc->sge_size_ieee;
  1433. if (chain_offset)
  1434. chain_length += ioc->sge_size_ieee;
  1435. _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
  1436. chain_offset, chain_length, chain_dma);
  1437. sg_local = chain;
  1438. if (!chain_offset)
  1439. goto fill_in_last_segment;
  1440. /* fill in chain segments */
  1441. while (sges_in_segment) {
  1442. _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
  1443. sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
  1444. sg_scmd = sg_next(sg_scmd);
  1445. sg_local += ioc->sge_size_ieee;
  1446. sges_left--;
  1447. sges_in_segment--;
  1448. }
  1449. chain_req = _base_get_chain_buffer_tracker(ioc, smid);
  1450. if (!chain_req)
  1451. return -1;
  1452. chain = chain_req->chain_buffer;
  1453. chain_dma = chain_req->chain_buffer_dma;
  1454. } while (1);
  1455. fill_in_last_segment:
  1456. /* fill the last segment */
  1457. while (sges_left > 0) {
  1458. if (sges_left == 1)
  1459. _base_add_sg_single_ieee(sg_local,
  1460. simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
  1461. sg_dma_address(sg_scmd));
  1462. else
  1463. _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
  1464. sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
  1465. sg_scmd = sg_next(sg_scmd);
  1466. sg_local += ioc->sge_size_ieee;
  1467. sges_left--;
  1468. }
  1469. return 0;
  1470. }
  1471. /**
  1472. * _base_build_sg_ieee - build generic sg for IEEE format
  1473. * @ioc: per adapter object
  1474. * @psge: virtual address for SGE
  1475. * @data_out_dma: physical address for WRITES
  1476. * @data_out_sz: data xfer size for WRITES
  1477. * @data_in_dma: physical address for READS
  1478. * @data_in_sz: data xfer size for READS
  1479. *
  1480. * Return nothing.
  1481. */
  1482. static void
  1483. _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
  1484. dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
  1485. size_t data_in_sz)
  1486. {
  1487. u8 sgl_flags;
  1488. if (!data_out_sz && !data_in_sz) {
  1489. _base_build_zero_len_sge_ieee(ioc, psge);
  1490. return;
  1491. }
  1492. if (data_out_sz && data_in_sz) {
  1493. /* WRITE sgel first */
  1494. sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
  1495. MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
  1496. _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
  1497. data_out_dma);
  1498. /* incr sgel */
  1499. psge += ioc->sge_size_ieee;
  1500. /* READ sgel last */
  1501. sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
  1502. _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
  1503. data_in_dma);
  1504. } else if (data_out_sz) /* WRITE */ {
  1505. sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
  1506. MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
  1507. MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
  1508. _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
  1509. data_out_dma);
  1510. } else if (data_in_sz) /* READ */ {
  1511. sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
  1512. MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
  1513. MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
  1514. _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
  1515. data_in_dma);
  1516. }
  1517. }
  1518. #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
  1519. /**
  1520. * _base_config_dma_addressing - set dma addressing
  1521. * @ioc: per adapter object
  1522. * @pdev: PCI device struct
  1523. *
  1524. * Returns 0 for success, non-zero for failure.
  1525. */
  1526. static int
  1527. _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
  1528. {
  1529. struct sysinfo s;
  1530. u64 consistent_dma_mask;
  1531. if (ioc->dma_mask)
  1532. consistent_dma_mask = DMA_BIT_MASK(64);
  1533. else
  1534. consistent_dma_mask = DMA_BIT_MASK(32);
  1535. if (sizeof(dma_addr_t) > 4) {
  1536. const uint64_t required_mask =
  1537. dma_get_required_mask(&pdev->dev);
  1538. if ((required_mask > DMA_BIT_MASK(32)) &&
  1539. !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
  1540. !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
  1541. ioc->base_add_sg_single = &_base_add_sg_single_64;
  1542. ioc->sge_size = sizeof(Mpi2SGESimple64_t);
  1543. ioc->dma_mask = 64;
  1544. goto out;
  1545. }
  1546. }
  1547. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
  1548. && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  1549. ioc->base_add_sg_single = &_base_add_sg_single_32;
  1550. ioc->sge_size = sizeof(Mpi2SGESimple32_t);
  1551. ioc->dma_mask = 32;
  1552. } else
  1553. return -ENODEV;
  1554. out:
  1555. si_meminfo(&s);
  1556. pr_info(MPT3SAS_FMT
  1557. "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
  1558. ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
  1559. return 0;
  1560. }
  1561. static int
  1562. _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
  1563. struct pci_dev *pdev)
  1564. {
  1565. if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
  1566. if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
  1567. return -ENODEV;
  1568. }
  1569. return 0;
  1570. }
  1571. /**
  1572. * _base_check_enable_msix - checks MSIX capabable.
  1573. * @ioc: per adapter object
  1574. *
  1575. * Check to see if card is capable of MSIX, and set number
  1576. * of available msix vectors
  1577. */
  1578. static int
  1579. _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
  1580. {
  1581. int base;
  1582. u16 message_control;
  1583. /* Check whether controller SAS2008 B0 controller,
  1584. * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
  1585. */
  1586. if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
  1587. ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
  1588. return -EINVAL;
  1589. }
  1590. base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
  1591. if (!base) {
  1592. dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
  1593. ioc->name));
  1594. return -EINVAL;
  1595. }
  1596. /* get msix vector count */
  1597. /* NUMA_IO not supported for older controllers */
  1598. if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
  1599. ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
  1600. ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
  1601. ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
  1602. ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
  1603. ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
  1604. ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
  1605. ioc->msix_vector_count = 1;
  1606. else {
  1607. pci_read_config_word(ioc->pdev, base + 2, &message_control);
  1608. ioc->msix_vector_count = (message_control & 0x3FF) + 1;
  1609. }
  1610. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  1611. "msix is supported, vector_count(%d)\n",
  1612. ioc->name, ioc->msix_vector_count));
  1613. return 0;
  1614. }
  1615. /**
  1616. * _base_free_irq - free irq
  1617. * @ioc: per adapter object
  1618. *
  1619. * Freeing respective reply_queue from the list.
  1620. */
  1621. static void
  1622. _base_free_irq(struct MPT3SAS_ADAPTER *ioc)
  1623. {
  1624. struct adapter_reply_queue *reply_q, *next;
  1625. if (list_empty(&ioc->reply_queue_list))
  1626. return;
  1627. list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
  1628. list_del(&reply_q->list);
  1629. if (smp_affinity_enable) {
  1630. irq_set_affinity_hint(reply_q->vector, NULL);
  1631. free_cpumask_var(reply_q->affinity_hint);
  1632. }
  1633. free_irq(reply_q->vector, reply_q);
  1634. kfree(reply_q);
  1635. }
  1636. }
  1637. /**
  1638. * _base_request_irq - request irq
  1639. * @ioc: per adapter object
  1640. * @index: msix index into vector table
  1641. * @vector: irq vector
  1642. *
  1643. * Inserting respective reply_queue into the list.
  1644. */
  1645. static int
  1646. _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
  1647. {
  1648. struct adapter_reply_queue *reply_q;
  1649. int r;
  1650. reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
  1651. if (!reply_q) {
  1652. pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
  1653. ioc->name, (int)sizeof(struct adapter_reply_queue));
  1654. return -ENOMEM;
  1655. }
  1656. reply_q->ioc = ioc;
  1657. reply_q->msix_index = index;
  1658. reply_q->vector = vector;
  1659. if (smp_affinity_enable) {
  1660. if (!zalloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL)) {
  1661. kfree(reply_q);
  1662. return -ENOMEM;
  1663. }
  1664. }
  1665. atomic_set(&reply_q->busy, 0);
  1666. if (ioc->msix_enable)
  1667. snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
  1668. ioc->driver_name, ioc->id, index);
  1669. else
  1670. snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
  1671. ioc->driver_name, ioc->id);
  1672. r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
  1673. reply_q);
  1674. if (r) {
  1675. pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
  1676. reply_q->name, vector);
  1677. free_cpumask_var(reply_q->affinity_hint);
  1678. kfree(reply_q);
  1679. return -EBUSY;
  1680. }
  1681. INIT_LIST_HEAD(&reply_q->list);
  1682. list_add_tail(&reply_q->list, &ioc->reply_queue_list);
  1683. return 0;
  1684. }
  1685. /**
  1686. * _base_assign_reply_queues - assigning msix index for each cpu
  1687. * @ioc: per adapter object
  1688. *
  1689. * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
  1690. *
  1691. * It would nice if we could call irq_set_affinity, however it is not
  1692. * an exported symbol
  1693. */
  1694. static void
  1695. _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
  1696. {
  1697. unsigned int cpu, nr_cpus, nr_msix, index = 0;
  1698. struct adapter_reply_queue *reply_q;
  1699. if (!_base_is_controller_msix_enabled(ioc))
  1700. return;
  1701. memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
  1702. nr_cpus = num_online_cpus();
  1703. nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
  1704. ioc->facts.MaxMSIxVectors);
  1705. if (!nr_msix)
  1706. return;
  1707. cpu = cpumask_first(cpu_online_mask);
  1708. list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
  1709. unsigned int i, group = nr_cpus / nr_msix;
  1710. if (cpu >= nr_cpus)
  1711. break;
  1712. if (index < nr_cpus % nr_msix)
  1713. group++;
  1714. for (i = 0 ; i < group ; i++) {
  1715. ioc->cpu_msix_table[cpu] = index;
  1716. if (smp_affinity_enable)
  1717. cpumask_or(reply_q->affinity_hint,
  1718. reply_q->affinity_hint, get_cpu_mask(cpu));
  1719. cpu = cpumask_next(cpu, cpu_online_mask);
  1720. }
  1721. if (smp_affinity_enable)
  1722. if (irq_set_affinity_hint(reply_q->vector,
  1723. reply_q->affinity_hint))
  1724. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  1725. "Err setting affinity hint to irq vector %d\n",
  1726. ioc->name, reply_q->vector));
  1727. index++;
  1728. }
  1729. }
  1730. /**
  1731. * _base_disable_msix - disables msix
  1732. * @ioc: per adapter object
  1733. *
  1734. */
  1735. static void
  1736. _base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
  1737. {
  1738. if (!ioc->msix_enable)
  1739. return;
  1740. pci_disable_msix(ioc->pdev);
  1741. ioc->msix_enable = 0;
  1742. }
  1743. /**
  1744. * _base_enable_msix - enables msix, failback to io_apic
  1745. * @ioc: per adapter object
  1746. *
  1747. */
  1748. static int
  1749. _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
  1750. {
  1751. struct msix_entry *entries, *a;
  1752. int r;
  1753. int i;
  1754. u8 try_msix = 0;
  1755. if (msix_disable == -1 || msix_disable == 0)
  1756. try_msix = 1;
  1757. if (!try_msix)
  1758. goto try_ioapic;
  1759. if (_base_check_enable_msix(ioc) != 0)
  1760. goto try_ioapic;
  1761. ioc->reply_queue_count = min_t(int, ioc->cpu_count,
  1762. ioc->msix_vector_count);
  1763. printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
  1764. ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
  1765. ioc->cpu_count, max_msix_vectors);
  1766. if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
  1767. max_msix_vectors = 8;
  1768. if (max_msix_vectors > 0) {
  1769. ioc->reply_queue_count = min_t(int, max_msix_vectors,
  1770. ioc->reply_queue_count);
  1771. ioc->msix_vector_count = ioc->reply_queue_count;
  1772. } else if (max_msix_vectors == 0)
  1773. goto try_ioapic;
  1774. if (ioc->msix_vector_count < ioc->cpu_count)
  1775. smp_affinity_enable = 0;
  1776. entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
  1777. GFP_KERNEL);
  1778. if (!entries) {
  1779. dfailprintk(ioc, pr_info(MPT3SAS_FMT
  1780. "kcalloc failed @ at %s:%d/%s() !!!\n",
  1781. ioc->name, __FILE__, __LINE__, __func__));
  1782. goto try_ioapic;
  1783. }
  1784. for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
  1785. a->entry = i;
  1786. r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
  1787. if (r) {
  1788. dfailprintk(ioc, pr_info(MPT3SAS_FMT
  1789. "pci_enable_msix_exact failed (r=%d) !!!\n",
  1790. ioc->name, r));
  1791. kfree(entries);
  1792. goto try_ioapic;
  1793. }
  1794. ioc->msix_enable = 1;
  1795. for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
  1796. r = _base_request_irq(ioc, i, a->vector);
  1797. if (r) {
  1798. _base_free_irq(ioc);
  1799. _base_disable_msix(ioc);
  1800. kfree(entries);
  1801. goto try_ioapic;
  1802. }
  1803. }
  1804. kfree(entries);
  1805. return 0;
  1806. /* failback to io_apic interrupt routing */
  1807. try_ioapic:
  1808. ioc->reply_queue_count = 1;
  1809. r = _base_request_irq(ioc, 0, ioc->pdev->irq);
  1810. return r;
  1811. }
  1812. /**
  1813. * mpt3sas_base_unmap_resources - free controller resources
  1814. * @ioc: per adapter object
  1815. */
  1816. static void
  1817. mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
  1818. {
  1819. struct pci_dev *pdev = ioc->pdev;
  1820. dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
  1821. ioc->name, __func__));
  1822. _base_free_irq(ioc);
  1823. _base_disable_msix(ioc);
  1824. if (ioc->msix96_vector) {
  1825. kfree(ioc->replyPostRegisterIndex);
  1826. ioc->replyPostRegisterIndex = NULL;
  1827. }
  1828. if (ioc->chip_phys) {
  1829. iounmap(ioc->chip);
  1830. ioc->chip_phys = 0;
  1831. }
  1832. if (pci_is_enabled(pdev)) {
  1833. pci_release_selected_regions(ioc->pdev, ioc->bars);
  1834. pci_disable_pcie_error_reporting(pdev);
  1835. pci_disable_device(pdev);
  1836. }
  1837. }
  1838. /**
  1839. * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
  1840. * @ioc: per adapter object
  1841. *
  1842. * Returns 0 for success, non-zero for failure.
  1843. */
  1844. int
  1845. mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
  1846. {
  1847. struct pci_dev *pdev = ioc->pdev;
  1848. u32 memap_sz;
  1849. u32 pio_sz;
  1850. int i, r = 0;
  1851. u64 pio_chip = 0;
  1852. u64 chip_phys = 0;
  1853. struct adapter_reply_queue *reply_q;
  1854. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
  1855. ioc->name, __func__));
  1856. ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1857. if (pci_enable_device_mem(pdev)) {
  1858. pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
  1859. ioc->name);
  1860. ioc->bars = 0;
  1861. return -ENODEV;
  1862. }
  1863. if (pci_request_selected_regions(pdev, ioc->bars,
  1864. ioc->driver_name)) {
  1865. pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
  1866. ioc->name);
  1867. ioc->bars = 0;
  1868. r = -ENODEV;
  1869. goto out_fail;
  1870. }
  1871. /* AER (Advanced Error Reporting) hooks */
  1872. pci_enable_pcie_error_reporting(pdev);
  1873. pci_set_master(pdev);
  1874. if (_base_config_dma_addressing(ioc, pdev) != 0) {
  1875. pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
  1876. ioc->name, pci_name(pdev));
  1877. r = -ENODEV;
  1878. goto out_fail;
  1879. }
  1880. for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
  1881. (!memap_sz || !pio_sz); i++) {
  1882. if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
  1883. if (pio_sz)
  1884. continue;
  1885. pio_chip = (u64)pci_resource_start(pdev, i);
  1886. pio_sz = pci_resource_len(pdev, i);
  1887. } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  1888. if (memap_sz)
  1889. continue;
  1890. ioc->chip_phys = pci_resource_start(pdev, i);
  1891. chip_phys = (u64)ioc->chip_phys;
  1892. memap_sz = pci_resource_len(pdev, i);
  1893. ioc->chip = ioremap(ioc->chip_phys, memap_sz);
  1894. }
  1895. }
  1896. if (ioc->chip == NULL) {
  1897. pr_err(MPT3SAS_FMT "unable to map adapter memory! "
  1898. " or resource not found\n", ioc->name);
  1899. r = -EINVAL;
  1900. goto out_fail;
  1901. }
  1902. _base_mask_interrupts(ioc);
  1903. r = _base_get_ioc_facts(ioc);
  1904. if (r)
  1905. goto out_fail;
  1906. if (!ioc->rdpq_array_enable_assigned) {
  1907. ioc->rdpq_array_enable = ioc->rdpq_array_capable;
  1908. ioc->rdpq_array_enable_assigned = 1;
  1909. }
  1910. r = _base_enable_msix(ioc);
  1911. if (r)
  1912. goto out_fail;
  1913. /* Use the Combined reply queue feature only for SAS3 C0 & higher
  1914. * revision HBAs and also only when reply queue count is greater than 8
  1915. */
  1916. if (ioc->msix96_vector && ioc->reply_queue_count > 8) {
  1917. /* Determine the Supplemental Reply Post Host Index Registers
  1918. * Addresse. Supplemental Reply Post Host Index Registers
  1919. * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
  1920. * each register is at offset bytes of
  1921. * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
  1922. */
  1923. ioc->replyPostRegisterIndex = kcalloc(
  1924. MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT,
  1925. sizeof(resource_size_t *), GFP_KERNEL);
  1926. if (!ioc->replyPostRegisterIndex) {
  1927. dfailprintk(ioc, printk(MPT3SAS_FMT
  1928. "allocation for reply Post Register Index failed!!!\n",
  1929. ioc->name));
  1930. r = -ENOMEM;
  1931. goto out_fail;
  1932. }
  1933. for (i = 0; i < MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT; i++) {
  1934. ioc->replyPostRegisterIndex[i] = (resource_size_t *)
  1935. ((u8 *)&ioc->chip->Doorbell +
  1936. MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
  1937. (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
  1938. }
  1939. } else
  1940. ioc->msix96_vector = 0;
  1941. if (ioc->is_warpdrive) {
  1942. ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
  1943. &ioc->chip->ReplyPostHostIndex;
  1944. for (i = 1; i < ioc->cpu_msix_table_sz; i++)
  1945. ioc->reply_post_host_index[i] =
  1946. (resource_size_t __iomem *)
  1947. ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
  1948. * 4)));
  1949. }
  1950. list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
  1951. pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
  1952. reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
  1953. "IO-APIC enabled"), reply_q->vector);
  1954. pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
  1955. ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
  1956. pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
  1957. ioc->name, (unsigned long long)pio_chip, pio_sz);
  1958. /* Save PCI configuration state for recovery from PCI AER/EEH errors */
  1959. pci_save_state(pdev);
  1960. return 0;
  1961. out_fail:
  1962. mpt3sas_base_unmap_resources(ioc);
  1963. return r;
  1964. }
  1965. /**
  1966. * mpt3sas_base_get_msg_frame - obtain request mf pointer
  1967. * @ioc: per adapter object
  1968. * @smid: system request message index(smid zero is invalid)
  1969. *
  1970. * Returns virt pointer to message frame.
  1971. */
  1972. void *
  1973. mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  1974. {
  1975. return (void *)(ioc->request + (smid * ioc->request_sz));
  1976. }
  1977. /**
  1978. * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
  1979. * @ioc: per adapter object
  1980. * @smid: system request message index
  1981. *
  1982. * Returns virt pointer to sense buffer.
  1983. */
  1984. void *
  1985. mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  1986. {
  1987. return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
  1988. }
  1989. /**
  1990. * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
  1991. * @ioc: per adapter object
  1992. * @smid: system request message index
  1993. *
  1994. * Returns phys pointer to the low 32bit address of the sense buffer.
  1995. */
  1996. __le32
  1997. mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  1998. {
  1999. return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
  2000. SCSI_SENSE_BUFFERSIZE));
  2001. }
  2002. /**
  2003. * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
  2004. * @ioc: per adapter object
  2005. * @phys_addr: lower 32 physical addr of the reply
  2006. *
  2007. * Converts 32bit lower physical addr into a virt address.
  2008. */
  2009. void *
  2010. mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
  2011. {
  2012. if (!phys_addr)
  2013. return NULL;
  2014. return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
  2015. }
  2016. static inline u8
  2017. _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
  2018. {
  2019. return ioc->cpu_msix_table[raw_smp_processor_id()];
  2020. }
  2021. /**
  2022. * mpt3sas_base_get_smid - obtain a free smid from internal queue
  2023. * @ioc: per adapter object
  2024. * @cb_idx: callback index
  2025. *
  2026. * Returns smid (zero is invalid)
  2027. */
  2028. u16
  2029. mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
  2030. {
  2031. unsigned long flags;
  2032. struct request_tracker *request;
  2033. u16 smid;
  2034. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  2035. if (list_empty(&ioc->internal_free_list)) {
  2036. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  2037. pr_err(MPT3SAS_FMT "%s: smid not available\n",
  2038. ioc->name, __func__);
  2039. return 0;
  2040. }
  2041. request = list_entry(ioc->internal_free_list.next,
  2042. struct request_tracker, tracker_list);
  2043. request->cb_idx = cb_idx;
  2044. smid = request->smid;
  2045. list_del(&request->tracker_list);
  2046. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  2047. return smid;
  2048. }
  2049. /**
  2050. * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
  2051. * @ioc: per adapter object
  2052. * @cb_idx: callback index
  2053. * @scmd: pointer to scsi command object
  2054. *
  2055. * Returns smid (zero is invalid)
  2056. */
  2057. u16
  2058. mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
  2059. struct scsi_cmnd *scmd)
  2060. {
  2061. unsigned long flags;
  2062. struct scsiio_tracker *request;
  2063. u16 smid;
  2064. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  2065. if (list_empty(&ioc->free_list)) {
  2066. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  2067. pr_err(MPT3SAS_FMT "%s: smid not available\n",
  2068. ioc->name, __func__);
  2069. return 0;
  2070. }
  2071. request = list_entry(ioc->free_list.next,
  2072. struct scsiio_tracker, tracker_list);
  2073. request->scmd = scmd;
  2074. request->cb_idx = cb_idx;
  2075. smid = request->smid;
  2076. request->msix_io = _base_get_msix_index(ioc);
  2077. list_del(&request->tracker_list);
  2078. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  2079. return smid;
  2080. }
  2081. /**
  2082. * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
  2083. * @ioc: per adapter object
  2084. * @cb_idx: callback index
  2085. *
  2086. * Returns smid (zero is invalid)
  2087. */
  2088. u16
  2089. mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
  2090. {
  2091. unsigned long flags;
  2092. struct request_tracker *request;
  2093. u16 smid;
  2094. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  2095. if (list_empty(&ioc->hpr_free_list)) {
  2096. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  2097. return 0;
  2098. }
  2099. request = list_entry(ioc->hpr_free_list.next,
  2100. struct request_tracker, tracker_list);
  2101. request->cb_idx = cb_idx;
  2102. smid = request->smid;
  2103. list_del(&request->tracker_list);
  2104. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  2105. return smid;
  2106. }
  2107. /**
  2108. * mpt3sas_base_free_smid - put smid back on free_list
  2109. * @ioc: per adapter object
  2110. * @smid: system request message index
  2111. *
  2112. * Return nothing.
  2113. */
  2114. void
  2115. mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  2116. {
  2117. unsigned long flags;
  2118. int i;
  2119. struct chain_tracker *chain_req, *next;
  2120. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  2121. if (smid < ioc->hi_priority_smid) {
  2122. /* scsiio queue */
  2123. i = smid - 1;
  2124. if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
  2125. list_for_each_entry_safe(chain_req, next,
  2126. &ioc->scsi_lookup[i].chain_list, tracker_list) {
  2127. list_del_init(&chain_req->tracker_list);
  2128. list_add(&chain_req->tracker_list,
  2129. &ioc->free_chain_list);
  2130. }
  2131. }
  2132. ioc->scsi_lookup[i].cb_idx = 0xFF;
  2133. ioc->scsi_lookup[i].scmd = NULL;
  2134. ioc->scsi_lookup[i].direct_io = 0;
  2135. list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
  2136. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  2137. /*
  2138. * See _wait_for_commands_to_complete() call with regards
  2139. * to this code.
  2140. */
  2141. if (ioc->shost_recovery && ioc->pending_io_count) {
  2142. if (ioc->pending_io_count == 1)
  2143. wake_up(&ioc->reset_wq);
  2144. ioc->pending_io_count--;
  2145. }
  2146. return;
  2147. } else if (smid < ioc->internal_smid) {
  2148. /* hi-priority */
  2149. i = smid - ioc->hi_priority_smid;
  2150. ioc->hpr_lookup[i].cb_idx = 0xFF;
  2151. list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
  2152. } else if (smid <= ioc->hba_queue_depth) {
  2153. /* internal queue */
  2154. i = smid - ioc->internal_smid;
  2155. ioc->internal_lookup[i].cb_idx = 0xFF;
  2156. list_add(&ioc->internal_lookup[i].tracker_list,
  2157. &ioc->internal_free_list);
  2158. }
  2159. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  2160. }
  2161. /**
  2162. * _base_writeq - 64 bit write to MMIO
  2163. * @ioc: per adapter object
  2164. * @b: data payload
  2165. * @addr: address in MMIO space
  2166. * @writeq_lock: spin lock
  2167. *
  2168. * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
  2169. * care of 32 bit environment where its not quarenteed to send the entire word
  2170. * in one transfer.
  2171. */
  2172. #if defined(writeq) && defined(CONFIG_64BIT)
  2173. static inline void
  2174. _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
  2175. {
  2176. writeq(cpu_to_le64(b), addr);
  2177. }
  2178. #else
  2179. static inline void
  2180. _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
  2181. {
  2182. unsigned long flags;
  2183. __u64 data_out = cpu_to_le64(b);
  2184. spin_lock_irqsave(writeq_lock, flags);
  2185. writel((u32)(data_out), addr);
  2186. writel((u32)(data_out >> 32), (addr + 4));
  2187. spin_unlock_irqrestore(writeq_lock, flags);
  2188. }
  2189. #endif
  2190. /**
  2191. * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
  2192. * @ioc: per adapter object
  2193. * @smid: system request message index
  2194. * @handle: device handle
  2195. *
  2196. * Return nothing.
  2197. */
  2198. void
  2199. mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
  2200. {
  2201. Mpi2RequestDescriptorUnion_t descriptor;
  2202. u64 *request = (u64 *)&descriptor;
  2203. descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
  2204. descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
  2205. descriptor.SCSIIO.SMID = cpu_to_le16(smid);
  2206. descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
  2207. descriptor.SCSIIO.LMID = 0;
  2208. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  2209. &ioc->scsi_lookup_lock);
  2210. }
  2211. /**
  2212. * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
  2213. * @ioc: per adapter object
  2214. * @smid: system request message index
  2215. * @handle: device handle
  2216. *
  2217. * Return nothing.
  2218. */
  2219. void
  2220. mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
  2221. u16 handle)
  2222. {
  2223. Mpi2RequestDescriptorUnion_t descriptor;
  2224. u64 *request = (u64 *)&descriptor;
  2225. descriptor.SCSIIO.RequestFlags =
  2226. MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
  2227. descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
  2228. descriptor.SCSIIO.SMID = cpu_to_le16(smid);
  2229. descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
  2230. descriptor.SCSIIO.LMID = 0;
  2231. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  2232. &ioc->scsi_lookup_lock);
  2233. }
  2234. /**
  2235. * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
  2236. * @ioc: per adapter object
  2237. * @smid: system request message index
  2238. * @msix_task: msix_task will be same as msix of IO incase of task abort else 0.
  2239. * Return nothing.
  2240. */
  2241. void
  2242. mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
  2243. u16 msix_task)
  2244. {
  2245. Mpi2RequestDescriptorUnion_t descriptor;
  2246. u64 *request = (u64 *)&descriptor;
  2247. descriptor.HighPriority.RequestFlags =
  2248. MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
  2249. descriptor.HighPriority.MSIxIndex = msix_task;
  2250. descriptor.HighPriority.SMID = cpu_to_le16(smid);
  2251. descriptor.HighPriority.LMID = 0;
  2252. descriptor.HighPriority.Reserved1 = 0;
  2253. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  2254. &ioc->scsi_lookup_lock);
  2255. }
  2256. /**
  2257. * mpt3sas_base_put_smid_default - Default, primarily used for config pages
  2258. * @ioc: per adapter object
  2259. * @smid: system request message index
  2260. *
  2261. * Return nothing.
  2262. */
  2263. void
  2264. mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  2265. {
  2266. Mpi2RequestDescriptorUnion_t descriptor;
  2267. u64 *request = (u64 *)&descriptor;
  2268. descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
  2269. descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
  2270. descriptor.Default.SMID = cpu_to_le16(smid);
  2271. descriptor.Default.LMID = 0;
  2272. descriptor.Default.DescriptorTypeDependent = 0;
  2273. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  2274. &ioc->scsi_lookup_lock);
  2275. }
  2276. /**
  2277. * _base_display_OEMs_branding - Display branding string
  2278. * @ioc: per adapter object
  2279. *
  2280. * Return nothing.
  2281. */
  2282. static void
  2283. _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
  2284. {
  2285. if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
  2286. return;
  2287. switch (ioc->pdev->subsystem_vendor) {
  2288. case PCI_VENDOR_ID_INTEL:
  2289. switch (ioc->pdev->device) {
  2290. case MPI2_MFGPAGE_DEVID_SAS2008:
  2291. switch (ioc->pdev->subsystem_device) {
  2292. case MPT2SAS_INTEL_RMS2LL080_SSDID:
  2293. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2294. MPT2SAS_INTEL_RMS2LL080_BRANDING);
  2295. break;
  2296. case MPT2SAS_INTEL_RMS2LL040_SSDID:
  2297. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2298. MPT2SAS_INTEL_RMS2LL040_BRANDING);
  2299. break;
  2300. case MPT2SAS_INTEL_SSD910_SSDID:
  2301. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2302. MPT2SAS_INTEL_SSD910_BRANDING);
  2303. break;
  2304. default:
  2305. pr_info(MPT3SAS_FMT
  2306. "Intel(R) Controller: Subsystem ID: 0x%X\n",
  2307. ioc->name, ioc->pdev->subsystem_device);
  2308. break;
  2309. }
  2310. case MPI2_MFGPAGE_DEVID_SAS2308_2:
  2311. switch (ioc->pdev->subsystem_device) {
  2312. case MPT2SAS_INTEL_RS25GB008_SSDID:
  2313. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2314. MPT2SAS_INTEL_RS25GB008_BRANDING);
  2315. break;
  2316. case MPT2SAS_INTEL_RMS25JB080_SSDID:
  2317. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2318. MPT2SAS_INTEL_RMS25JB080_BRANDING);
  2319. break;
  2320. case MPT2SAS_INTEL_RMS25JB040_SSDID:
  2321. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2322. MPT2SAS_INTEL_RMS25JB040_BRANDING);
  2323. break;
  2324. case MPT2SAS_INTEL_RMS25KB080_SSDID:
  2325. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2326. MPT2SAS_INTEL_RMS25KB080_BRANDING);
  2327. break;
  2328. case MPT2SAS_INTEL_RMS25KB040_SSDID:
  2329. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2330. MPT2SAS_INTEL_RMS25KB040_BRANDING);
  2331. break;
  2332. case MPT2SAS_INTEL_RMS25LB040_SSDID:
  2333. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2334. MPT2SAS_INTEL_RMS25LB040_BRANDING);
  2335. break;
  2336. case MPT2SAS_INTEL_RMS25LB080_SSDID:
  2337. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2338. MPT2SAS_INTEL_RMS25LB080_BRANDING);
  2339. break;
  2340. default:
  2341. pr_info(MPT3SAS_FMT
  2342. "Intel(R) Controller: Subsystem ID: 0x%X\n",
  2343. ioc->name, ioc->pdev->subsystem_device);
  2344. break;
  2345. }
  2346. case MPI25_MFGPAGE_DEVID_SAS3008:
  2347. switch (ioc->pdev->subsystem_device) {
  2348. case MPT3SAS_INTEL_RMS3JC080_SSDID:
  2349. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2350. MPT3SAS_INTEL_RMS3JC080_BRANDING);
  2351. break;
  2352. case MPT3SAS_INTEL_RS3GC008_SSDID:
  2353. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2354. MPT3SAS_INTEL_RS3GC008_BRANDING);
  2355. break;
  2356. case MPT3SAS_INTEL_RS3FC044_SSDID:
  2357. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2358. MPT3SAS_INTEL_RS3FC044_BRANDING);
  2359. break;
  2360. case MPT3SAS_INTEL_RS3UC080_SSDID:
  2361. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2362. MPT3SAS_INTEL_RS3UC080_BRANDING);
  2363. break;
  2364. default:
  2365. pr_info(MPT3SAS_FMT
  2366. "Intel(R) Controller: Subsystem ID: 0x%X\n",
  2367. ioc->name, ioc->pdev->subsystem_device);
  2368. break;
  2369. }
  2370. break;
  2371. default:
  2372. pr_info(MPT3SAS_FMT
  2373. "Intel(R) Controller: Subsystem ID: 0x%X\n",
  2374. ioc->name, ioc->pdev->subsystem_device);
  2375. break;
  2376. }
  2377. break;
  2378. case PCI_VENDOR_ID_DELL:
  2379. switch (ioc->pdev->device) {
  2380. case MPI2_MFGPAGE_DEVID_SAS2008:
  2381. switch (ioc->pdev->subsystem_device) {
  2382. case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
  2383. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2384. MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
  2385. break;
  2386. case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
  2387. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2388. MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
  2389. break;
  2390. case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
  2391. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2392. MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
  2393. break;
  2394. case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
  2395. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2396. MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
  2397. break;
  2398. case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
  2399. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2400. MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
  2401. break;
  2402. case MPT2SAS_DELL_PERC_H200_SSDID:
  2403. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2404. MPT2SAS_DELL_PERC_H200_BRANDING);
  2405. break;
  2406. case MPT2SAS_DELL_6GBPS_SAS_SSDID:
  2407. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2408. MPT2SAS_DELL_6GBPS_SAS_BRANDING);
  2409. break;
  2410. default:
  2411. pr_info(MPT3SAS_FMT
  2412. "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
  2413. ioc->name, ioc->pdev->subsystem_device);
  2414. break;
  2415. }
  2416. break;
  2417. case MPI25_MFGPAGE_DEVID_SAS3008:
  2418. switch (ioc->pdev->subsystem_device) {
  2419. case MPT3SAS_DELL_12G_HBA_SSDID:
  2420. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2421. MPT3SAS_DELL_12G_HBA_BRANDING);
  2422. break;
  2423. default:
  2424. pr_info(MPT3SAS_FMT
  2425. "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
  2426. ioc->name, ioc->pdev->subsystem_device);
  2427. break;
  2428. }
  2429. break;
  2430. default:
  2431. pr_info(MPT3SAS_FMT
  2432. "Dell HBA: Subsystem ID: 0x%X\n", ioc->name,
  2433. ioc->pdev->subsystem_device);
  2434. break;
  2435. }
  2436. break;
  2437. case PCI_VENDOR_ID_CISCO:
  2438. switch (ioc->pdev->device) {
  2439. case MPI25_MFGPAGE_DEVID_SAS3008:
  2440. switch (ioc->pdev->subsystem_device) {
  2441. case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
  2442. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2443. MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
  2444. break;
  2445. case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
  2446. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2447. MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
  2448. break;
  2449. case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
  2450. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2451. MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
  2452. break;
  2453. default:
  2454. pr_info(MPT3SAS_FMT
  2455. "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
  2456. ioc->name, ioc->pdev->subsystem_device);
  2457. break;
  2458. }
  2459. break;
  2460. case MPI25_MFGPAGE_DEVID_SAS3108_1:
  2461. switch (ioc->pdev->subsystem_device) {
  2462. case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
  2463. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2464. MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
  2465. break;
  2466. case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
  2467. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2468. MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING
  2469. );
  2470. break;
  2471. default:
  2472. pr_info(MPT3SAS_FMT
  2473. "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
  2474. ioc->name, ioc->pdev->subsystem_device);
  2475. break;
  2476. }
  2477. break;
  2478. default:
  2479. pr_info(MPT3SAS_FMT
  2480. "Cisco SAS HBA: Subsystem ID: 0x%X\n",
  2481. ioc->name, ioc->pdev->subsystem_device);
  2482. break;
  2483. }
  2484. break;
  2485. case MPT2SAS_HP_3PAR_SSVID:
  2486. switch (ioc->pdev->device) {
  2487. case MPI2_MFGPAGE_DEVID_SAS2004:
  2488. switch (ioc->pdev->subsystem_device) {
  2489. case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
  2490. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2491. MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
  2492. break;
  2493. default:
  2494. pr_info(MPT3SAS_FMT
  2495. "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
  2496. ioc->name, ioc->pdev->subsystem_device);
  2497. break;
  2498. }
  2499. case MPI2_MFGPAGE_DEVID_SAS2308_2:
  2500. switch (ioc->pdev->subsystem_device) {
  2501. case MPT2SAS_HP_2_4_INTERNAL_SSDID:
  2502. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2503. MPT2SAS_HP_2_4_INTERNAL_BRANDING);
  2504. break;
  2505. case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
  2506. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2507. MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
  2508. break;
  2509. case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
  2510. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2511. MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
  2512. break;
  2513. case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
  2514. pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2515. MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
  2516. break;
  2517. default:
  2518. pr_info(MPT3SAS_FMT
  2519. "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
  2520. ioc->name, ioc->pdev->subsystem_device);
  2521. break;
  2522. }
  2523. default:
  2524. pr_info(MPT3SAS_FMT
  2525. "HP SAS HBA: Subsystem ID: 0x%X\n",
  2526. ioc->name, ioc->pdev->subsystem_device);
  2527. break;
  2528. }
  2529. default:
  2530. break;
  2531. }
  2532. }
  2533. /**
  2534. * _base_display_ioc_capabilities - Disply IOC's capabilities.
  2535. * @ioc: per adapter object
  2536. *
  2537. * Return nothing.
  2538. */
  2539. static void
  2540. _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
  2541. {
  2542. int i = 0;
  2543. char desc[16];
  2544. u32 iounit_pg1_flags;
  2545. u32 bios_version;
  2546. bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
  2547. strncpy(desc, ioc->manu_pg0.ChipName, 16);
  2548. pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
  2549. "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
  2550. ioc->name, desc,
  2551. (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
  2552. (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
  2553. (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
  2554. ioc->facts.FWVersion.Word & 0x000000FF,
  2555. ioc->pdev->revision,
  2556. (bios_version & 0xFF000000) >> 24,
  2557. (bios_version & 0x00FF0000) >> 16,
  2558. (bios_version & 0x0000FF00) >> 8,
  2559. bios_version & 0x000000FF);
  2560. _base_display_OEMs_branding(ioc);
  2561. pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
  2562. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
  2563. pr_info("Initiator");
  2564. i++;
  2565. }
  2566. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
  2567. pr_info("%sTarget", i ? "," : "");
  2568. i++;
  2569. }
  2570. i = 0;
  2571. pr_info("), ");
  2572. pr_info("Capabilities=(");
  2573. if (!ioc->hide_ir_msg) {
  2574. if (ioc->facts.IOCCapabilities &
  2575. MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
  2576. pr_info("Raid");
  2577. i++;
  2578. }
  2579. }
  2580. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
  2581. pr_info("%sTLR", i ? "," : "");
  2582. i++;
  2583. }
  2584. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
  2585. pr_info("%sMulticast", i ? "," : "");
  2586. i++;
  2587. }
  2588. if (ioc->facts.IOCCapabilities &
  2589. MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
  2590. pr_info("%sBIDI Target", i ? "," : "");
  2591. i++;
  2592. }
  2593. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
  2594. pr_info("%sEEDP", i ? "," : "");
  2595. i++;
  2596. }
  2597. if (ioc->facts.IOCCapabilities &
  2598. MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
  2599. pr_info("%sSnapshot Buffer", i ? "," : "");
  2600. i++;
  2601. }
  2602. if (ioc->facts.IOCCapabilities &
  2603. MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
  2604. pr_info("%sDiag Trace Buffer", i ? "," : "");
  2605. i++;
  2606. }
  2607. if (ioc->facts.IOCCapabilities &
  2608. MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
  2609. pr_info("%sDiag Extended Buffer", i ? "," : "");
  2610. i++;
  2611. }
  2612. if (ioc->facts.IOCCapabilities &
  2613. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
  2614. pr_info("%sTask Set Full", i ? "," : "");
  2615. i++;
  2616. }
  2617. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  2618. if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
  2619. pr_info("%sNCQ", i ? "," : "");
  2620. i++;
  2621. }
  2622. pr_info(")\n");
  2623. }
  2624. /**
  2625. * mpt3sas_base_update_missing_delay - change the missing delay timers
  2626. * @ioc: per adapter object
  2627. * @device_missing_delay: amount of time till device is reported missing
  2628. * @io_missing_delay: interval IO is returned when there is a missing device
  2629. *
  2630. * Return nothing.
  2631. *
  2632. * Passed on the command line, this function will modify the device missing
  2633. * delay, as well as the io missing delay. This should be called at driver
  2634. * load time.
  2635. */
  2636. void
  2637. mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
  2638. u16 device_missing_delay, u8 io_missing_delay)
  2639. {
  2640. u16 dmd, dmd_new, dmd_orignal;
  2641. u8 io_missing_delay_original;
  2642. u16 sz;
  2643. Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
  2644. Mpi2ConfigReply_t mpi_reply;
  2645. u8 num_phys = 0;
  2646. u16 ioc_status;
  2647. mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
  2648. if (!num_phys)
  2649. return;
  2650. sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
  2651. sizeof(Mpi2SasIOUnit1PhyData_t));
  2652. sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
  2653. if (!sas_iounit_pg1) {
  2654. pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
  2655. ioc->name, __FILE__, __LINE__, __func__);
  2656. goto out;
  2657. }
  2658. if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
  2659. sas_iounit_pg1, sz))) {
  2660. pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
  2661. ioc->name, __FILE__, __LINE__, __func__);
  2662. goto out;
  2663. }
  2664. ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
  2665. MPI2_IOCSTATUS_MASK;
  2666. if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
  2667. pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
  2668. ioc->name, __FILE__, __LINE__, __func__);
  2669. goto out;
  2670. }
  2671. /* device missing delay */
  2672. dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
  2673. if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
  2674. dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
  2675. else
  2676. dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
  2677. dmd_orignal = dmd;
  2678. if (device_missing_delay > 0x7F) {
  2679. dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
  2680. device_missing_delay;
  2681. dmd = dmd / 16;
  2682. dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
  2683. } else
  2684. dmd = device_missing_delay;
  2685. sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
  2686. /* io missing delay */
  2687. io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
  2688. sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
  2689. if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
  2690. sz)) {
  2691. if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
  2692. dmd_new = (dmd &
  2693. MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
  2694. else
  2695. dmd_new =
  2696. dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
  2697. pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
  2698. ioc->name, dmd_orignal, dmd_new);
  2699. pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
  2700. ioc->name, io_missing_delay_original,
  2701. io_missing_delay);
  2702. ioc->device_missing_delay = dmd_new;
  2703. ioc->io_missing_delay = io_missing_delay;
  2704. }
  2705. out:
  2706. kfree(sas_iounit_pg1);
  2707. }
  2708. /**
  2709. * _base_static_config_pages - static start of day config pages
  2710. * @ioc: per adapter object
  2711. *
  2712. * Return nothing.
  2713. */
  2714. static void
  2715. _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
  2716. {
  2717. Mpi2ConfigReply_t mpi_reply;
  2718. u32 iounit_pg1_flags;
  2719. mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
  2720. if (ioc->ir_firmware)
  2721. mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
  2722. &ioc->manu_pg10);
  2723. /*
  2724. * Ensure correct T10 PI operation if vendor left EEDPTagMode
  2725. * flag unset in NVDATA.
  2726. */
  2727. mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
  2728. if (ioc->manu_pg11.EEDPTagMode == 0) {
  2729. pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
  2730. ioc->name);
  2731. ioc->manu_pg11.EEDPTagMode &= ~0x3;
  2732. ioc->manu_pg11.EEDPTagMode |= 0x1;
  2733. mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
  2734. &ioc->manu_pg11);
  2735. }
  2736. mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
  2737. mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
  2738. mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
  2739. mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
  2740. mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  2741. mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
  2742. _base_display_ioc_capabilities(ioc);
  2743. /*
  2744. * Enable task_set_full handling in iounit_pg1 when the
  2745. * facts capabilities indicate that its supported.
  2746. */
  2747. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  2748. if ((ioc->facts.IOCCapabilities &
  2749. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
  2750. iounit_pg1_flags &=
  2751. ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  2752. else
  2753. iounit_pg1_flags |=
  2754. MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  2755. ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
  2756. mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  2757. if (ioc->iounit_pg8.NumSensors)
  2758. ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
  2759. }
  2760. /**
  2761. * _base_release_memory_pools - release memory
  2762. * @ioc: per adapter object
  2763. *
  2764. * Free memory allocated from _base_allocate_memory_pools.
  2765. *
  2766. * Return nothing.
  2767. */
  2768. static void
  2769. _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
  2770. {
  2771. int i = 0;
  2772. struct reply_post_struct *rps;
  2773. dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2774. __func__));
  2775. if (ioc->request) {
  2776. pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
  2777. ioc->request, ioc->request_dma);
  2778. dexitprintk(ioc, pr_info(MPT3SAS_FMT
  2779. "request_pool(0x%p): free\n",
  2780. ioc->name, ioc->request));
  2781. ioc->request = NULL;
  2782. }
  2783. if (ioc->sense) {
  2784. pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
  2785. if (ioc->sense_dma_pool)
  2786. pci_pool_destroy(ioc->sense_dma_pool);
  2787. dexitprintk(ioc, pr_info(MPT3SAS_FMT
  2788. "sense_pool(0x%p): free\n",
  2789. ioc->name, ioc->sense));
  2790. ioc->sense = NULL;
  2791. }
  2792. if (ioc->reply) {
  2793. pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
  2794. if (ioc->reply_dma_pool)
  2795. pci_pool_destroy(ioc->reply_dma_pool);
  2796. dexitprintk(ioc, pr_info(MPT3SAS_FMT
  2797. "reply_pool(0x%p): free\n",
  2798. ioc->name, ioc->reply));
  2799. ioc->reply = NULL;
  2800. }
  2801. if (ioc->reply_free) {
  2802. pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
  2803. ioc->reply_free_dma);
  2804. if (ioc->reply_free_dma_pool)
  2805. pci_pool_destroy(ioc->reply_free_dma_pool);
  2806. dexitprintk(ioc, pr_info(MPT3SAS_FMT
  2807. "reply_free_pool(0x%p): free\n",
  2808. ioc->name, ioc->reply_free));
  2809. ioc->reply_free = NULL;
  2810. }
  2811. if (ioc->reply_post) {
  2812. do {
  2813. rps = &ioc->reply_post[i];
  2814. if (rps->reply_post_free) {
  2815. pci_pool_free(
  2816. ioc->reply_post_free_dma_pool,
  2817. rps->reply_post_free,
  2818. rps->reply_post_free_dma);
  2819. dexitprintk(ioc, pr_info(MPT3SAS_FMT
  2820. "reply_post_free_pool(0x%p): free\n",
  2821. ioc->name, rps->reply_post_free));
  2822. rps->reply_post_free = NULL;
  2823. }
  2824. } while (ioc->rdpq_array_enable &&
  2825. (++i < ioc->reply_queue_count));
  2826. if (ioc->reply_post_free_dma_pool)
  2827. pci_pool_destroy(ioc->reply_post_free_dma_pool);
  2828. kfree(ioc->reply_post);
  2829. }
  2830. if (ioc->config_page) {
  2831. dexitprintk(ioc, pr_info(MPT3SAS_FMT
  2832. "config_page(0x%p): free\n", ioc->name,
  2833. ioc->config_page));
  2834. pci_free_consistent(ioc->pdev, ioc->config_page_sz,
  2835. ioc->config_page, ioc->config_page_dma);
  2836. }
  2837. if (ioc->scsi_lookup) {
  2838. free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
  2839. ioc->scsi_lookup = NULL;
  2840. }
  2841. kfree(ioc->hpr_lookup);
  2842. kfree(ioc->internal_lookup);
  2843. if (ioc->chain_lookup) {
  2844. for (i = 0; i < ioc->chain_depth; i++) {
  2845. if (ioc->chain_lookup[i].chain_buffer)
  2846. pci_pool_free(ioc->chain_dma_pool,
  2847. ioc->chain_lookup[i].chain_buffer,
  2848. ioc->chain_lookup[i].chain_buffer_dma);
  2849. }
  2850. if (ioc->chain_dma_pool)
  2851. pci_pool_destroy(ioc->chain_dma_pool);
  2852. free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
  2853. ioc->chain_lookup = NULL;
  2854. }
  2855. }
  2856. /**
  2857. * _base_allocate_memory_pools - allocate start of day memory pools
  2858. * @ioc: per adapter object
  2859. *
  2860. * Returns 0 success, anything else error
  2861. */
  2862. static int
  2863. _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
  2864. {
  2865. struct mpt3sas_facts *facts;
  2866. u16 max_sge_elements;
  2867. u16 chains_needed_per_io;
  2868. u32 sz, total_sz, reply_post_free_sz;
  2869. u32 retry_sz;
  2870. u16 max_request_credit;
  2871. unsigned short sg_tablesize;
  2872. u16 sge_size;
  2873. int i;
  2874. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2875. __func__));
  2876. retry_sz = 0;
  2877. facts = &ioc->facts;
  2878. /* command line tunables for max sgl entries */
  2879. if (max_sgl_entries != -1)
  2880. sg_tablesize = max_sgl_entries;
  2881. else {
  2882. if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
  2883. sg_tablesize = MPT2SAS_SG_DEPTH;
  2884. else
  2885. sg_tablesize = MPT3SAS_SG_DEPTH;
  2886. }
  2887. if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
  2888. sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
  2889. else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
  2890. sg_tablesize = min_t(unsigned short, sg_tablesize,
  2891. SG_MAX_SEGMENTS);
  2892. pr_warn(MPT3SAS_FMT
  2893. "sg_tablesize(%u) is bigger than kernel"
  2894. " defined SG_CHUNK_SIZE(%u)\n", ioc->name,
  2895. sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
  2896. }
  2897. ioc->shost->sg_tablesize = sg_tablesize;
  2898. ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
  2899. (facts->RequestCredit / 4));
  2900. if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
  2901. if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
  2902. INTERNAL_SCSIIO_CMDS_COUNT)) {
  2903. pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \
  2904. Credits, it has just %d number of credits\n",
  2905. ioc->name, facts->RequestCredit);
  2906. return -ENOMEM;
  2907. }
  2908. ioc->internal_depth = 10;
  2909. }
  2910. ioc->hi_priority_depth = ioc->internal_depth - (5);
  2911. /* command line tunables for max controller queue depth */
  2912. if (max_queue_depth != -1 && max_queue_depth != 0) {
  2913. max_request_credit = min_t(u16, max_queue_depth +
  2914. ioc->internal_depth, facts->RequestCredit);
  2915. if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
  2916. max_request_credit = MAX_HBA_QUEUE_DEPTH;
  2917. } else
  2918. max_request_credit = min_t(u16, facts->RequestCredit,
  2919. MAX_HBA_QUEUE_DEPTH);
  2920. /* Firmware maintains additional facts->HighPriorityCredit number of
  2921. * credits for HiPriprity Request messages, so hba queue depth will be
  2922. * sum of max_request_credit and high priority queue depth.
  2923. */
  2924. ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
  2925. /* request frame size */
  2926. ioc->request_sz = facts->IOCRequestFrameSize * 4;
  2927. /* reply frame size */
  2928. ioc->reply_sz = facts->ReplyFrameSize * 4;
  2929. /* chain segment size */
  2930. if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
  2931. if (facts->IOCMaxChainSegmentSize)
  2932. ioc->chain_segment_sz =
  2933. facts->IOCMaxChainSegmentSize *
  2934. MAX_CHAIN_ELEMT_SZ;
  2935. else
  2936. /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
  2937. ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
  2938. MAX_CHAIN_ELEMT_SZ;
  2939. } else
  2940. ioc->chain_segment_sz = ioc->request_sz;
  2941. /* calculate the max scatter element size */
  2942. sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
  2943. retry_allocation:
  2944. total_sz = 0;
  2945. /* calculate number of sg elements left over in the 1st frame */
  2946. max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
  2947. sizeof(Mpi2SGEIOUnion_t)) + sge_size);
  2948. ioc->max_sges_in_main_message = max_sge_elements/sge_size;
  2949. /* now do the same for a chain buffer */
  2950. max_sge_elements = ioc->chain_segment_sz - sge_size;
  2951. ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
  2952. /*
  2953. * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
  2954. */
  2955. chains_needed_per_io = ((ioc->shost->sg_tablesize -
  2956. ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
  2957. + 1;
  2958. if (chains_needed_per_io > facts->MaxChainDepth) {
  2959. chains_needed_per_io = facts->MaxChainDepth;
  2960. ioc->shost->sg_tablesize = min_t(u16,
  2961. ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
  2962. * chains_needed_per_io), ioc->shost->sg_tablesize);
  2963. }
  2964. ioc->chains_needed_per_io = chains_needed_per_io;
  2965. /* reply free queue sizing - taking into account for 64 FW events */
  2966. ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
  2967. /* calculate reply descriptor post queue depth */
  2968. ioc->reply_post_queue_depth = ioc->hba_queue_depth +
  2969. ioc->reply_free_queue_depth + 1 ;
  2970. /* align the reply post queue on the next 16 count boundary */
  2971. if (ioc->reply_post_queue_depth % 16)
  2972. ioc->reply_post_queue_depth += 16 -
  2973. (ioc->reply_post_queue_depth % 16);
  2974. if (ioc->reply_post_queue_depth >
  2975. facts->MaxReplyDescriptorPostQueueDepth) {
  2976. ioc->reply_post_queue_depth =
  2977. facts->MaxReplyDescriptorPostQueueDepth -
  2978. (facts->MaxReplyDescriptorPostQueueDepth % 16);
  2979. ioc->hba_queue_depth =
  2980. ((ioc->reply_post_queue_depth - 64) / 2) - 1;
  2981. ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
  2982. }
  2983. dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
  2984. "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
  2985. "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
  2986. ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
  2987. ioc->chains_needed_per_io));
  2988. /* reply post queue, 16 byte align */
  2989. reply_post_free_sz = ioc->reply_post_queue_depth *
  2990. sizeof(Mpi2DefaultReplyDescriptor_t);
  2991. sz = reply_post_free_sz;
  2992. if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
  2993. sz *= ioc->reply_queue_count;
  2994. ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
  2995. (ioc->reply_queue_count):1,
  2996. sizeof(struct reply_post_struct), GFP_KERNEL);
  2997. if (!ioc->reply_post) {
  2998. pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
  2999. ioc->name);
  3000. goto out;
  3001. }
  3002. ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
  3003. ioc->pdev, sz, 16, 0);
  3004. if (!ioc->reply_post_free_dma_pool) {
  3005. pr_err(MPT3SAS_FMT
  3006. "reply_post_free pool: pci_pool_create failed\n",
  3007. ioc->name);
  3008. goto out;
  3009. }
  3010. i = 0;
  3011. do {
  3012. ioc->reply_post[i].reply_post_free =
  3013. pci_pool_alloc(ioc->reply_post_free_dma_pool,
  3014. GFP_KERNEL,
  3015. &ioc->reply_post[i].reply_post_free_dma);
  3016. if (!ioc->reply_post[i].reply_post_free) {
  3017. pr_err(MPT3SAS_FMT
  3018. "reply_post_free pool: pci_pool_alloc failed\n",
  3019. ioc->name);
  3020. goto out;
  3021. }
  3022. memset(ioc->reply_post[i].reply_post_free, 0, sz);
  3023. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3024. "reply post free pool (0x%p): depth(%d),"
  3025. "element_size(%d), pool_size(%d kB)\n", ioc->name,
  3026. ioc->reply_post[i].reply_post_free,
  3027. ioc->reply_post_queue_depth, 8, sz/1024));
  3028. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3029. "reply_post_free_dma = (0x%llx)\n", ioc->name,
  3030. (unsigned long long)
  3031. ioc->reply_post[i].reply_post_free_dma));
  3032. total_sz += sz;
  3033. } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
  3034. if (ioc->dma_mask == 64) {
  3035. if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
  3036. pr_warn(MPT3SAS_FMT
  3037. "no suitable consistent DMA mask for %s\n",
  3038. ioc->name, pci_name(ioc->pdev));
  3039. goto out;
  3040. }
  3041. }
  3042. ioc->scsiio_depth = ioc->hba_queue_depth -
  3043. ioc->hi_priority_depth - ioc->internal_depth;
  3044. /* set the scsi host can_queue depth
  3045. * with some internal commands that could be outstanding
  3046. */
  3047. ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
  3048. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3049. "scsi host: can_queue depth (%d)\n",
  3050. ioc->name, ioc->shost->can_queue));
  3051. /* contiguous pool for request and chains, 16 byte align, one extra "
  3052. * "frame for smid=0
  3053. */
  3054. ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
  3055. sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
  3056. /* hi-priority queue */
  3057. sz += (ioc->hi_priority_depth * ioc->request_sz);
  3058. /* internal queue */
  3059. sz += (ioc->internal_depth * ioc->request_sz);
  3060. ioc->request_dma_sz = sz;
  3061. ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
  3062. if (!ioc->request) {
  3063. pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
  3064. "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  3065. "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
  3066. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  3067. if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
  3068. goto out;
  3069. retry_sz = 64;
  3070. ioc->hba_queue_depth -= retry_sz;
  3071. _base_release_memory_pools(ioc);
  3072. goto retry_allocation;
  3073. }
  3074. if (retry_sz)
  3075. pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
  3076. "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  3077. "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
  3078. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  3079. /* hi-priority queue */
  3080. ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
  3081. ioc->request_sz);
  3082. ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
  3083. ioc->request_sz);
  3084. /* internal queue */
  3085. ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
  3086. ioc->request_sz);
  3087. ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
  3088. ioc->request_sz);
  3089. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3090. "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
  3091. ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
  3092. (ioc->hba_queue_depth * ioc->request_sz)/1024));
  3093. dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
  3094. ioc->name, (unsigned long long) ioc->request_dma));
  3095. total_sz += sz;
  3096. sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
  3097. ioc->scsi_lookup_pages = get_order(sz);
  3098. ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
  3099. GFP_KERNEL, ioc->scsi_lookup_pages);
  3100. if (!ioc->scsi_lookup) {
  3101. pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
  3102. ioc->name, (int)sz);
  3103. goto out;
  3104. }
  3105. dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
  3106. ioc->name, ioc->request, ioc->scsiio_depth));
  3107. ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
  3108. sz = ioc->chain_depth * sizeof(struct chain_tracker);
  3109. ioc->chain_pages = get_order(sz);
  3110. ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
  3111. GFP_KERNEL, ioc->chain_pages);
  3112. if (!ioc->chain_lookup) {
  3113. pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
  3114. ioc->name);
  3115. goto out;
  3116. }
  3117. ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
  3118. ioc->chain_segment_sz, 16, 0);
  3119. if (!ioc->chain_dma_pool) {
  3120. pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
  3121. ioc->name);
  3122. goto out;
  3123. }
  3124. for (i = 0; i < ioc->chain_depth; i++) {
  3125. ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
  3126. ioc->chain_dma_pool , GFP_KERNEL,
  3127. &ioc->chain_lookup[i].chain_buffer_dma);
  3128. if (!ioc->chain_lookup[i].chain_buffer) {
  3129. ioc->chain_depth = i;
  3130. goto chain_done;
  3131. }
  3132. total_sz += ioc->chain_segment_sz;
  3133. }
  3134. chain_done:
  3135. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3136. "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
  3137. ioc->name, ioc->chain_depth, ioc->chain_segment_sz,
  3138. ((ioc->chain_depth * ioc->chain_segment_sz))/1024));
  3139. /* initialize hi-priority queue smid's */
  3140. ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
  3141. sizeof(struct request_tracker), GFP_KERNEL);
  3142. if (!ioc->hpr_lookup) {
  3143. pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
  3144. ioc->name);
  3145. goto out;
  3146. }
  3147. ioc->hi_priority_smid = ioc->scsiio_depth + 1;
  3148. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3149. "hi_priority(0x%p): depth(%d), start smid(%d)\n",
  3150. ioc->name, ioc->hi_priority,
  3151. ioc->hi_priority_depth, ioc->hi_priority_smid));
  3152. /* initialize internal queue smid's */
  3153. ioc->internal_lookup = kcalloc(ioc->internal_depth,
  3154. sizeof(struct request_tracker), GFP_KERNEL);
  3155. if (!ioc->internal_lookup) {
  3156. pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
  3157. ioc->name);
  3158. goto out;
  3159. }
  3160. ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
  3161. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3162. "internal(0x%p): depth(%d), start smid(%d)\n",
  3163. ioc->name, ioc->internal,
  3164. ioc->internal_depth, ioc->internal_smid));
  3165. /* sense buffers, 4 byte align */
  3166. sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
  3167. ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
  3168. 0);
  3169. if (!ioc->sense_dma_pool) {
  3170. pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
  3171. ioc->name);
  3172. goto out;
  3173. }
  3174. ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
  3175. &ioc->sense_dma);
  3176. if (!ioc->sense) {
  3177. pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
  3178. ioc->name);
  3179. goto out;
  3180. }
  3181. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3182. "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
  3183. "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
  3184. SCSI_SENSE_BUFFERSIZE, sz/1024));
  3185. dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
  3186. ioc->name, (unsigned long long)ioc->sense_dma));
  3187. total_sz += sz;
  3188. /* reply pool, 4 byte align */
  3189. sz = ioc->reply_free_queue_depth * ioc->reply_sz;
  3190. ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
  3191. 0);
  3192. if (!ioc->reply_dma_pool) {
  3193. pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
  3194. ioc->name);
  3195. goto out;
  3196. }
  3197. ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
  3198. &ioc->reply_dma);
  3199. if (!ioc->reply) {
  3200. pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
  3201. ioc->name);
  3202. goto out;
  3203. }
  3204. ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
  3205. ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
  3206. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3207. "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
  3208. ioc->name, ioc->reply,
  3209. ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
  3210. dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
  3211. ioc->name, (unsigned long long)ioc->reply_dma));
  3212. total_sz += sz;
  3213. /* reply free queue, 16 byte align */
  3214. sz = ioc->reply_free_queue_depth * 4;
  3215. ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
  3216. ioc->pdev, sz, 16, 0);
  3217. if (!ioc->reply_free_dma_pool) {
  3218. pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
  3219. ioc->name);
  3220. goto out;
  3221. }
  3222. ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
  3223. &ioc->reply_free_dma);
  3224. if (!ioc->reply_free) {
  3225. pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
  3226. ioc->name);
  3227. goto out;
  3228. }
  3229. memset(ioc->reply_free, 0, sz);
  3230. dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
  3231. "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
  3232. ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
  3233. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3234. "reply_free_dma (0x%llx)\n",
  3235. ioc->name, (unsigned long long)ioc->reply_free_dma));
  3236. total_sz += sz;
  3237. ioc->config_page_sz = 512;
  3238. ioc->config_page = pci_alloc_consistent(ioc->pdev,
  3239. ioc->config_page_sz, &ioc->config_page_dma);
  3240. if (!ioc->config_page) {
  3241. pr_err(MPT3SAS_FMT
  3242. "config page: pci_pool_alloc failed\n",
  3243. ioc->name);
  3244. goto out;
  3245. }
  3246. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3247. "config page(0x%p): size(%d)\n",
  3248. ioc->name, ioc->config_page, ioc->config_page_sz));
  3249. dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
  3250. ioc->name, (unsigned long long)ioc->config_page_dma));
  3251. total_sz += ioc->config_page_sz;
  3252. pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
  3253. ioc->name, total_sz/1024);
  3254. pr_info(MPT3SAS_FMT
  3255. "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
  3256. ioc->name, ioc->shost->can_queue, facts->RequestCredit);
  3257. pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
  3258. ioc->name, ioc->shost->sg_tablesize);
  3259. return 0;
  3260. out:
  3261. return -ENOMEM;
  3262. }
  3263. /**
  3264. * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
  3265. * @ioc: Pointer to MPT_ADAPTER structure
  3266. * @cooked: Request raw or cooked IOC state
  3267. *
  3268. * Returns all IOC Doorbell register bits if cooked==0, else just the
  3269. * Doorbell bits in MPI_IOC_STATE_MASK.
  3270. */
  3271. u32
  3272. mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
  3273. {
  3274. u32 s, sc;
  3275. s = readl(&ioc->chip->Doorbell);
  3276. sc = s & MPI2_IOC_STATE_MASK;
  3277. return cooked ? sc : s;
  3278. }
  3279. /**
  3280. * _base_wait_on_iocstate - waiting on a particular ioc state
  3281. * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
  3282. * @timeout: timeout in second
  3283. *
  3284. * Returns 0 for success, non-zero for failure.
  3285. */
  3286. static int
  3287. _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout)
  3288. {
  3289. u32 count, cntdn;
  3290. u32 current_state;
  3291. count = 0;
  3292. cntdn = 1000 * timeout;
  3293. do {
  3294. current_state = mpt3sas_base_get_iocstate(ioc, 1);
  3295. if (current_state == ioc_state)
  3296. return 0;
  3297. if (count && current_state == MPI2_IOC_STATE_FAULT)
  3298. break;
  3299. usleep_range(1000, 1500);
  3300. count++;
  3301. } while (--cntdn);
  3302. return current_state;
  3303. }
  3304. /**
  3305. * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
  3306. * a write to the doorbell)
  3307. * @ioc: per adapter object
  3308. * @timeout: timeout in second
  3309. *
  3310. * Returns 0 for success, non-zero for failure.
  3311. *
  3312. * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
  3313. */
  3314. static int
  3315. _base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
  3316. static int
  3317. _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
  3318. {
  3319. u32 cntdn, count;
  3320. u32 int_status;
  3321. count = 0;
  3322. cntdn = 1000 * timeout;
  3323. do {
  3324. int_status = readl(&ioc->chip->HostInterruptStatus);
  3325. if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  3326. dhsprintk(ioc, pr_info(MPT3SAS_FMT
  3327. "%s: successful count(%d), timeout(%d)\n",
  3328. ioc->name, __func__, count, timeout));
  3329. return 0;
  3330. }
  3331. usleep_range(1000, 1500);
  3332. count++;
  3333. } while (--cntdn);
  3334. pr_err(MPT3SAS_FMT
  3335. "%s: failed due to timeout count(%d), int_status(%x)!\n",
  3336. ioc->name, __func__, count, int_status);
  3337. return -EFAULT;
  3338. }
  3339. static int
  3340. _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
  3341. {
  3342. u32 cntdn, count;
  3343. u32 int_status;
  3344. count = 0;
  3345. cntdn = 2000 * timeout;
  3346. do {
  3347. int_status = readl(&ioc->chip->HostInterruptStatus);
  3348. if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  3349. dhsprintk(ioc, pr_info(MPT3SAS_FMT
  3350. "%s: successful count(%d), timeout(%d)\n",
  3351. ioc->name, __func__, count, timeout));
  3352. return 0;
  3353. }
  3354. udelay(500);
  3355. count++;
  3356. } while (--cntdn);
  3357. pr_err(MPT3SAS_FMT
  3358. "%s: failed due to timeout count(%d), int_status(%x)!\n",
  3359. ioc->name, __func__, count, int_status);
  3360. return -EFAULT;
  3361. }
  3362. /**
  3363. * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
  3364. * @ioc: per adapter object
  3365. * @timeout: timeout in second
  3366. *
  3367. * Returns 0 for success, non-zero for failure.
  3368. *
  3369. * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
  3370. * doorbell.
  3371. */
  3372. static int
  3373. _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout)
  3374. {
  3375. u32 cntdn, count;
  3376. u32 int_status;
  3377. u32 doorbell;
  3378. count = 0;
  3379. cntdn = 1000 * timeout;
  3380. do {
  3381. int_status = readl(&ioc->chip->HostInterruptStatus);
  3382. if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
  3383. dhsprintk(ioc, pr_info(MPT3SAS_FMT
  3384. "%s: successful count(%d), timeout(%d)\n",
  3385. ioc->name, __func__, count, timeout));
  3386. return 0;
  3387. } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  3388. doorbell = readl(&ioc->chip->Doorbell);
  3389. if ((doorbell & MPI2_IOC_STATE_MASK) ==
  3390. MPI2_IOC_STATE_FAULT) {
  3391. mpt3sas_base_fault_info(ioc , doorbell);
  3392. return -EFAULT;
  3393. }
  3394. } else if (int_status == 0xFFFFFFFF)
  3395. goto out;
  3396. usleep_range(1000, 1500);
  3397. count++;
  3398. } while (--cntdn);
  3399. out:
  3400. pr_err(MPT3SAS_FMT
  3401. "%s: failed due to timeout count(%d), int_status(%x)!\n",
  3402. ioc->name, __func__, count, int_status);
  3403. return -EFAULT;
  3404. }
  3405. /**
  3406. * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
  3407. * @ioc: per adapter object
  3408. * @timeout: timeout in second
  3409. *
  3410. * Returns 0 for success, non-zero for failure.
  3411. *
  3412. */
  3413. static int
  3414. _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout)
  3415. {
  3416. u32 cntdn, count;
  3417. u32 doorbell_reg;
  3418. count = 0;
  3419. cntdn = 1000 * timeout;
  3420. do {
  3421. doorbell_reg = readl(&ioc->chip->Doorbell);
  3422. if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
  3423. dhsprintk(ioc, pr_info(MPT3SAS_FMT
  3424. "%s: successful count(%d), timeout(%d)\n",
  3425. ioc->name, __func__, count, timeout));
  3426. return 0;
  3427. }
  3428. usleep_range(1000, 1500);
  3429. count++;
  3430. } while (--cntdn);
  3431. pr_err(MPT3SAS_FMT
  3432. "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
  3433. ioc->name, __func__, count, doorbell_reg);
  3434. return -EFAULT;
  3435. }
  3436. /**
  3437. * _base_send_ioc_reset - send doorbell reset
  3438. * @ioc: per adapter object
  3439. * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
  3440. * @timeout: timeout in second
  3441. *
  3442. * Returns 0 for success, non-zero for failure.
  3443. */
  3444. static int
  3445. _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout)
  3446. {
  3447. u32 ioc_state;
  3448. int r = 0;
  3449. if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
  3450. pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
  3451. ioc->name, __func__);
  3452. return -EFAULT;
  3453. }
  3454. if (!(ioc->facts.IOCCapabilities &
  3455. MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
  3456. return -EFAULT;
  3457. pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
  3458. writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
  3459. &ioc->chip->Doorbell);
  3460. if ((_base_wait_for_doorbell_ack(ioc, 15))) {
  3461. r = -EFAULT;
  3462. goto out;
  3463. }
  3464. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
  3465. if (ioc_state) {
  3466. pr_err(MPT3SAS_FMT
  3467. "%s: failed going to ready state (ioc_state=0x%x)\n",
  3468. ioc->name, __func__, ioc_state);
  3469. r = -EFAULT;
  3470. goto out;
  3471. }
  3472. out:
  3473. pr_info(MPT3SAS_FMT "message unit reset: %s\n",
  3474. ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
  3475. return r;
  3476. }
  3477. /**
  3478. * _base_handshake_req_reply_wait - send request thru doorbell interface
  3479. * @ioc: per adapter object
  3480. * @request_bytes: request length
  3481. * @request: pointer having request payload
  3482. * @reply_bytes: reply length
  3483. * @reply: pointer to reply payload
  3484. * @timeout: timeout in second
  3485. *
  3486. * Returns 0 for success, non-zero for failure.
  3487. */
  3488. static int
  3489. _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
  3490. u32 *request, int reply_bytes, u16 *reply, int timeout)
  3491. {
  3492. MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
  3493. int i;
  3494. u8 failed;
  3495. __le32 *mfp;
  3496. /* make sure doorbell is not in use */
  3497. if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
  3498. pr_err(MPT3SAS_FMT
  3499. "doorbell is in use (line=%d)\n",
  3500. ioc->name, __LINE__);
  3501. return -EFAULT;
  3502. }
  3503. /* clear pending doorbell interrupts from previous state changes */
  3504. if (readl(&ioc->chip->HostInterruptStatus) &
  3505. MPI2_HIS_IOC2SYS_DB_STATUS)
  3506. writel(0, &ioc->chip->HostInterruptStatus);
  3507. /* send message to ioc */
  3508. writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
  3509. ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
  3510. &ioc->chip->Doorbell);
  3511. if ((_base_spin_on_doorbell_int(ioc, 5))) {
  3512. pr_err(MPT3SAS_FMT
  3513. "doorbell handshake int failed (line=%d)\n",
  3514. ioc->name, __LINE__);
  3515. return -EFAULT;
  3516. }
  3517. writel(0, &ioc->chip->HostInterruptStatus);
  3518. if ((_base_wait_for_doorbell_ack(ioc, 5))) {
  3519. pr_err(MPT3SAS_FMT
  3520. "doorbell handshake ack failed (line=%d)\n",
  3521. ioc->name, __LINE__);
  3522. return -EFAULT;
  3523. }
  3524. /* send message 32-bits at a time */
  3525. for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
  3526. writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
  3527. if ((_base_wait_for_doorbell_ack(ioc, 5)))
  3528. failed = 1;
  3529. }
  3530. if (failed) {
  3531. pr_err(MPT3SAS_FMT
  3532. "doorbell handshake sending request failed (line=%d)\n",
  3533. ioc->name, __LINE__);
  3534. return -EFAULT;
  3535. }
  3536. /* now wait for the reply */
  3537. if ((_base_wait_for_doorbell_int(ioc, timeout))) {
  3538. pr_err(MPT3SAS_FMT
  3539. "doorbell handshake int failed (line=%d)\n",
  3540. ioc->name, __LINE__);
  3541. return -EFAULT;
  3542. }
  3543. /* read the first two 16-bits, it gives the total length of the reply */
  3544. reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  3545. & MPI2_DOORBELL_DATA_MASK);
  3546. writel(0, &ioc->chip->HostInterruptStatus);
  3547. if ((_base_wait_for_doorbell_int(ioc, 5))) {
  3548. pr_err(MPT3SAS_FMT
  3549. "doorbell handshake int failed (line=%d)\n",
  3550. ioc->name, __LINE__);
  3551. return -EFAULT;
  3552. }
  3553. reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  3554. & MPI2_DOORBELL_DATA_MASK);
  3555. writel(0, &ioc->chip->HostInterruptStatus);
  3556. for (i = 2; i < default_reply->MsgLength * 2; i++) {
  3557. if ((_base_wait_for_doorbell_int(ioc, 5))) {
  3558. pr_err(MPT3SAS_FMT
  3559. "doorbell handshake int failed (line=%d)\n",
  3560. ioc->name, __LINE__);
  3561. return -EFAULT;
  3562. }
  3563. if (i >= reply_bytes/2) /* overflow case */
  3564. readl(&ioc->chip->Doorbell);
  3565. else
  3566. reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  3567. & MPI2_DOORBELL_DATA_MASK);
  3568. writel(0, &ioc->chip->HostInterruptStatus);
  3569. }
  3570. _base_wait_for_doorbell_int(ioc, 5);
  3571. if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
  3572. dhsprintk(ioc, pr_info(MPT3SAS_FMT
  3573. "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
  3574. }
  3575. writel(0, &ioc->chip->HostInterruptStatus);
  3576. if (ioc->logging_level & MPT_DEBUG_INIT) {
  3577. mfp = (__le32 *)reply;
  3578. pr_info("\toffset:data\n");
  3579. for (i = 0; i < reply_bytes/4; i++)
  3580. pr_info("\t[0x%02x]:%08x\n", i*4,
  3581. le32_to_cpu(mfp[i]));
  3582. }
  3583. return 0;
  3584. }
  3585. /**
  3586. * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
  3587. * @ioc: per adapter object
  3588. * @mpi_reply: the reply payload from FW
  3589. * @mpi_request: the request payload sent to FW
  3590. *
  3591. * The SAS IO Unit Control Request message allows the host to perform low-level
  3592. * operations, such as resets on the PHYs of the IO Unit, also allows the host
  3593. * to obtain the IOC assigned device handles for a device if it has other
  3594. * identifying information about the device, in addition allows the host to
  3595. * remove IOC resources associated with the device.
  3596. *
  3597. * Returns 0 for success, non-zero for failure.
  3598. */
  3599. int
  3600. mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
  3601. Mpi2SasIoUnitControlReply_t *mpi_reply,
  3602. Mpi2SasIoUnitControlRequest_t *mpi_request)
  3603. {
  3604. u16 smid;
  3605. u32 ioc_state;
  3606. bool issue_reset = false;
  3607. int rc;
  3608. void *request;
  3609. u16 wait_state_count;
  3610. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3611. __func__));
  3612. mutex_lock(&ioc->base_cmds.mutex);
  3613. if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
  3614. pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
  3615. ioc->name, __func__);
  3616. rc = -EAGAIN;
  3617. goto out;
  3618. }
  3619. wait_state_count = 0;
  3620. ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
  3621. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  3622. if (wait_state_count++ == 10) {
  3623. pr_err(MPT3SAS_FMT
  3624. "%s: failed due to ioc not operational\n",
  3625. ioc->name, __func__);
  3626. rc = -EFAULT;
  3627. goto out;
  3628. }
  3629. ssleep(1);
  3630. ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
  3631. pr_info(MPT3SAS_FMT
  3632. "%s: waiting for operational state(count=%d)\n",
  3633. ioc->name, __func__, wait_state_count);
  3634. }
  3635. smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
  3636. if (!smid) {
  3637. pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
  3638. ioc->name, __func__);
  3639. rc = -EAGAIN;
  3640. goto out;
  3641. }
  3642. rc = 0;
  3643. ioc->base_cmds.status = MPT3_CMD_PENDING;
  3644. request = mpt3sas_base_get_msg_frame(ioc, smid);
  3645. ioc->base_cmds.smid = smid;
  3646. memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
  3647. if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  3648. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
  3649. ioc->ioc_link_reset_in_progress = 1;
  3650. init_completion(&ioc->base_cmds.done);
  3651. mpt3sas_base_put_smid_default(ioc, smid);
  3652. wait_for_completion_timeout(&ioc->base_cmds.done,
  3653. msecs_to_jiffies(10000));
  3654. if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  3655. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
  3656. ioc->ioc_link_reset_in_progress)
  3657. ioc->ioc_link_reset_in_progress = 0;
  3658. if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
  3659. pr_err(MPT3SAS_FMT "%s: timeout\n",
  3660. ioc->name, __func__);
  3661. _debug_dump_mf(mpi_request,
  3662. sizeof(Mpi2SasIoUnitControlRequest_t)/4);
  3663. if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
  3664. issue_reset = true;
  3665. goto issue_host_reset;
  3666. }
  3667. if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
  3668. memcpy(mpi_reply, ioc->base_cmds.reply,
  3669. sizeof(Mpi2SasIoUnitControlReply_t));
  3670. else
  3671. memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
  3672. ioc->base_cmds.status = MPT3_CMD_NOT_USED;
  3673. goto out;
  3674. issue_host_reset:
  3675. if (issue_reset)
  3676. mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
  3677. ioc->base_cmds.status = MPT3_CMD_NOT_USED;
  3678. rc = -EFAULT;
  3679. out:
  3680. mutex_unlock(&ioc->base_cmds.mutex);
  3681. return rc;
  3682. }
  3683. /**
  3684. * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
  3685. * @ioc: per adapter object
  3686. * @mpi_reply: the reply payload from FW
  3687. * @mpi_request: the request payload sent to FW
  3688. *
  3689. * The SCSI Enclosure Processor request message causes the IOC to
  3690. * communicate with SES devices to control LED status signals.
  3691. *
  3692. * Returns 0 for success, non-zero for failure.
  3693. */
  3694. int
  3695. mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
  3696. Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
  3697. {
  3698. u16 smid;
  3699. u32 ioc_state;
  3700. bool issue_reset = false;
  3701. int rc;
  3702. void *request;
  3703. u16 wait_state_count;
  3704. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3705. __func__));
  3706. mutex_lock(&ioc->base_cmds.mutex);
  3707. if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
  3708. pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
  3709. ioc->name, __func__);
  3710. rc = -EAGAIN;
  3711. goto out;
  3712. }
  3713. wait_state_count = 0;
  3714. ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
  3715. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  3716. if (wait_state_count++ == 10) {
  3717. pr_err(MPT3SAS_FMT
  3718. "%s: failed due to ioc not operational\n",
  3719. ioc->name, __func__);
  3720. rc = -EFAULT;
  3721. goto out;
  3722. }
  3723. ssleep(1);
  3724. ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
  3725. pr_info(MPT3SAS_FMT
  3726. "%s: waiting for operational state(count=%d)\n",
  3727. ioc->name,
  3728. __func__, wait_state_count);
  3729. }
  3730. smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
  3731. if (!smid) {
  3732. pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
  3733. ioc->name, __func__);
  3734. rc = -EAGAIN;
  3735. goto out;
  3736. }
  3737. rc = 0;
  3738. ioc->base_cmds.status = MPT3_CMD_PENDING;
  3739. request = mpt3sas_base_get_msg_frame(ioc, smid);
  3740. ioc->base_cmds.smid = smid;
  3741. memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
  3742. init_completion(&ioc->base_cmds.done);
  3743. mpt3sas_base_put_smid_default(ioc, smid);
  3744. wait_for_completion_timeout(&ioc->base_cmds.done,
  3745. msecs_to_jiffies(10000));
  3746. if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
  3747. pr_err(MPT3SAS_FMT "%s: timeout\n",
  3748. ioc->name, __func__);
  3749. _debug_dump_mf(mpi_request,
  3750. sizeof(Mpi2SepRequest_t)/4);
  3751. if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
  3752. issue_reset = false;
  3753. goto issue_host_reset;
  3754. }
  3755. if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
  3756. memcpy(mpi_reply, ioc->base_cmds.reply,
  3757. sizeof(Mpi2SepReply_t));
  3758. else
  3759. memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
  3760. ioc->base_cmds.status = MPT3_CMD_NOT_USED;
  3761. goto out;
  3762. issue_host_reset:
  3763. if (issue_reset)
  3764. mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
  3765. ioc->base_cmds.status = MPT3_CMD_NOT_USED;
  3766. rc = -EFAULT;
  3767. out:
  3768. mutex_unlock(&ioc->base_cmds.mutex);
  3769. return rc;
  3770. }
  3771. /**
  3772. * _base_get_port_facts - obtain port facts reply and save in ioc
  3773. * @ioc: per adapter object
  3774. *
  3775. * Returns 0 for success, non-zero for failure.
  3776. */
  3777. static int
  3778. _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port)
  3779. {
  3780. Mpi2PortFactsRequest_t mpi_request;
  3781. Mpi2PortFactsReply_t mpi_reply;
  3782. struct mpt3sas_port_facts *pfacts;
  3783. int mpi_reply_sz, mpi_request_sz, r;
  3784. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3785. __func__));
  3786. mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
  3787. mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
  3788. memset(&mpi_request, 0, mpi_request_sz);
  3789. mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
  3790. mpi_request.PortNumber = port;
  3791. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  3792. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
  3793. if (r != 0) {
  3794. pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
  3795. ioc->name, __func__, r);
  3796. return r;
  3797. }
  3798. pfacts = &ioc->pfacts[port];
  3799. memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
  3800. pfacts->PortNumber = mpi_reply.PortNumber;
  3801. pfacts->VP_ID = mpi_reply.VP_ID;
  3802. pfacts->VF_ID = mpi_reply.VF_ID;
  3803. pfacts->MaxPostedCmdBuffers =
  3804. le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
  3805. return 0;
  3806. }
  3807. /**
  3808. * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
  3809. * @ioc: per adapter object
  3810. * @timeout:
  3811. *
  3812. * Returns 0 for success, non-zero for failure.
  3813. */
  3814. static int
  3815. _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout)
  3816. {
  3817. u32 ioc_state;
  3818. int rc;
  3819. dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
  3820. __func__));
  3821. if (ioc->pci_error_recovery) {
  3822. dfailprintk(ioc, printk(MPT3SAS_FMT
  3823. "%s: host in pci error recovery\n", ioc->name, __func__));
  3824. return -EFAULT;
  3825. }
  3826. ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
  3827. dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
  3828. ioc->name, __func__, ioc_state));
  3829. if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
  3830. (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
  3831. return 0;
  3832. if (ioc_state & MPI2_DOORBELL_USED) {
  3833. dhsprintk(ioc, printk(MPT3SAS_FMT
  3834. "unexpected doorbell active!\n", ioc->name));
  3835. goto issue_diag_reset;
  3836. }
  3837. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
  3838. mpt3sas_base_fault_info(ioc, ioc_state &
  3839. MPI2_DOORBELL_DATA_MASK);
  3840. goto issue_diag_reset;
  3841. }
  3842. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
  3843. if (ioc_state) {
  3844. dfailprintk(ioc, printk(MPT3SAS_FMT
  3845. "%s: failed going to ready state (ioc_state=0x%x)\n",
  3846. ioc->name, __func__, ioc_state));
  3847. return -EFAULT;
  3848. }
  3849. issue_diag_reset:
  3850. rc = _base_diag_reset(ioc);
  3851. return rc;
  3852. }
  3853. /**
  3854. * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
  3855. * @ioc: per adapter object
  3856. *
  3857. * Returns 0 for success, non-zero for failure.
  3858. */
  3859. static int
  3860. _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc)
  3861. {
  3862. Mpi2IOCFactsRequest_t mpi_request;
  3863. Mpi2IOCFactsReply_t mpi_reply;
  3864. struct mpt3sas_facts *facts;
  3865. int mpi_reply_sz, mpi_request_sz, r;
  3866. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3867. __func__));
  3868. r = _base_wait_for_iocstate(ioc, 10);
  3869. if (r) {
  3870. dfailprintk(ioc, printk(MPT3SAS_FMT
  3871. "%s: failed getting to correct state\n",
  3872. ioc->name, __func__));
  3873. return r;
  3874. }
  3875. mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
  3876. mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
  3877. memset(&mpi_request, 0, mpi_request_sz);
  3878. mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
  3879. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  3880. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
  3881. if (r != 0) {
  3882. pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
  3883. ioc->name, __func__, r);
  3884. return r;
  3885. }
  3886. facts = &ioc->facts;
  3887. memset(facts, 0, sizeof(struct mpt3sas_facts));
  3888. facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
  3889. facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
  3890. facts->VP_ID = mpi_reply.VP_ID;
  3891. facts->VF_ID = mpi_reply.VF_ID;
  3892. facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
  3893. facts->MaxChainDepth = mpi_reply.MaxChainDepth;
  3894. facts->WhoInit = mpi_reply.WhoInit;
  3895. facts->NumberOfPorts = mpi_reply.NumberOfPorts;
  3896. facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
  3897. facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
  3898. facts->MaxReplyDescriptorPostQueueDepth =
  3899. le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
  3900. facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
  3901. facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
  3902. if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
  3903. ioc->ir_firmware = 1;
  3904. if ((facts->IOCCapabilities &
  3905. MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
  3906. ioc->rdpq_array_capable = 1;
  3907. facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
  3908. facts->IOCRequestFrameSize =
  3909. le16_to_cpu(mpi_reply.IOCRequestFrameSize);
  3910. if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
  3911. facts->IOCMaxChainSegmentSize =
  3912. le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
  3913. }
  3914. facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
  3915. facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
  3916. ioc->shost->max_id = -1;
  3917. facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
  3918. facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
  3919. facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
  3920. facts->HighPriorityCredit =
  3921. le16_to_cpu(mpi_reply.HighPriorityCredit);
  3922. facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
  3923. facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
  3924. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3925. "hba queue depth(%d), max chains per io(%d)\n",
  3926. ioc->name, facts->RequestCredit,
  3927. facts->MaxChainDepth));
  3928. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3929. "request frame size(%d), reply frame size(%d)\n", ioc->name,
  3930. facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
  3931. return 0;
  3932. }
  3933. /**
  3934. * _base_send_ioc_init - send ioc_init to firmware
  3935. * @ioc: per adapter object
  3936. *
  3937. * Returns 0 for success, non-zero for failure.
  3938. */
  3939. static int
  3940. _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc)
  3941. {
  3942. Mpi2IOCInitRequest_t mpi_request;
  3943. Mpi2IOCInitReply_t mpi_reply;
  3944. int i, r = 0;
  3945. ktime_t current_time;
  3946. u16 ioc_status;
  3947. u32 reply_post_free_array_sz = 0;
  3948. Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
  3949. dma_addr_t reply_post_free_array_dma;
  3950. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3951. __func__));
  3952. memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
  3953. mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
  3954. mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
  3955. mpi_request.VF_ID = 0; /* TODO */
  3956. mpi_request.VP_ID = 0;
  3957. mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
  3958. mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
  3959. if (_base_is_controller_msix_enabled(ioc))
  3960. mpi_request.HostMSIxVectors = ioc->reply_queue_count;
  3961. mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
  3962. mpi_request.ReplyDescriptorPostQueueDepth =
  3963. cpu_to_le16(ioc->reply_post_queue_depth);
  3964. mpi_request.ReplyFreeQueueDepth =
  3965. cpu_to_le16(ioc->reply_free_queue_depth);
  3966. mpi_request.SenseBufferAddressHigh =
  3967. cpu_to_le32((u64)ioc->sense_dma >> 32);
  3968. mpi_request.SystemReplyAddressHigh =
  3969. cpu_to_le32((u64)ioc->reply_dma >> 32);
  3970. mpi_request.SystemRequestFrameBaseAddress =
  3971. cpu_to_le64((u64)ioc->request_dma);
  3972. mpi_request.ReplyFreeQueueAddress =
  3973. cpu_to_le64((u64)ioc->reply_free_dma);
  3974. if (ioc->rdpq_array_enable) {
  3975. reply_post_free_array_sz = ioc->reply_queue_count *
  3976. sizeof(Mpi2IOCInitRDPQArrayEntry);
  3977. reply_post_free_array = pci_alloc_consistent(ioc->pdev,
  3978. reply_post_free_array_sz, &reply_post_free_array_dma);
  3979. if (!reply_post_free_array) {
  3980. pr_err(MPT3SAS_FMT
  3981. "reply_post_free_array: pci_alloc_consistent failed\n",
  3982. ioc->name);
  3983. r = -ENOMEM;
  3984. goto out;
  3985. }
  3986. memset(reply_post_free_array, 0, reply_post_free_array_sz);
  3987. for (i = 0; i < ioc->reply_queue_count; i++)
  3988. reply_post_free_array[i].RDPQBaseAddress =
  3989. cpu_to_le64(
  3990. (u64)ioc->reply_post[i].reply_post_free_dma);
  3991. mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
  3992. mpi_request.ReplyDescriptorPostQueueAddress =
  3993. cpu_to_le64((u64)reply_post_free_array_dma);
  3994. } else {
  3995. mpi_request.ReplyDescriptorPostQueueAddress =
  3996. cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
  3997. }
  3998. /* This time stamp specifies number of milliseconds
  3999. * since epoch ~ midnight January 1, 1970.
  4000. */
  4001. current_time = ktime_get_real();
  4002. mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time));
  4003. if (ioc->logging_level & MPT_DEBUG_INIT) {
  4004. __le32 *mfp;
  4005. int i;
  4006. mfp = (__le32 *)&mpi_request;
  4007. pr_info("\toffset:data\n");
  4008. for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
  4009. pr_info("\t[0x%02x]:%08x\n", i*4,
  4010. le32_to_cpu(mfp[i]));
  4011. }
  4012. r = _base_handshake_req_reply_wait(ioc,
  4013. sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
  4014. sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10);
  4015. if (r != 0) {
  4016. pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
  4017. ioc->name, __func__, r);
  4018. goto out;
  4019. }
  4020. ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
  4021. if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
  4022. mpi_reply.IOCLogInfo) {
  4023. pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
  4024. r = -EIO;
  4025. }
  4026. out:
  4027. if (reply_post_free_array)
  4028. pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
  4029. reply_post_free_array,
  4030. reply_post_free_array_dma);
  4031. return r;
  4032. }
  4033. /**
  4034. * mpt3sas_port_enable_done - command completion routine for port enable
  4035. * @ioc: per adapter object
  4036. * @smid: system request message index
  4037. * @msix_index: MSIX table index supplied by the OS
  4038. * @reply: reply message frame(lower 32bit addr)
  4039. *
  4040. * Return 1 meaning mf should be freed from _base_interrupt
  4041. * 0 means the mf is freed from this function.
  4042. */
  4043. u8
  4044. mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  4045. u32 reply)
  4046. {
  4047. MPI2DefaultReply_t *mpi_reply;
  4048. u16 ioc_status;
  4049. if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
  4050. return 1;
  4051. mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
  4052. if (!mpi_reply)
  4053. return 1;
  4054. if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
  4055. return 1;
  4056. ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
  4057. ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
  4058. ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
  4059. memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
  4060. ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
  4061. if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
  4062. ioc->port_enable_failed = 1;
  4063. if (ioc->is_driver_loading) {
  4064. if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
  4065. mpt3sas_port_enable_complete(ioc);
  4066. return 1;
  4067. } else {
  4068. ioc->start_scan_failed = ioc_status;
  4069. ioc->start_scan = 0;
  4070. return 1;
  4071. }
  4072. }
  4073. complete(&ioc->port_enable_cmds.done);
  4074. return 1;
  4075. }
  4076. /**
  4077. * _base_send_port_enable - send port_enable(discovery stuff) to firmware
  4078. * @ioc: per adapter object
  4079. *
  4080. * Returns 0 for success, non-zero for failure.
  4081. */
  4082. static int
  4083. _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc)
  4084. {
  4085. Mpi2PortEnableRequest_t *mpi_request;
  4086. Mpi2PortEnableReply_t *mpi_reply;
  4087. int r = 0;
  4088. u16 smid;
  4089. u16 ioc_status;
  4090. pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
  4091. if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
  4092. pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
  4093. ioc->name, __func__);
  4094. return -EAGAIN;
  4095. }
  4096. smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
  4097. if (!smid) {
  4098. pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
  4099. ioc->name, __func__);
  4100. return -EAGAIN;
  4101. }
  4102. ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
  4103. mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
  4104. ioc->port_enable_cmds.smid = smid;
  4105. memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
  4106. mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
  4107. init_completion(&ioc->port_enable_cmds.done);
  4108. mpt3sas_base_put_smid_default(ioc, smid);
  4109. wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ);
  4110. if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
  4111. pr_err(MPT3SAS_FMT "%s: timeout\n",
  4112. ioc->name, __func__);
  4113. _debug_dump_mf(mpi_request,
  4114. sizeof(Mpi2PortEnableRequest_t)/4);
  4115. if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
  4116. r = -EFAULT;
  4117. else
  4118. r = -ETIME;
  4119. goto out;
  4120. }
  4121. mpi_reply = ioc->port_enable_cmds.reply;
  4122. ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
  4123. if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
  4124. pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
  4125. ioc->name, __func__, ioc_status);
  4126. r = -EFAULT;
  4127. goto out;
  4128. }
  4129. out:
  4130. ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
  4131. pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
  4132. "SUCCESS" : "FAILED"));
  4133. return r;
  4134. }
  4135. /**
  4136. * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
  4137. * @ioc: per adapter object
  4138. *
  4139. * Returns 0 for success, non-zero for failure.
  4140. */
  4141. int
  4142. mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
  4143. {
  4144. Mpi2PortEnableRequest_t *mpi_request;
  4145. u16 smid;
  4146. pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
  4147. if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
  4148. pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
  4149. ioc->name, __func__);
  4150. return -EAGAIN;
  4151. }
  4152. smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
  4153. if (!smid) {
  4154. pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
  4155. ioc->name, __func__);
  4156. return -EAGAIN;
  4157. }
  4158. ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
  4159. mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
  4160. ioc->port_enable_cmds.smid = smid;
  4161. memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
  4162. mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
  4163. mpt3sas_base_put_smid_default(ioc, smid);
  4164. return 0;
  4165. }
  4166. /**
  4167. * _base_determine_wait_on_discovery - desposition
  4168. * @ioc: per adapter object
  4169. *
  4170. * Decide whether to wait on discovery to complete. Used to either
  4171. * locate boot device, or report volumes ahead of physical devices.
  4172. *
  4173. * Returns 1 for wait, 0 for don't wait
  4174. */
  4175. static int
  4176. _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
  4177. {
  4178. /* We wait for discovery to complete if IR firmware is loaded.
  4179. * The sas topology events arrive before PD events, so we need time to
  4180. * turn on the bit in ioc->pd_handles to indicate PD
  4181. * Also, it maybe required to report Volumes ahead of physical
  4182. * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
  4183. */
  4184. if (ioc->ir_firmware)
  4185. return 1;
  4186. /* if no Bios, then we don't need to wait */
  4187. if (!ioc->bios_pg3.BiosVersion)
  4188. return 0;
  4189. /* Bios is present, then we drop down here.
  4190. *
  4191. * If there any entries in the Bios Page 2, then we wait
  4192. * for discovery to complete.
  4193. */
  4194. /* Current Boot Device */
  4195. if ((ioc->bios_pg2.CurrentBootDeviceForm &
  4196. MPI2_BIOSPAGE2_FORM_MASK) ==
  4197. MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
  4198. /* Request Boot Device */
  4199. (ioc->bios_pg2.ReqBootDeviceForm &
  4200. MPI2_BIOSPAGE2_FORM_MASK) ==
  4201. MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
  4202. /* Alternate Request Boot Device */
  4203. (ioc->bios_pg2.ReqAltBootDeviceForm &
  4204. MPI2_BIOSPAGE2_FORM_MASK) ==
  4205. MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
  4206. return 0;
  4207. return 1;
  4208. }
  4209. /**
  4210. * _base_unmask_events - turn on notification for this event
  4211. * @ioc: per adapter object
  4212. * @event: firmware event
  4213. *
  4214. * The mask is stored in ioc->event_masks.
  4215. */
  4216. static void
  4217. _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
  4218. {
  4219. u32 desired_event;
  4220. if (event >= 128)
  4221. return;
  4222. desired_event = (1 << (event % 32));
  4223. if (event < 32)
  4224. ioc->event_masks[0] &= ~desired_event;
  4225. else if (event < 64)
  4226. ioc->event_masks[1] &= ~desired_event;
  4227. else if (event < 96)
  4228. ioc->event_masks[2] &= ~desired_event;
  4229. else if (event < 128)
  4230. ioc->event_masks[3] &= ~desired_event;
  4231. }
  4232. /**
  4233. * _base_event_notification - send event notification
  4234. * @ioc: per adapter object
  4235. *
  4236. * Returns 0 for success, non-zero for failure.
  4237. */
  4238. static int
  4239. _base_event_notification(struct MPT3SAS_ADAPTER *ioc)
  4240. {
  4241. Mpi2EventNotificationRequest_t *mpi_request;
  4242. u16 smid;
  4243. int r = 0;
  4244. int i;
  4245. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  4246. __func__));
  4247. if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
  4248. pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
  4249. ioc->name, __func__);
  4250. return -EAGAIN;
  4251. }
  4252. smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
  4253. if (!smid) {
  4254. pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
  4255. ioc->name, __func__);
  4256. return -EAGAIN;
  4257. }
  4258. ioc->base_cmds.status = MPT3_CMD_PENDING;
  4259. mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
  4260. ioc->base_cmds.smid = smid;
  4261. memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
  4262. mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
  4263. mpi_request->VF_ID = 0; /* TODO */
  4264. mpi_request->VP_ID = 0;
  4265. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  4266. mpi_request->EventMasks[i] =
  4267. cpu_to_le32(ioc->event_masks[i]);
  4268. init_completion(&ioc->base_cmds.done);
  4269. mpt3sas_base_put_smid_default(ioc, smid);
  4270. wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
  4271. if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
  4272. pr_err(MPT3SAS_FMT "%s: timeout\n",
  4273. ioc->name, __func__);
  4274. _debug_dump_mf(mpi_request,
  4275. sizeof(Mpi2EventNotificationRequest_t)/4);
  4276. if (ioc->base_cmds.status & MPT3_CMD_RESET)
  4277. r = -EFAULT;
  4278. else
  4279. r = -ETIME;
  4280. } else
  4281. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
  4282. ioc->name, __func__));
  4283. ioc->base_cmds.status = MPT3_CMD_NOT_USED;
  4284. return r;
  4285. }
  4286. /**
  4287. * mpt3sas_base_validate_event_type - validating event types
  4288. * @ioc: per adapter object
  4289. * @event: firmware event
  4290. *
  4291. * This will turn on firmware event notification when application
  4292. * ask for that event. We don't mask events that are already enabled.
  4293. */
  4294. void
  4295. mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
  4296. {
  4297. int i, j;
  4298. u32 event_mask, desired_event;
  4299. u8 send_update_to_fw;
  4300. for (i = 0, send_update_to_fw = 0; i <
  4301. MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
  4302. event_mask = ~event_type[i];
  4303. desired_event = 1;
  4304. for (j = 0; j < 32; j++) {
  4305. if (!(event_mask & desired_event) &&
  4306. (ioc->event_masks[i] & desired_event)) {
  4307. ioc->event_masks[i] &= ~desired_event;
  4308. send_update_to_fw = 1;
  4309. }
  4310. desired_event = (desired_event << 1);
  4311. }
  4312. }
  4313. if (!send_update_to_fw)
  4314. return;
  4315. mutex_lock(&ioc->base_cmds.mutex);
  4316. _base_event_notification(ioc);
  4317. mutex_unlock(&ioc->base_cmds.mutex);
  4318. }
  4319. /**
  4320. * _base_diag_reset - the "big hammer" start of day reset
  4321. * @ioc: per adapter object
  4322. *
  4323. * Returns 0 for success, non-zero for failure.
  4324. */
  4325. static int
  4326. _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
  4327. {
  4328. u32 host_diagnostic;
  4329. u32 ioc_state;
  4330. u32 count;
  4331. u32 hcb_size;
  4332. pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
  4333. drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
  4334. ioc->name));
  4335. count = 0;
  4336. do {
  4337. /* Write magic sequence to WriteSequence register
  4338. * Loop until in diagnostic mode
  4339. */
  4340. drsprintk(ioc, pr_info(MPT3SAS_FMT
  4341. "write magic sequence\n", ioc->name));
  4342. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  4343. writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
  4344. writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
  4345. writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
  4346. writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
  4347. writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
  4348. writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
  4349. /* wait 100 msec */
  4350. msleep(100);
  4351. if (count++ > 20)
  4352. goto out;
  4353. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  4354. drsprintk(ioc, pr_info(MPT3SAS_FMT
  4355. "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
  4356. ioc->name, count, host_diagnostic));
  4357. } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
  4358. hcb_size = readl(&ioc->chip->HCBSize);
  4359. drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
  4360. ioc->name));
  4361. writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
  4362. &ioc->chip->HostDiagnostic);
  4363. /*This delay allows the chip PCIe hardware time to finish reset tasks*/
  4364. msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
  4365. /* Approximately 300 second max wait */
  4366. for (count = 0; count < (300000000 /
  4367. MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
  4368. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  4369. if (host_diagnostic == 0xFFFFFFFF)
  4370. goto out;
  4371. if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
  4372. break;
  4373. msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
  4374. }
  4375. if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
  4376. drsprintk(ioc, pr_info(MPT3SAS_FMT
  4377. "restart the adapter assuming the HCB Address points to good F/W\n",
  4378. ioc->name));
  4379. host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
  4380. host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
  4381. writel(host_diagnostic, &ioc->chip->HostDiagnostic);
  4382. drsprintk(ioc, pr_info(MPT3SAS_FMT
  4383. "re-enable the HCDW\n", ioc->name));
  4384. writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
  4385. &ioc->chip->HCBSize);
  4386. }
  4387. drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
  4388. ioc->name));
  4389. writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
  4390. &ioc->chip->HostDiagnostic);
  4391. drsprintk(ioc, pr_info(MPT3SAS_FMT
  4392. "disable writes to the diagnostic register\n", ioc->name));
  4393. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  4394. drsprintk(ioc, pr_info(MPT3SAS_FMT
  4395. "Wait for FW to go to the READY state\n", ioc->name));
  4396. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
  4397. if (ioc_state) {
  4398. pr_err(MPT3SAS_FMT
  4399. "%s: failed going to ready state (ioc_state=0x%x)\n",
  4400. ioc->name, __func__, ioc_state);
  4401. goto out;
  4402. }
  4403. pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
  4404. return 0;
  4405. out:
  4406. pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
  4407. return -EFAULT;
  4408. }
  4409. /**
  4410. * _base_make_ioc_ready - put controller in READY state
  4411. * @ioc: per adapter object
  4412. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  4413. *
  4414. * Returns 0 for success, non-zero for failure.
  4415. */
  4416. static int
  4417. _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)
  4418. {
  4419. u32 ioc_state;
  4420. int rc;
  4421. int count;
  4422. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  4423. __func__));
  4424. if (ioc->pci_error_recovery)
  4425. return 0;
  4426. ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
  4427. dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
  4428. ioc->name, __func__, ioc_state));
  4429. /* if in RESET state, it should move to READY state shortly */
  4430. count = 0;
  4431. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
  4432. while ((ioc_state & MPI2_IOC_STATE_MASK) !=
  4433. MPI2_IOC_STATE_READY) {
  4434. if (count++ == 10) {
  4435. pr_err(MPT3SAS_FMT
  4436. "%s: failed going to ready state (ioc_state=0x%x)\n",
  4437. ioc->name, __func__, ioc_state);
  4438. return -EFAULT;
  4439. }
  4440. ssleep(1);
  4441. ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
  4442. }
  4443. }
  4444. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
  4445. return 0;
  4446. if (ioc_state & MPI2_DOORBELL_USED) {
  4447. dhsprintk(ioc, pr_info(MPT3SAS_FMT
  4448. "unexpected doorbell active!\n",
  4449. ioc->name));
  4450. goto issue_diag_reset;
  4451. }
  4452. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
  4453. mpt3sas_base_fault_info(ioc, ioc_state &
  4454. MPI2_DOORBELL_DATA_MASK);
  4455. goto issue_diag_reset;
  4456. }
  4457. if (type == FORCE_BIG_HAMMER)
  4458. goto issue_diag_reset;
  4459. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
  4460. if (!(_base_send_ioc_reset(ioc,
  4461. MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) {
  4462. return 0;
  4463. }
  4464. issue_diag_reset:
  4465. rc = _base_diag_reset(ioc);
  4466. return rc;
  4467. }
  4468. /**
  4469. * _base_make_ioc_operational - put controller in OPERATIONAL state
  4470. * @ioc: per adapter object
  4471. *
  4472. * Returns 0 for success, non-zero for failure.
  4473. */
  4474. static int
  4475. _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
  4476. {
  4477. int r, i, index;
  4478. unsigned long flags;
  4479. u32 reply_address;
  4480. u16 smid;
  4481. struct _tr_list *delayed_tr, *delayed_tr_next;
  4482. struct _sc_list *delayed_sc, *delayed_sc_next;
  4483. struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
  4484. u8 hide_flag;
  4485. struct adapter_reply_queue *reply_q;
  4486. Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
  4487. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  4488. __func__));
  4489. /* clean the delayed target reset list */
  4490. list_for_each_entry_safe(delayed_tr, delayed_tr_next,
  4491. &ioc->delayed_tr_list, list) {
  4492. list_del(&delayed_tr->list);
  4493. kfree(delayed_tr);
  4494. }
  4495. list_for_each_entry_safe(delayed_tr, delayed_tr_next,
  4496. &ioc->delayed_tr_volume_list, list) {
  4497. list_del(&delayed_tr->list);
  4498. kfree(delayed_tr);
  4499. }
  4500. list_for_each_entry_safe(delayed_sc, delayed_sc_next,
  4501. &ioc->delayed_sc_list, list) {
  4502. list_del(&delayed_sc->list);
  4503. kfree(delayed_sc);
  4504. }
  4505. list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
  4506. &ioc->delayed_event_ack_list, list) {
  4507. list_del(&delayed_event_ack->list);
  4508. kfree(delayed_event_ack);
  4509. }
  4510. /* initialize the scsi lookup free list */
  4511. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  4512. INIT_LIST_HEAD(&ioc->free_list);
  4513. smid = 1;
  4514. for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
  4515. INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
  4516. ioc->scsi_lookup[i].cb_idx = 0xFF;
  4517. ioc->scsi_lookup[i].smid = smid;
  4518. ioc->scsi_lookup[i].scmd = NULL;
  4519. ioc->scsi_lookup[i].direct_io = 0;
  4520. list_add_tail(&ioc->scsi_lookup[i].tracker_list,
  4521. &ioc->free_list);
  4522. }
  4523. /* hi-priority queue */
  4524. INIT_LIST_HEAD(&ioc->hpr_free_list);
  4525. smid = ioc->hi_priority_smid;
  4526. for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
  4527. ioc->hpr_lookup[i].cb_idx = 0xFF;
  4528. ioc->hpr_lookup[i].smid = smid;
  4529. list_add_tail(&ioc->hpr_lookup[i].tracker_list,
  4530. &ioc->hpr_free_list);
  4531. }
  4532. /* internal queue */
  4533. INIT_LIST_HEAD(&ioc->internal_free_list);
  4534. smid = ioc->internal_smid;
  4535. for (i = 0; i < ioc->internal_depth; i++, smid++) {
  4536. ioc->internal_lookup[i].cb_idx = 0xFF;
  4537. ioc->internal_lookup[i].smid = smid;
  4538. list_add_tail(&ioc->internal_lookup[i].tracker_list,
  4539. &ioc->internal_free_list);
  4540. }
  4541. /* chain pool */
  4542. INIT_LIST_HEAD(&ioc->free_chain_list);
  4543. for (i = 0; i < ioc->chain_depth; i++)
  4544. list_add_tail(&ioc->chain_lookup[i].tracker_list,
  4545. &ioc->free_chain_list);
  4546. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  4547. /* initialize Reply Free Queue */
  4548. for (i = 0, reply_address = (u32)ioc->reply_dma ;
  4549. i < ioc->reply_free_queue_depth ; i++, reply_address +=
  4550. ioc->reply_sz)
  4551. ioc->reply_free[i] = cpu_to_le32(reply_address);
  4552. /* initialize reply queues */
  4553. if (ioc->is_driver_loading)
  4554. _base_assign_reply_queues(ioc);
  4555. /* initialize Reply Post Free Queue */
  4556. index = 0;
  4557. reply_post_free_contig = ioc->reply_post[0].reply_post_free;
  4558. list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
  4559. /*
  4560. * If RDPQ is enabled, switch to the next allocation.
  4561. * Otherwise advance within the contiguous region.
  4562. */
  4563. if (ioc->rdpq_array_enable) {
  4564. reply_q->reply_post_free =
  4565. ioc->reply_post[index++].reply_post_free;
  4566. } else {
  4567. reply_q->reply_post_free = reply_post_free_contig;
  4568. reply_post_free_contig += ioc->reply_post_queue_depth;
  4569. }
  4570. reply_q->reply_post_host_index = 0;
  4571. for (i = 0; i < ioc->reply_post_queue_depth; i++)
  4572. reply_q->reply_post_free[i].Words =
  4573. cpu_to_le64(ULLONG_MAX);
  4574. if (!_base_is_controller_msix_enabled(ioc))
  4575. goto skip_init_reply_post_free_queue;
  4576. }
  4577. skip_init_reply_post_free_queue:
  4578. r = _base_send_ioc_init(ioc);
  4579. if (r)
  4580. return r;
  4581. /* initialize reply free host index */
  4582. ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
  4583. writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
  4584. /* initialize reply post host index */
  4585. list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
  4586. if (ioc->msix96_vector)
  4587. writel((reply_q->msix_index & 7)<<
  4588. MPI2_RPHI_MSIX_INDEX_SHIFT,
  4589. ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
  4590. else
  4591. writel(reply_q->msix_index <<
  4592. MPI2_RPHI_MSIX_INDEX_SHIFT,
  4593. &ioc->chip->ReplyPostHostIndex);
  4594. if (!_base_is_controller_msix_enabled(ioc))
  4595. goto skip_init_reply_post_host_index;
  4596. }
  4597. skip_init_reply_post_host_index:
  4598. _base_unmask_interrupts(ioc);
  4599. r = _base_event_notification(ioc);
  4600. if (r)
  4601. return r;
  4602. _base_static_config_pages(ioc);
  4603. if (ioc->is_driver_loading) {
  4604. if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
  4605. == 0x80) {
  4606. hide_flag = (u8) (
  4607. le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
  4608. MFG_PAGE10_HIDE_SSDS_MASK);
  4609. if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
  4610. ioc->mfg_pg10_hide_flag = hide_flag;
  4611. }
  4612. ioc->wait_for_discovery_to_complete =
  4613. _base_determine_wait_on_discovery(ioc);
  4614. return r; /* scan_start and scan_finished support */
  4615. }
  4616. r = _base_send_port_enable(ioc);
  4617. if (r)
  4618. return r;
  4619. return r;
  4620. }
  4621. /**
  4622. * mpt3sas_base_free_resources - free resources controller resources
  4623. * @ioc: per adapter object
  4624. *
  4625. * Return nothing.
  4626. */
  4627. void
  4628. mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
  4629. {
  4630. dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  4631. __func__));
  4632. /* synchronizing freeing resource with pci_access_mutex lock */
  4633. mutex_lock(&ioc->pci_access_mutex);
  4634. if (ioc->chip_phys && ioc->chip) {
  4635. _base_mask_interrupts(ioc);
  4636. ioc->shost_recovery = 1;
  4637. _base_make_ioc_ready(ioc, SOFT_RESET);
  4638. ioc->shost_recovery = 0;
  4639. }
  4640. mpt3sas_base_unmap_resources(ioc);
  4641. mutex_unlock(&ioc->pci_access_mutex);
  4642. return;
  4643. }
  4644. /**
  4645. * mpt3sas_base_attach - attach controller instance
  4646. * @ioc: per adapter object
  4647. *
  4648. * Returns 0 for success, non-zero for failure.
  4649. */
  4650. int
  4651. mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
  4652. {
  4653. int r, i;
  4654. int cpu_id, last_cpu_id = 0;
  4655. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  4656. __func__));
  4657. /* setup cpu_msix_table */
  4658. ioc->cpu_count = num_online_cpus();
  4659. for_each_online_cpu(cpu_id)
  4660. last_cpu_id = cpu_id;
  4661. ioc->cpu_msix_table_sz = last_cpu_id + 1;
  4662. ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
  4663. ioc->reply_queue_count = 1;
  4664. if (!ioc->cpu_msix_table) {
  4665. dfailprintk(ioc, pr_info(MPT3SAS_FMT
  4666. "allocation for cpu_msix_table failed!!!\n",
  4667. ioc->name));
  4668. r = -ENOMEM;
  4669. goto out_free_resources;
  4670. }
  4671. if (ioc->is_warpdrive) {
  4672. ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
  4673. sizeof(resource_size_t *), GFP_KERNEL);
  4674. if (!ioc->reply_post_host_index) {
  4675. dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation "
  4676. "for cpu_msix_table failed!!!\n", ioc->name));
  4677. r = -ENOMEM;
  4678. goto out_free_resources;
  4679. }
  4680. }
  4681. ioc->rdpq_array_enable_assigned = 0;
  4682. ioc->dma_mask = 0;
  4683. r = mpt3sas_base_map_resources(ioc);
  4684. if (r)
  4685. goto out_free_resources;
  4686. pci_set_drvdata(ioc->pdev, ioc->shost);
  4687. r = _base_get_ioc_facts(ioc);
  4688. if (r)
  4689. goto out_free_resources;
  4690. switch (ioc->hba_mpi_version_belonged) {
  4691. case MPI2_VERSION:
  4692. ioc->build_sg_scmd = &_base_build_sg_scmd;
  4693. ioc->build_sg = &_base_build_sg;
  4694. ioc->build_zero_len_sge = &_base_build_zero_len_sge;
  4695. break;
  4696. case MPI25_VERSION:
  4697. case MPI26_VERSION:
  4698. /*
  4699. * In SAS3.0,
  4700. * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
  4701. * Target Status - all require the IEEE formated scatter gather
  4702. * elements.
  4703. */
  4704. ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
  4705. ioc->build_sg = &_base_build_sg_ieee;
  4706. ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
  4707. ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
  4708. break;
  4709. }
  4710. /*
  4711. * These function pointers for other requests that don't
  4712. * the require IEEE scatter gather elements.
  4713. *
  4714. * For example Configuration Pages and SAS IOUNIT Control don't.
  4715. */
  4716. ioc->build_sg_mpi = &_base_build_sg;
  4717. ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
  4718. r = _base_make_ioc_ready(ioc, SOFT_RESET);
  4719. if (r)
  4720. goto out_free_resources;
  4721. ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
  4722. sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
  4723. if (!ioc->pfacts) {
  4724. r = -ENOMEM;
  4725. goto out_free_resources;
  4726. }
  4727. for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
  4728. r = _base_get_port_facts(ioc, i);
  4729. if (r)
  4730. goto out_free_resources;
  4731. }
  4732. r = _base_allocate_memory_pools(ioc);
  4733. if (r)
  4734. goto out_free_resources;
  4735. init_waitqueue_head(&ioc->reset_wq);
  4736. /* allocate memory pd handle bitmask list */
  4737. ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
  4738. if (ioc->facts.MaxDevHandle % 8)
  4739. ioc->pd_handles_sz++;
  4740. ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
  4741. GFP_KERNEL);
  4742. if (!ioc->pd_handles) {
  4743. r = -ENOMEM;
  4744. goto out_free_resources;
  4745. }
  4746. ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
  4747. GFP_KERNEL);
  4748. if (!ioc->blocking_handles) {
  4749. r = -ENOMEM;
  4750. goto out_free_resources;
  4751. }
  4752. ioc->fwfault_debug = mpt3sas_fwfault_debug;
  4753. /* base internal command bits */
  4754. mutex_init(&ioc->base_cmds.mutex);
  4755. ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4756. ioc->base_cmds.status = MPT3_CMD_NOT_USED;
  4757. /* port_enable command bits */
  4758. ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4759. ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
  4760. /* transport internal command bits */
  4761. ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4762. ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
  4763. mutex_init(&ioc->transport_cmds.mutex);
  4764. /* scsih internal command bits */
  4765. ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4766. ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
  4767. mutex_init(&ioc->scsih_cmds.mutex);
  4768. /* task management internal command bits */
  4769. ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4770. ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
  4771. mutex_init(&ioc->tm_cmds.mutex);
  4772. /* config page internal command bits */
  4773. ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4774. ioc->config_cmds.status = MPT3_CMD_NOT_USED;
  4775. mutex_init(&ioc->config_cmds.mutex);
  4776. /* ctl module internal command bits */
  4777. ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4778. ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  4779. ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
  4780. mutex_init(&ioc->ctl_cmds.mutex);
  4781. if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
  4782. !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
  4783. !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
  4784. !ioc->ctl_cmds.sense) {
  4785. r = -ENOMEM;
  4786. goto out_free_resources;
  4787. }
  4788. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  4789. ioc->event_masks[i] = -1;
  4790. /* here we enable the events we care about */
  4791. _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
  4792. _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
  4793. _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
  4794. _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
  4795. _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
  4796. _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
  4797. _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
  4798. _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
  4799. _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
  4800. _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
  4801. _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
  4802. if (ioc->hba_mpi_version_belonged == MPI26_VERSION)
  4803. _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION);
  4804. r = _base_make_ioc_operational(ioc);
  4805. if (r)
  4806. goto out_free_resources;
  4807. ioc->non_operational_loop = 0;
  4808. return 0;
  4809. out_free_resources:
  4810. ioc->remove_host = 1;
  4811. mpt3sas_base_free_resources(ioc);
  4812. _base_release_memory_pools(ioc);
  4813. pci_set_drvdata(ioc->pdev, NULL);
  4814. kfree(ioc->cpu_msix_table);
  4815. if (ioc->is_warpdrive)
  4816. kfree(ioc->reply_post_host_index);
  4817. kfree(ioc->pd_handles);
  4818. kfree(ioc->blocking_handles);
  4819. kfree(ioc->tm_cmds.reply);
  4820. kfree(ioc->transport_cmds.reply);
  4821. kfree(ioc->scsih_cmds.reply);
  4822. kfree(ioc->config_cmds.reply);
  4823. kfree(ioc->base_cmds.reply);
  4824. kfree(ioc->port_enable_cmds.reply);
  4825. kfree(ioc->ctl_cmds.reply);
  4826. kfree(ioc->ctl_cmds.sense);
  4827. kfree(ioc->pfacts);
  4828. ioc->ctl_cmds.reply = NULL;
  4829. ioc->base_cmds.reply = NULL;
  4830. ioc->tm_cmds.reply = NULL;
  4831. ioc->scsih_cmds.reply = NULL;
  4832. ioc->transport_cmds.reply = NULL;
  4833. ioc->config_cmds.reply = NULL;
  4834. ioc->pfacts = NULL;
  4835. return r;
  4836. }
  4837. /**
  4838. * mpt3sas_base_detach - remove controller instance
  4839. * @ioc: per adapter object
  4840. *
  4841. * Return nothing.
  4842. */
  4843. void
  4844. mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
  4845. {
  4846. dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  4847. __func__));
  4848. mpt3sas_base_stop_watchdog(ioc);
  4849. mpt3sas_base_free_resources(ioc);
  4850. _base_release_memory_pools(ioc);
  4851. pci_set_drvdata(ioc->pdev, NULL);
  4852. kfree(ioc->cpu_msix_table);
  4853. if (ioc->is_warpdrive)
  4854. kfree(ioc->reply_post_host_index);
  4855. kfree(ioc->pd_handles);
  4856. kfree(ioc->blocking_handles);
  4857. kfree(ioc->pfacts);
  4858. kfree(ioc->ctl_cmds.reply);
  4859. kfree(ioc->ctl_cmds.sense);
  4860. kfree(ioc->base_cmds.reply);
  4861. kfree(ioc->port_enable_cmds.reply);
  4862. kfree(ioc->tm_cmds.reply);
  4863. kfree(ioc->transport_cmds.reply);
  4864. kfree(ioc->scsih_cmds.reply);
  4865. kfree(ioc->config_cmds.reply);
  4866. }
  4867. /**
  4868. * _base_reset_handler - reset callback handler (for base)
  4869. * @ioc: per adapter object
  4870. * @reset_phase: phase
  4871. *
  4872. * The handler for doing any required cleanup or initialization.
  4873. *
  4874. * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
  4875. * MPT3_IOC_DONE_RESET
  4876. *
  4877. * Return nothing.
  4878. */
  4879. static void
  4880. _base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
  4881. {
  4882. mpt3sas_scsih_reset_handler(ioc, reset_phase);
  4883. mpt3sas_ctl_reset_handler(ioc, reset_phase);
  4884. switch (reset_phase) {
  4885. case MPT3_IOC_PRE_RESET:
  4886. dtmprintk(ioc, pr_info(MPT3SAS_FMT
  4887. "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
  4888. break;
  4889. case MPT3_IOC_AFTER_RESET:
  4890. dtmprintk(ioc, pr_info(MPT3SAS_FMT
  4891. "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
  4892. if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
  4893. ioc->transport_cmds.status |= MPT3_CMD_RESET;
  4894. mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
  4895. complete(&ioc->transport_cmds.done);
  4896. }
  4897. if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
  4898. ioc->base_cmds.status |= MPT3_CMD_RESET;
  4899. mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
  4900. complete(&ioc->base_cmds.done);
  4901. }
  4902. if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
  4903. ioc->port_enable_failed = 1;
  4904. ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
  4905. mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
  4906. if (ioc->is_driver_loading) {
  4907. ioc->start_scan_failed =
  4908. MPI2_IOCSTATUS_INTERNAL_ERROR;
  4909. ioc->start_scan = 0;
  4910. ioc->port_enable_cmds.status =
  4911. MPT3_CMD_NOT_USED;
  4912. } else
  4913. complete(&ioc->port_enable_cmds.done);
  4914. }
  4915. if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
  4916. ioc->config_cmds.status |= MPT3_CMD_RESET;
  4917. mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
  4918. ioc->config_cmds.smid = USHRT_MAX;
  4919. complete(&ioc->config_cmds.done);
  4920. }
  4921. break;
  4922. case MPT3_IOC_DONE_RESET:
  4923. dtmprintk(ioc, pr_info(MPT3SAS_FMT
  4924. "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
  4925. break;
  4926. }
  4927. }
  4928. /**
  4929. * _wait_for_commands_to_complete - reset controller
  4930. * @ioc: Pointer to MPT_ADAPTER structure
  4931. *
  4932. * This function waiting(3s) for all pending commands to complete
  4933. * prior to putting controller in reset.
  4934. */
  4935. static void
  4936. _wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc)
  4937. {
  4938. u32 ioc_state;
  4939. unsigned long flags;
  4940. u16 i;
  4941. ioc->pending_io_count = 0;
  4942. ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
  4943. if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
  4944. return;
  4945. /* pending command count */
  4946. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  4947. for (i = 0; i < ioc->scsiio_depth; i++)
  4948. if (ioc->scsi_lookup[i].cb_idx != 0xFF)
  4949. ioc->pending_io_count++;
  4950. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  4951. if (!ioc->pending_io_count)
  4952. return;
  4953. /* wait for pending commands to complete */
  4954. wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
  4955. }
  4956. /**
  4957. * mpt3sas_base_hard_reset_handler - reset controller
  4958. * @ioc: Pointer to MPT_ADAPTER structure
  4959. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  4960. *
  4961. * Returns 0 for success, non-zero for failure.
  4962. */
  4963. int
  4964. mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc,
  4965. enum reset_type type)
  4966. {
  4967. int r;
  4968. unsigned long flags;
  4969. u32 ioc_state;
  4970. u8 is_fault = 0, is_trigger = 0;
  4971. dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
  4972. __func__));
  4973. if (ioc->pci_error_recovery) {
  4974. pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
  4975. ioc->name, __func__);
  4976. r = 0;
  4977. goto out_unlocked;
  4978. }
  4979. if (mpt3sas_fwfault_debug)
  4980. mpt3sas_halt_firmware(ioc);
  4981. /* wait for an active reset in progress to complete */
  4982. if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
  4983. do {
  4984. ssleep(1);
  4985. } while (ioc->shost_recovery == 1);
  4986. dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
  4987. __func__));
  4988. return ioc->ioc_reset_in_progress_status;
  4989. }
  4990. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  4991. ioc->shost_recovery = 1;
  4992. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  4993. if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
  4994. MPT3_DIAG_BUFFER_IS_REGISTERED) &&
  4995. (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
  4996. MPT3_DIAG_BUFFER_IS_RELEASED))) {
  4997. is_trigger = 1;
  4998. ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
  4999. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  5000. is_fault = 1;
  5001. }
  5002. _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
  5003. _wait_for_commands_to_complete(ioc);
  5004. _base_mask_interrupts(ioc);
  5005. r = _base_make_ioc_ready(ioc, type);
  5006. if (r)
  5007. goto out;
  5008. _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
  5009. /* If this hard reset is called while port enable is active, then
  5010. * there is no reason to call make_ioc_operational
  5011. */
  5012. if (ioc->is_driver_loading && ioc->port_enable_failed) {
  5013. ioc->remove_host = 1;
  5014. r = -EFAULT;
  5015. goto out;
  5016. }
  5017. r = _base_get_ioc_facts(ioc);
  5018. if (r)
  5019. goto out;
  5020. if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
  5021. panic("%s: Issue occurred with flashing controller firmware."
  5022. "Please reboot the system and ensure that the correct"
  5023. " firmware version is running\n", ioc->name);
  5024. r = _base_make_ioc_operational(ioc);
  5025. if (!r)
  5026. _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
  5027. out:
  5028. dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
  5029. ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
  5030. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  5031. ioc->ioc_reset_in_progress_status = r;
  5032. ioc->shost_recovery = 0;
  5033. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  5034. ioc->ioc_reset_count++;
  5035. mutex_unlock(&ioc->reset_in_progress_mutex);
  5036. out_unlocked:
  5037. if ((r == 0) && is_trigger) {
  5038. if (is_fault)
  5039. mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
  5040. else
  5041. mpt3sas_trigger_master(ioc,
  5042. MASTER_TRIGGER_ADAPTER_RESET);
  5043. }
  5044. dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
  5045. __func__));
  5046. return r;
  5047. }