hscx_irq.c 7.1 KB

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  1. /* $Id: hscx_irq.c,v 1.18.2.3 2004/02/11 13:21:34 keil Exp $
  2. *
  3. * low level b-channel stuff for Siemens HSCX
  4. *
  5. * Author Karsten Keil
  6. * Copyright by Karsten Keil <keil@isdn4linux.de>
  7. *
  8. * This software may be used and distributed according to the terms
  9. * of the GNU General Public License, incorporated herein by reference.
  10. *
  11. * This is an include file for fast inline IRQ stuff
  12. *
  13. */
  14. static inline void
  15. waitforCEC(struct IsdnCardState *cs, int hscx)
  16. {
  17. int to = 50;
  18. while ((READHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) {
  19. udelay(1);
  20. to--;
  21. }
  22. if (!to)
  23. printk(KERN_WARNING "HiSax: waitforCEC timeout\n");
  24. }
  25. static inline void
  26. waitforXFW(struct IsdnCardState *cs, int hscx)
  27. {
  28. int to = 50;
  29. while (((READHSCX(cs, hscx, HSCX_STAR) & 0x44) != 0x40) && to) {
  30. udelay(1);
  31. to--;
  32. }
  33. if (!to)
  34. printk(KERN_WARNING "HiSax: waitforXFW timeout\n");
  35. }
  36. static inline void
  37. WriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data)
  38. {
  39. waitforCEC(cs, hscx);
  40. WRITEHSCX(cs, hscx, HSCX_CMDR, data);
  41. }
  42. static void
  43. hscx_empty_fifo(struct BCState *bcs, int count)
  44. {
  45. u_char *ptr;
  46. struct IsdnCardState *cs = bcs->cs;
  47. if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
  48. debugl1(cs, "hscx_empty_fifo");
  49. if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
  50. if (cs->debug & L1_DEB_WARN)
  51. debugl1(cs, "hscx_empty_fifo: incoming packet too large");
  52. WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
  53. bcs->hw.hscx.rcvidx = 0;
  54. return;
  55. }
  56. ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
  57. bcs->hw.hscx.rcvidx += count;
  58. READHSCXFIFO(cs, bcs->hw.hscx.hscx, ptr, count);
  59. WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
  60. if (cs->debug & L1_DEB_HSCX_FIFO) {
  61. char *t = bcs->blog;
  62. t += sprintf(t, "hscx_empty_fifo %c cnt %d",
  63. bcs->hw.hscx.hscx ? 'B' : 'A', count);
  64. QuickHex(t, ptr, count);
  65. debugl1(cs, "%s", bcs->blog);
  66. }
  67. }
  68. static void
  69. hscx_fill_fifo(struct BCState *bcs)
  70. {
  71. struct IsdnCardState *cs = bcs->cs;
  72. int more, count;
  73. int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags) ? 64 : 32;
  74. u_char *ptr;
  75. if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
  76. debugl1(cs, "hscx_fill_fifo");
  77. if (!bcs->tx_skb)
  78. return;
  79. if (bcs->tx_skb->len <= 0)
  80. return;
  81. more = (bcs->mode == L1_MODE_TRANS) ? 1 : 0;
  82. if (bcs->tx_skb->len > fifo_size) {
  83. more = !0;
  84. count = fifo_size;
  85. } else
  86. count = bcs->tx_skb->len;
  87. waitforXFW(cs, bcs->hw.hscx.hscx);
  88. ptr = bcs->tx_skb->data;
  89. skb_pull(bcs->tx_skb, count);
  90. bcs->tx_cnt -= count;
  91. bcs->hw.hscx.count += count;
  92. WRITEHSCXFIFO(cs, bcs->hw.hscx.hscx, ptr, count);
  93. WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa);
  94. if (cs->debug & L1_DEB_HSCX_FIFO) {
  95. char *t = bcs->blog;
  96. t += sprintf(t, "hscx_fill_fifo %c cnt %d",
  97. bcs->hw.hscx.hscx ? 'B' : 'A', count);
  98. QuickHex(t, ptr, count);
  99. debugl1(cs, "%s", bcs->blog);
  100. }
  101. }
  102. static void
  103. hscx_interrupt(struct IsdnCardState *cs, u_char val, u_char hscx)
  104. {
  105. u_char r;
  106. struct BCState *bcs = cs->bcs + hscx;
  107. struct sk_buff *skb;
  108. int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags) ? 64 : 32;
  109. int count;
  110. if (!test_bit(BC_FLG_INIT, &bcs->Flag))
  111. return;
  112. if (val & 0x80) { /* RME */
  113. r = READHSCX(cs, hscx, HSCX_RSTA);
  114. if ((r & 0xf0) != 0xa0) {
  115. if (!(r & 0x80)) {
  116. if (cs->debug & L1_DEB_WARN)
  117. debugl1(cs, "HSCX invalid frame");
  118. #ifdef ERROR_STATISTIC
  119. bcs->err_inv++;
  120. #endif
  121. }
  122. if ((r & 0x40) && bcs->mode) {
  123. if (cs->debug & L1_DEB_WARN)
  124. debugl1(cs, "HSCX RDO mode=%d",
  125. bcs->mode);
  126. #ifdef ERROR_STATISTIC
  127. bcs->err_rdo++;
  128. #endif
  129. }
  130. if (!(r & 0x20)) {
  131. if (cs->debug & L1_DEB_WARN)
  132. debugl1(cs, "HSCX CRC error");
  133. #ifdef ERROR_STATISTIC
  134. bcs->err_crc++;
  135. #endif
  136. }
  137. WriteHSCXCMDR(cs, hscx, 0x80);
  138. } else {
  139. count = READHSCX(cs, hscx, HSCX_RBCL) & (
  140. test_bit(HW_IPAC, &cs->HW_Flags) ? 0x3f : 0x1f);
  141. if (count == 0)
  142. count = fifo_size;
  143. hscx_empty_fifo(bcs, count);
  144. if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {
  145. if (cs->debug & L1_DEB_HSCX_FIFO)
  146. debugl1(cs, "HX Frame %d", count);
  147. if (!(skb = dev_alloc_skb(count)))
  148. printk(KERN_WARNING "HSCX: receive out of memory\n");
  149. else {
  150. memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count);
  151. skb_queue_tail(&bcs->rqueue, skb);
  152. }
  153. }
  154. }
  155. bcs->hw.hscx.rcvidx = 0;
  156. schedule_event(bcs, B_RCVBUFREADY);
  157. }
  158. if (val & 0x40) { /* RPF */
  159. hscx_empty_fifo(bcs, fifo_size);
  160. if (bcs->mode == L1_MODE_TRANS) {
  161. /* receive audio data */
  162. if (!(skb = dev_alloc_skb(fifo_size)))
  163. printk(KERN_WARNING "HiSax: receive out of memory\n");
  164. else {
  165. memcpy(skb_put(skb, fifo_size), bcs->hw.hscx.rcvbuf, fifo_size);
  166. skb_queue_tail(&bcs->rqueue, skb);
  167. }
  168. bcs->hw.hscx.rcvidx = 0;
  169. schedule_event(bcs, B_RCVBUFREADY);
  170. }
  171. }
  172. if (val & 0x10) { /* XPR */
  173. if (bcs->tx_skb) {
  174. if (bcs->tx_skb->len) {
  175. hscx_fill_fifo(bcs);
  176. return;
  177. } else {
  178. if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
  179. (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
  180. u_long flags;
  181. spin_lock_irqsave(&bcs->aclock, flags);
  182. bcs->ackcnt += bcs->hw.hscx.count;
  183. spin_unlock_irqrestore(&bcs->aclock, flags);
  184. schedule_event(bcs, B_ACKPENDING);
  185. }
  186. dev_kfree_skb_irq(bcs->tx_skb);
  187. bcs->hw.hscx.count = 0;
  188. bcs->tx_skb = NULL;
  189. }
  190. }
  191. if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
  192. bcs->hw.hscx.count = 0;
  193. test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
  194. hscx_fill_fifo(bcs);
  195. } else {
  196. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  197. schedule_event(bcs, B_XMTBUFREADY);
  198. }
  199. }
  200. }
  201. static void
  202. hscx_int_main(struct IsdnCardState *cs, u_char val)
  203. {
  204. u_char exval;
  205. struct BCState *bcs;
  206. if (val & 0x01) {
  207. bcs = cs->bcs + 1;
  208. exval = READHSCX(cs, 1, HSCX_EXIR);
  209. if (exval & 0x40) {
  210. if (bcs->mode == 1)
  211. hscx_fill_fifo(bcs);
  212. else {
  213. #ifdef ERROR_STATISTIC
  214. bcs->err_tx++;
  215. #endif
  216. /* Here we lost an TX interrupt, so
  217. * restart transmitting the whole frame.
  218. */
  219. if (bcs->tx_skb) {
  220. skb_push(bcs->tx_skb, bcs->hw.hscx.count);
  221. bcs->tx_cnt += bcs->hw.hscx.count;
  222. bcs->hw.hscx.count = 0;
  223. }
  224. WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);
  225. if (cs->debug & L1_DEB_WARN)
  226. debugl1(cs, "HSCX B EXIR %x Lost TX", exval);
  227. }
  228. } else if (cs->debug & L1_DEB_HSCX)
  229. debugl1(cs, "HSCX B EXIR %x", exval);
  230. }
  231. if (val & 0xf8) {
  232. if (cs->debug & L1_DEB_HSCX)
  233. debugl1(cs, "HSCX B interrupt %x", val);
  234. hscx_interrupt(cs, val, 1);
  235. }
  236. if (val & 0x02) {
  237. bcs = cs->bcs;
  238. exval = READHSCX(cs, 0, HSCX_EXIR);
  239. if (exval & 0x40) {
  240. if (bcs->mode == L1_MODE_TRANS)
  241. hscx_fill_fifo(bcs);
  242. else {
  243. /* Here we lost an TX interrupt, so
  244. * restart transmitting the whole frame.
  245. */
  246. #ifdef ERROR_STATISTIC
  247. bcs->err_tx++;
  248. #endif
  249. if (bcs->tx_skb) {
  250. skb_push(bcs->tx_skb, bcs->hw.hscx.count);
  251. bcs->tx_cnt += bcs->hw.hscx.count;
  252. bcs->hw.hscx.count = 0;
  253. }
  254. WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);
  255. if (cs->debug & L1_DEB_WARN)
  256. debugl1(cs, "HSCX A EXIR %x Lost TX", exval);
  257. }
  258. } else if (cs->debug & L1_DEB_HSCX)
  259. debugl1(cs, "HSCX A EXIR %x", exval);
  260. }
  261. if (val & 0x04) {
  262. exval = READHSCX(cs, 0, HSCX_ISTA);
  263. if (cs->debug & L1_DEB_HSCX)
  264. debugl1(cs, "HSCX A interrupt %x", exval);
  265. hscx_interrupt(cs, exval, 0);
  266. }
  267. }