afe4403.c 16 KB

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  1. /*
  2. * AFE4403 Heart Rate Monitors and Low-Cost Pulse Oximeters
  3. *
  4. * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
  5. * Andrew F. Davis <afd@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. */
  16. #include <linux/device.h>
  17. #include <linux/err.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/regmap.h>
  22. #include <linux/spi/spi.h>
  23. #include <linux/sysfs.h>
  24. #include <linux/regulator/consumer.h>
  25. #include <linux/iio/iio.h>
  26. #include <linux/iio/sysfs.h>
  27. #include <linux/iio/buffer.h>
  28. #include <linux/iio/trigger.h>
  29. #include <linux/iio/triggered_buffer.h>
  30. #include <linux/iio/trigger_consumer.h>
  31. #include "afe440x.h"
  32. #define AFE4403_DRIVER_NAME "afe4403"
  33. /* AFE4403 Registers */
  34. #define AFE4403_TIAGAIN 0x20
  35. #define AFE4403_TIA_AMB_GAIN 0x21
  36. enum afe4403_fields {
  37. /* Gains */
  38. F_RF_LED1, F_CF_LED1,
  39. F_RF_LED, F_CF_LED,
  40. /* LED Current */
  41. F_ILED1, F_ILED2,
  42. /* sentinel */
  43. F_MAX_FIELDS
  44. };
  45. static const struct reg_field afe4403_reg_fields[] = {
  46. /* Gains */
  47. [F_RF_LED1] = REG_FIELD(AFE4403_TIAGAIN, 0, 2),
  48. [F_CF_LED1] = REG_FIELD(AFE4403_TIAGAIN, 3, 7),
  49. [F_RF_LED] = REG_FIELD(AFE4403_TIA_AMB_GAIN, 0, 2),
  50. [F_CF_LED] = REG_FIELD(AFE4403_TIA_AMB_GAIN, 3, 7),
  51. /* LED Current */
  52. [F_ILED1] = REG_FIELD(AFE440X_LEDCNTRL, 0, 7),
  53. [F_ILED2] = REG_FIELD(AFE440X_LEDCNTRL, 8, 15),
  54. };
  55. /**
  56. * struct afe4403_data - AFE4403 device instance data
  57. * @dev: Device structure
  58. * @spi: SPI device handle
  59. * @regmap: Register map of the device
  60. * @fields: Register fields of the device
  61. * @regulator: Pointer to the regulator for the IC
  62. * @trig: IIO trigger for this device
  63. * @irq: ADC_RDY line interrupt number
  64. */
  65. struct afe4403_data {
  66. struct device *dev;
  67. struct spi_device *spi;
  68. struct regmap *regmap;
  69. struct regmap_field *fields[F_MAX_FIELDS];
  70. struct regulator *regulator;
  71. struct iio_trigger *trig;
  72. int irq;
  73. };
  74. enum afe4403_chan_id {
  75. LED2 = 1,
  76. ALED2,
  77. LED1,
  78. ALED1,
  79. LED2_ALED2,
  80. LED1_ALED1,
  81. };
  82. static const unsigned int afe4403_channel_values[] = {
  83. [LED2] = AFE440X_LED2VAL,
  84. [ALED2] = AFE440X_ALED2VAL,
  85. [LED1] = AFE440X_LED1VAL,
  86. [ALED1] = AFE440X_ALED1VAL,
  87. [LED2_ALED2] = AFE440X_LED2_ALED2VAL,
  88. [LED1_ALED1] = AFE440X_LED1_ALED1VAL,
  89. };
  90. static const unsigned int afe4403_channel_leds[] = {
  91. [LED2] = F_ILED2,
  92. [LED1] = F_ILED1,
  93. };
  94. static const struct iio_chan_spec afe4403_channels[] = {
  95. /* ADC values */
  96. AFE440X_INTENSITY_CHAN(LED2, 0),
  97. AFE440X_INTENSITY_CHAN(ALED2, 0),
  98. AFE440X_INTENSITY_CHAN(LED1, 0),
  99. AFE440X_INTENSITY_CHAN(ALED1, 0),
  100. AFE440X_INTENSITY_CHAN(LED2_ALED2, 0),
  101. AFE440X_INTENSITY_CHAN(LED1_ALED1, 0),
  102. /* LED current */
  103. AFE440X_CURRENT_CHAN(LED2),
  104. AFE440X_CURRENT_CHAN(LED1),
  105. };
  106. static const struct afe440x_val_table afe4403_res_table[] = {
  107. { 500000 }, { 250000 }, { 100000 }, { 50000 },
  108. { 25000 }, { 10000 }, { 1000000 }, { 0 },
  109. };
  110. AFE440X_TABLE_ATTR(in_intensity_resistance_available, afe4403_res_table);
  111. static const struct afe440x_val_table afe4403_cap_table[] = {
  112. { 0, 5000 }, { 0, 10000 }, { 0, 20000 }, { 0, 25000 },
  113. { 0, 30000 }, { 0, 35000 }, { 0, 45000 }, { 0, 50000 },
  114. { 0, 55000 }, { 0, 60000 }, { 0, 70000 }, { 0, 75000 },
  115. { 0, 80000 }, { 0, 85000 }, { 0, 95000 }, { 0, 100000 },
  116. { 0, 155000 }, { 0, 160000 }, { 0, 170000 }, { 0, 175000 },
  117. { 0, 180000 }, { 0, 185000 }, { 0, 195000 }, { 0, 200000 },
  118. { 0, 205000 }, { 0, 210000 }, { 0, 220000 }, { 0, 225000 },
  119. { 0, 230000 }, { 0, 235000 }, { 0, 245000 }, { 0, 250000 },
  120. };
  121. AFE440X_TABLE_ATTR(in_intensity_capacitance_available, afe4403_cap_table);
  122. static ssize_t afe440x_show_register(struct device *dev,
  123. struct device_attribute *attr,
  124. char *buf)
  125. {
  126. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  127. struct afe4403_data *afe = iio_priv(indio_dev);
  128. struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
  129. unsigned int reg_val;
  130. int vals[2];
  131. int ret;
  132. ret = regmap_field_read(afe->fields[afe440x_attr->field], &reg_val);
  133. if (ret)
  134. return ret;
  135. if (reg_val >= afe440x_attr->table_size)
  136. return -EINVAL;
  137. vals[0] = afe440x_attr->val_table[reg_val].integer;
  138. vals[1] = afe440x_attr->val_table[reg_val].fract;
  139. return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals);
  140. }
  141. static ssize_t afe440x_store_register(struct device *dev,
  142. struct device_attribute *attr,
  143. const char *buf, size_t count)
  144. {
  145. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  146. struct afe4403_data *afe = iio_priv(indio_dev);
  147. struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
  148. int val, integer, fract, ret;
  149. ret = iio_str_to_fixpoint(buf, 100000, &integer, &fract);
  150. if (ret)
  151. return ret;
  152. for (val = 0; val < afe440x_attr->table_size; val++)
  153. if (afe440x_attr->val_table[val].integer == integer &&
  154. afe440x_attr->val_table[val].fract == fract)
  155. break;
  156. if (val == afe440x_attr->table_size)
  157. return -EINVAL;
  158. ret = regmap_field_write(afe->fields[afe440x_attr->field], val);
  159. if (ret)
  160. return ret;
  161. return count;
  162. }
  163. static AFE440X_ATTR(in_intensity1_resistance, F_RF_LED, afe4403_res_table);
  164. static AFE440X_ATTR(in_intensity1_capacitance, F_CF_LED, afe4403_cap_table);
  165. static AFE440X_ATTR(in_intensity2_resistance, F_RF_LED, afe4403_res_table);
  166. static AFE440X_ATTR(in_intensity2_capacitance, F_CF_LED, afe4403_cap_table);
  167. static AFE440X_ATTR(in_intensity3_resistance, F_RF_LED1, afe4403_res_table);
  168. static AFE440X_ATTR(in_intensity3_capacitance, F_CF_LED1, afe4403_cap_table);
  169. static AFE440X_ATTR(in_intensity4_resistance, F_RF_LED1, afe4403_res_table);
  170. static AFE440X_ATTR(in_intensity4_capacitance, F_CF_LED1, afe4403_cap_table);
  171. static struct attribute *afe440x_attributes[] = {
  172. &dev_attr_in_intensity_resistance_available.attr,
  173. &dev_attr_in_intensity_capacitance_available.attr,
  174. &afe440x_attr_in_intensity1_resistance.dev_attr.attr,
  175. &afe440x_attr_in_intensity1_capacitance.dev_attr.attr,
  176. &afe440x_attr_in_intensity2_resistance.dev_attr.attr,
  177. &afe440x_attr_in_intensity2_capacitance.dev_attr.attr,
  178. &afe440x_attr_in_intensity3_resistance.dev_attr.attr,
  179. &afe440x_attr_in_intensity3_capacitance.dev_attr.attr,
  180. &afe440x_attr_in_intensity4_resistance.dev_attr.attr,
  181. &afe440x_attr_in_intensity4_capacitance.dev_attr.attr,
  182. NULL
  183. };
  184. static const struct attribute_group afe440x_attribute_group = {
  185. .attrs = afe440x_attributes
  186. };
  187. static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val)
  188. {
  189. u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
  190. u8 rx[3];
  191. int ret;
  192. /* Enable reading from the device */
  193. ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
  194. if (ret)
  195. return ret;
  196. ret = spi_write_then_read(afe->spi, &reg, 1, rx, 3);
  197. if (ret)
  198. return ret;
  199. *val = (rx[0] << 16) |
  200. (rx[1] << 8) |
  201. (rx[2]);
  202. /* Disable reading from the device */
  203. tx[3] = AFE440X_CONTROL0_WRITE;
  204. ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
  205. if (ret)
  206. return ret;
  207. return 0;
  208. }
  209. static int afe4403_read_raw(struct iio_dev *indio_dev,
  210. struct iio_chan_spec const *chan,
  211. int *val, int *val2, long mask)
  212. {
  213. struct afe4403_data *afe = iio_priv(indio_dev);
  214. unsigned int reg = afe4403_channel_values[chan->address];
  215. unsigned int field = afe4403_channel_leds[chan->address];
  216. int ret;
  217. switch (chan->type) {
  218. case IIO_INTENSITY:
  219. switch (mask) {
  220. case IIO_CHAN_INFO_RAW:
  221. ret = afe4403_read(afe, reg, val);
  222. if (ret)
  223. return ret;
  224. return IIO_VAL_INT;
  225. }
  226. break;
  227. case IIO_CURRENT:
  228. switch (mask) {
  229. case IIO_CHAN_INFO_RAW:
  230. ret = regmap_field_read(afe->fields[field], val);
  231. if (ret)
  232. return ret;
  233. return IIO_VAL_INT;
  234. case IIO_CHAN_INFO_SCALE:
  235. *val = 0;
  236. *val2 = 800000;
  237. return IIO_VAL_INT_PLUS_MICRO;
  238. }
  239. break;
  240. default:
  241. break;
  242. }
  243. return -EINVAL;
  244. }
  245. static int afe4403_write_raw(struct iio_dev *indio_dev,
  246. struct iio_chan_spec const *chan,
  247. int val, int val2, long mask)
  248. {
  249. struct afe4403_data *afe = iio_priv(indio_dev);
  250. unsigned int field = afe4403_channel_leds[chan->address];
  251. switch (chan->type) {
  252. case IIO_CURRENT:
  253. switch (mask) {
  254. case IIO_CHAN_INFO_RAW:
  255. return regmap_field_write(afe->fields[field], val);
  256. }
  257. break;
  258. default:
  259. break;
  260. }
  261. return -EINVAL;
  262. }
  263. static const struct iio_info afe4403_iio_info = {
  264. .attrs = &afe440x_attribute_group,
  265. .read_raw = afe4403_read_raw,
  266. .write_raw = afe4403_write_raw,
  267. .driver_module = THIS_MODULE,
  268. };
  269. static irqreturn_t afe4403_trigger_handler(int irq, void *private)
  270. {
  271. struct iio_poll_func *pf = private;
  272. struct iio_dev *indio_dev = pf->indio_dev;
  273. struct afe4403_data *afe = iio_priv(indio_dev);
  274. int ret, bit, i = 0;
  275. s32 buffer[8];
  276. u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
  277. u8 rx[3];
  278. /* Enable reading from the device */
  279. ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
  280. if (ret)
  281. goto err;
  282. for_each_set_bit(bit, indio_dev->active_scan_mask,
  283. indio_dev->masklength) {
  284. ret = spi_write_then_read(afe->spi,
  285. &afe4403_channel_values[bit], 1,
  286. rx, 3);
  287. if (ret)
  288. goto err;
  289. buffer[i++] = (rx[0] << 16) |
  290. (rx[1] << 8) |
  291. (rx[2]);
  292. }
  293. /* Disable reading from the device */
  294. tx[3] = AFE440X_CONTROL0_WRITE;
  295. ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
  296. if (ret)
  297. goto err;
  298. iio_push_to_buffers_with_timestamp(indio_dev, buffer, pf->timestamp);
  299. err:
  300. iio_trigger_notify_done(indio_dev->trig);
  301. return IRQ_HANDLED;
  302. }
  303. static const struct iio_trigger_ops afe4403_trigger_ops = {
  304. .owner = THIS_MODULE,
  305. };
  306. #define AFE4403_TIMING_PAIRS \
  307. { AFE440X_LED2STC, 0x000050 }, \
  308. { AFE440X_LED2ENDC, 0x0003e7 }, \
  309. { AFE440X_LED1LEDSTC, 0x0007d0 }, \
  310. { AFE440X_LED1LEDENDC, 0x000bb7 }, \
  311. { AFE440X_ALED2STC, 0x000438 }, \
  312. { AFE440X_ALED2ENDC, 0x0007cf }, \
  313. { AFE440X_LED1STC, 0x000820 }, \
  314. { AFE440X_LED1ENDC, 0x000bb7 }, \
  315. { AFE440X_LED2LEDSTC, 0x000000 }, \
  316. { AFE440X_LED2LEDENDC, 0x0003e7 }, \
  317. { AFE440X_ALED1STC, 0x000c08 }, \
  318. { AFE440X_ALED1ENDC, 0x000f9f }, \
  319. { AFE440X_LED2CONVST, 0x0003ef }, \
  320. { AFE440X_LED2CONVEND, 0x0007cf }, \
  321. { AFE440X_ALED2CONVST, 0x0007d7 }, \
  322. { AFE440X_ALED2CONVEND, 0x000bb7 }, \
  323. { AFE440X_LED1CONVST, 0x000bbf }, \
  324. { AFE440X_LED1CONVEND, 0x009c3f }, \
  325. { AFE440X_ALED1CONVST, 0x000fa7 }, \
  326. { AFE440X_ALED1CONVEND, 0x001387 }, \
  327. { AFE440X_ADCRSTSTCT0, 0x0003e8 }, \
  328. { AFE440X_ADCRSTENDCT0, 0x0003eb }, \
  329. { AFE440X_ADCRSTSTCT1, 0x0007d0 }, \
  330. { AFE440X_ADCRSTENDCT1, 0x0007d3 }, \
  331. { AFE440X_ADCRSTSTCT2, 0x000bb8 }, \
  332. { AFE440X_ADCRSTENDCT2, 0x000bbb }, \
  333. { AFE440X_ADCRSTSTCT3, 0x000fa0 }, \
  334. { AFE440X_ADCRSTENDCT3, 0x000fa3 }, \
  335. { AFE440X_PRPCOUNT, 0x009c3f }, \
  336. { AFE440X_PDNCYCLESTC, 0x001518 }, \
  337. { AFE440X_PDNCYCLEENDC, 0x00991f }
  338. static const struct reg_sequence afe4403_reg_sequences[] = {
  339. AFE4403_TIMING_PAIRS,
  340. { AFE440X_CONTROL1, AFE440X_CONTROL1_TIMEREN },
  341. { AFE4403_TIAGAIN, AFE440X_TIAGAIN_ENSEPGAIN },
  342. };
  343. static const struct regmap_range afe4403_yes_ranges[] = {
  344. regmap_reg_range(AFE440X_LED2VAL, AFE440X_LED1_ALED1VAL),
  345. };
  346. static const struct regmap_access_table afe4403_volatile_table = {
  347. .yes_ranges = afe4403_yes_ranges,
  348. .n_yes_ranges = ARRAY_SIZE(afe4403_yes_ranges),
  349. };
  350. static const struct regmap_config afe4403_regmap_config = {
  351. .reg_bits = 8,
  352. .val_bits = 24,
  353. .max_register = AFE440X_PDNCYCLEENDC,
  354. .cache_type = REGCACHE_RBTREE,
  355. .volatile_table = &afe4403_volatile_table,
  356. };
  357. static const struct of_device_id afe4403_of_match[] = {
  358. { .compatible = "ti,afe4403", },
  359. { /* sentinel */ }
  360. };
  361. MODULE_DEVICE_TABLE(of, afe4403_of_match);
  362. static int __maybe_unused afe4403_suspend(struct device *dev)
  363. {
  364. struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
  365. struct afe4403_data *afe = iio_priv(indio_dev);
  366. int ret;
  367. ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
  368. AFE440X_CONTROL2_PDN_AFE,
  369. AFE440X_CONTROL2_PDN_AFE);
  370. if (ret)
  371. return ret;
  372. ret = regulator_disable(afe->regulator);
  373. if (ret) {
  374. dev_err(dev, "Unable to disable regulator\n");
  375. return ret;
  376. }
  377. return 0;
  378. }
  379. static int __maybe_unused afe4403_resume(struct device *dev)
  380. {
  381. struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
  382. struct afe4403_data *afe = iio_priv(indio_dev);
  383. int ret;
  384. ret = regulator_enable(afe->regulator);
  385. if (ret) {
  386. dev_err(dev, "Unable to enable regulator\n");
  387. return ret;
  388. }
  389. ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
  390. AFE440X_CONTROL2_PDN_AFE, 0);
  391. if (ret)
  392. return ret;
  393. return 0;
  394. }
  395. static SIMPLE_DEV_PM_OPS(afe4403_pm_ops, afe4403_suspend, afe4403_resume);
  396. static int afe4403_probe(struct spi_device *spi)
  397. {
  398. struct iio_dev *indio_dev;
  399. struct afe4403_data *afe;
  400. int i, ret;
  401. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*afe));
  402. if (!indio_dev)
  403. return -ENOMEM;
  404. afe = iio_priv(indio_dev);
  405. spi_set_drvdata(spi, indio_dev);
  406. afe->dev = &spi->dev;
  407. afe->spi = spi;
  408. afe->irq = spi->irq;
  409. afe->regmap = devm_regmap_init_spi(spi, &afe4403_regmap_config);
  410. if (IS_ERR(afe->regmap)) {
  411. dev_err(afe->dev, "Unable to allocate register map\n");
  412. return PTR_ERR(afe->regmap);
  413. }
  414. for (i = 0; i < F_MAX_FIELDS; i++) {
  415. afe->fields[i] = devm_regmap_field_alloc(afe->dev, afe->regmap,
  416. afe4403_reg_fields[i]);
  417. if (IS_ERR(afe->fields[i])) {
  418. dev_err(afe->dev, "Unable to allocate regmap fields\n");
  419. return PTR_ERR(afe->fields[i]);
  420. }
  421. }
  422. afe->regulator = devm_regulator_get(afe->dev, "tx_sup");
  423. if (IS_ERR(afe->regulator)) {
  424. dev_err(afe->dev, "Unable to get regulator\n");
  425. return PTR_ERR(afe->regulator);
  426. }
  427. ret = regulator_enable(afe->regulator);
  428. if (ret) {
  429. dev_err(afe->dev, "Unable to enable regulator\n");
  430. return ret;
  431. }
  432. ret = regmap_write(afe->regmap, AFE440X_CONTROL0,
  433. AFE440X_CONTROL0_SW_RESET);
  434. if (ret) {
  435. dev_err(afe->dev, "Unable to reset device\n");
  436. goto err_disable_reg;
  437. }
  438. ret = regmap_multi_reg_write(afe->regmap, afe4403_reg_sequences,
  439. ARRAY_SIZE(afe4403_reg_sequences));
  440. if (ret) {
  441. dev_err(afe->dev, "Unable to set register defaults\n");
  442. goto err_disable_reg;
  443. }
  444. indio_dev->modes = INDIO_DIRECT_MODE;
  445. indio_dev->dev.parent = afe->dev;
  446. indio_dev->channels = afe4403_channels;
  447. indio_dev->num_channels = ARRAY_SIZE(afe4403_channels);
  448. indio_dev->name = AFE4403_DRIVER_NAME;
  449. indio_dev->info = &afe4403_iio_info;
  450. if (afe->irq > 0) {
  451. afe->trig = devm_iio_trigger_alloc(afe->dev,
  452. "%s-dev%d",
  453. indio_dev->name,
  454. indio_dev->id);
  455. if (!afe->trig) {
  456. dev_err(afe->dev, "Unable to allocate IIO trigger\n");
  457. ret = -ENOMEM;
  458. goto err_disable_reg;
  459. }
  460. iio_trigger_set_drvdata(afe->trig, indio_dev);
  461. afe->trig->ops = &afe4403_trigger_ops;
  462. afe->trig->dev.parent = afe->dev;
  463. ret = iio_trigger_register(afe->trig);
  464. if (ret) {
  465. dev_err(afe->dev, "Unable to register IIO trigger\n");
  466. goto err_disable_reg;
  467. }
  468. ret = devm_request_threaded_irq(afe->dev, afe->irq,
  469. iio_trigger_generic_data_rdy_poll,
  470. NULL, IRQF_ONESHOT,
  471. AFE4403_DRIVER_NAME,
  472. afe->trig);
  473. if (ret) {
  474. dev_err(afe->dev, "Unable to request IRQ\n");
  475. goto err_trig;
  476. }
  477. }
  478. ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
  479. afe4403_trigger_handler, NULL);
  480. if (ret) {
  481. dev_err(afe->dev, "Unable to setup buffer\n");
  482. goto err_trig;
  483. }
  484. ret = iio_device_register(indio_dev);
  485. if (ret) {
  486. dev_err(afe->dev, "Unable to register IIO device\n");
  487. goto err_buff;
  488. }
  489. return 0;
  490. err_buff:
  491. iio_triggered_buffer_cleanup(indio_dev);
  492. err_trig:
  493. if (afe->irq > 0)
  494. iio_trigger_unregister(afe->trig);
  495. err_disable_reg:
  496. regulator_disable(afe->regulator);
  497. return ret;
  498. }
  499. static int afe4403_remove(struct spi_device *spi)
  500. {
  501. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  502. struct afe4403_data *afe = iio_priv(indio_dev);
  503. int ret;
  504. iio_device_unregister(indio_dev);
  505. iio_triggered_buffer_cleanup(indio_dev);
  506. if (afe->irq > 0)
  507. iio_trigger_unregister(afe->trig);
  508. ret = regulator_disable(afe->regulator);
  509. if (ret) {
  510. dev_err(afe->dev, "Unable to disable regulator\n");
  511. return ret;
  512. }
  513. return 0;
  514. }
  515. static const struct spi_device_id afe4403_ids[] = {
  516. { "afe4403", 0 },
  517. { /* sentinel */ }
  518. };
  519. MODULE_DEVICE_TABLE(spi, afe4403_ids);
  520. static struct spi_driver afe4403_spi_driver = {
  521. .driver = {
  522. .name = AFE4403_DRIVER_NAME,
  523. .of_match_table = afe4403_of_match,
  524. .pm = &afe4403_pm_ops,
  525. },
  526. .probe = afe4403_probe,
  527. .remove = afe4403_remove,
  528. .id_table = afe4403_ids,
  529. };
  530. module_spi_driver(afe4403_spi_driver);
  531. MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
  532. MODULE_DESCRIPTION("TI AFE4403 Heart Rate Monitor and Pulse Oximeter AFE");
  533. MODULE_LICENSE("GPL v2");