ad5421.c 13 KB

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  1. /*
  2. * AD5421 Digital to analog converters driver
  3. *
  4. * Copyright 2011 Analog Devices Inc.
  5. *
  6. * Licensed under the GPL-2.
  7. */
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/err.h>
  11. #include <linux/module.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/slab.h>
  16. #include <linux/sysfs.h>
  17. #include <linux/iio/iio.h>
  18. #include <linux/iio/sysfs.h>
  19. #include <linux/iio/events.h>
  20. #include <linux/iio/dac/ad5421.h>
  21. #define AD5421_REG_DAC_DATA 0x1
  22. #define AD5421_REG_CTRL 0x2
  23. #define AD5421_REG_OFFSET 0x3
  24. #define AD5421_REG_GAIN 0x4
  25. /* load dac and fault shared the same register number. Writing to it will cause
  26. * a dac load command, reading from it will return the fault status register */
  27. #define AD5421_REG_LOAD_DAC 0x5
  28. #define AD5421_REG_FAULT 0x5
  29. #define AD5421_REG_FORCE_ALARM_CURRENT 0x6
  30. #define AD5421_REG_RESET 0x7
  31. #define AD5421_REG_START_CONVERSION 0x8
  32. #define AD5421_REG_NOOP 0x9
  33. #define AD5421_CTRL_WATCHDOG_DISABLE BIT(12)
  34. #define AD5421_CTRL_AUTO_FAULT_READBACK BIT(11)
  35. #define AD5421_CTRL_MIN_CURRENT BIT(9)
  36. #define AD5421_CTRL_ADC_SOURCE_TEMP BIT(8)
  37. #define AD5421_CTRL_ADC_ENABLE BIT(7)
  38. #define AD5421_CTRL_PWR_DOWN_INT_VREF BIT(6)
  39. #define AD5421_FAULT_SPI BIT(15)
  40. #define AD5421_FAULT_PEC BIT(14)
  41. #define AD5421_FAULT_OVER_CURRENT BIT(13)
  42. #define AD5421_FAULT_UNDER_CURRENT BIT(12)
  43. #define AD5421_FAULT_TEMP_OVER_140 BIT(11)
  44. #define AD5421_FAULT_TEMP_OVER_100 BIT(10)
  45. #define AD5421_FAULT_UNDER_VOLTAGE_6V BIT(9)
  46. #define AD5421_FAULT_UNDER_VOLTAGE_12V BIT(8)
  47. /* These bits will cause the fault pin to go high */
  48. #define AD5421_FAULT_TRIGGER_IRQ \
  49. (AD5421_FAULT_SPI | AD5421_FAULT_PEC | AD5421_FAULT_OVER_CURRENT | \
  50. AD5421_FAULT_UNDER_CURRENT | AD5421_FAULT_TEMP_OVER_140)
  51. /**
  52. * struct ad5421_state - driver instance specific data
  53. * @spi: spi_device
  54. * @ctrl: control register cache
  55. * @current_range: current range which the device is configured for
  56. * @data: spi transfer buffers
  57. * @fault_mask: software masking of events
  58. */
  59. struct ad5421_state {
  60. struct spi_device *spi;
  61. unsigned int ctrl;
  62. enum ad5421_current_range current_range;
  63. unsigned int fault_mask;
  64. /*
  65. * DMA (thus cache coherency maintenance) requires the
  66. * transfer buffers to live in their own cache lines.
  67. */
  68. union {
  69. __be32 d32;
  70. u8 d8[4];
  71. } data[2] ____cacheline_aligned;
  72. };
  73. static const struct iio_event_spec ad5421_current_event[] = {
  74. {
  75. .type = IIO_EV_TYPE_THRESH,
  76. .dir = IIO_EV_DIR_RISING,
  77. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  78. BIT(IIO_EV_INFO_ENABLE),
  79. }, {
  80. .type = IIO_EV_TYPE_THRESH,
  81. .dir = IIO_EV_DIR_FALLING,
  82. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  83. BIT(IIO_EV_INFO_ENABLE),
  84. },
  85. };
  86. static const struct iio_event_spec ad5421_temp_event[] = {
  87. {
  88. .type = IIO_EV_TYPE_THRESH,
  89. .dir = IIO_EV_DIR_RISING,
  90. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  91. BIT(IIO_EV_INFO_ENABLE),
  92. },
  93. };
  94. static const struct iio_chan_spec ad5421_channels[] = {
  95. {
  96. .type = IIO_CURRENT,
  97. .indexed = 1,
  98. .output = 1,
  99. .channel = 0,
  100. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  101. BIT(IIO_CHAN_INFO_CALIBSCALE) |
  102. BIT(IIO_CHAN_INFO_CALIBBIAS),
  103. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
  104. BIT(IIO_CHAN_INFO_OFFSET),
  105. .scan_type = {
  106. .sign = 'u',
  107. .realbits = 16,
  108. .storagebits = 16,
  109. },
  110. .event_spec = ad5421_current_event,
  111. .num_event_specs = ARRAY_SIZE(ad5421_current_event),
  112. },
  113. {
  114. .type = IIO_TEMP,
  115. .channel = -1,
  116. .event_spec = ad5421_temp_event,
  117. .num_event_specs = ARRAY_SIZE(ad5421_temp_event),
  118. },
  119. };
  120. static int ad5421_write_unlocked(struct iio_dev *indio_dev,
  121. unsigned int reg, unsigned int val)
  122. {
  123. struct ad5421_state *st = iio_priv(indio_dev);
  124. st->data[0].d32 = cpu_to_be32((reg << 16) | val);
  125. return spi_write(st->spi, &st->data[0].d8[1], 3);
  126. }
  127. static int ad5421_write(struct iio_dev *indio_dev, unsigned int reg,
  128. unsigned int val)
  129. {
  130. int ret;
  131. mutex_lock(&indio_dev->mlock);
  132. ret = ad5421_write_unlocked(indio_dev, reg, val);
  133. mutex_unlock(&indio_dev->mlock);
  134. return ret;
  135. }
  136. static int ad5421_read(struct iio_dev *indio_dev, unsigned int reg)
  137. {
  138. struct ad5421_state *st = iio_priv(indio_dev);
  139. int ret;
  140. struct spi_transfer t[] = {
  141. {
  142. .tx_buf = &st->data[0].d8[1],
  143. .len = 3,
  144. .cs_change = 1,
  145. }, {
  146. .rx_buf = &st->data[1].d8[1],
  147. .len = 3,
  148. },
  149. };
  150. mutex_lock(&indio_dev->mlock);
  151. st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16));
  152. ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
  153. if (ret >= 0)
  154. ret = be32_to_cpu(st->data[1].d32) & 0xffff;
  155. mutex_unlock(&indio_dev->mlock);
  156. return ret;
  157. }
  158. static int ad5421_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
  159. unsigned int clr)
  160. {
  161. struct ad5421_state *st = iio_priv(indio_dev);
  162. unsigned int ret;
  163. mutex_lock(&indio_dev->mlock);
  164. st->ctrl &= ~clr;
  165. st->ctrl |= set;
  166. ret = ad5421_write_unlocked(indio_dev, AD5421_REG_CTRL, st->ctrl);
  167. mutex_unlock(&indio_dev->mlock);
  168. return ret;
  169. }
  170. static irqreturn_t ad5421_fault_handler(int irq, void *data)
  171. {
  172. struct iio_dev *indio_dev = data;
  173. struct ad5421_state *st = iio_priv(indio_dev);
  174. unsigned int fault;
  175. unsigned int old_fault = 0;
  176. unsigned int events;
  177. fault = ad5421_read(indio_dev, AD5421_REG_FAULT);
  178. if (!fault)
  179. return IRQ_NONE;
  180. /* If we had a fault, this might mean that the DAC has lost its state
  181. * and has been reset. Make sure that the control register actually
  182. * contains what we expect it to contain. Otherwise the watchdog might
  183. * be enabled and we get watchdog timeout faults, which will render the
  184. * DAC unusable. */
  185. ad5421_update_ctrl(indio_dev, 0, 0);
  186. /* The fault pin stays high as long as a fault condition is present and
  187. * it is not possible to mask fault conditions. For certain fault
  188. * conditions for example like over-temperature it takes some time
  189. * until the fault condition disappears. If we would exit the interrupt
  190. * handler immediately after handling the event it would be entered
  191. * again instantly. Thus we fall back to polling in case we detect that
  192. * a interrupt condition is still present.
  193. */
  194. do {
  195. /* 0xffff is a invalid value for the register and will only be
  196. * read if there has been a communication error */
  197. if (fault == 0xffff)
  198. fault = 0;
  199. /* we are only interested in new events */
  200. events = (old_fault ^ fault) & fault;
  201. events &= st->fault_mask;
  202. if (events & AD5421_FAULT_OVER_CURRENT) {
  203. iio_push_event(indio_dev,
  204. IIO_UNMOD_EVENT_CODE(IIO_CURRENT,
  205. 0,
  206. IIO_EV_TYPE_THRESH,
  207. IIO_EV_DIR_RISING),
  208. iio_get_time_ns(indio_dev));
  209. }
  210. if (events & AD5421_FAULT_UNDER_CURRENT) {
  211. iio_push_event(indio_dev,
  212. IIO_UNMOD_EVENT_CODE(IIO_CURRENT,
  213. 0,
  214. IIO_EV_TYPE_THRESH,
  215. IIO_EV_DIR_FALLING),
  216. iio_get_time_ns(indio_dev));
  217. }
  218. if (events & AD5421_FAULT_TEMP_OVER_140) {
  219. iio_push_event(indio_dev,
  220. IIO_UNMOD_EVENT_CODE(IIO_TEMP,
  221. 0,
  222. IIO_EV_TYPE_MAG,
  223. IIO_EV_DIR_RISING),
  224. iio_get_time_ns(indio_dev));
  225. }
  226. old_fault = fault;
  227. fault = ad5421_read(indio_dev, AD5421_REG_FAULT);
  228. /* still active? go to sleep for some time */
  229. if (fault & AD5421_FAULT_TRIGGER_IRQ)
  230. msleep(1000);
  231. } while (fault & AD5421_FAULT_TRIGGER_IRQ);
  232. return IRQ_HANDLED;
  233. }
  234. static void ad5421_get_current_min_max(struct ad5421_state *st,
  235. unsigned int *min, unsigned int *max)
  236. {
  237. /* The current range is configured using external pins, which are
  238. * usually hard-wired and not run-time switchable. */
  239. switch (st->current_range) {
  240. case AD5421_CURRENT_RANGE_4mA_20mA:
  241. *min = 4000;
  242. *max = 20000;
  243. break;
  244. case AD5421_CURRENT_RANGE_3mA8_21mA:
  245. *min = 3800;
  246. *max = 21000;
  247. break;
  248. case AD5421_CURRENT_RANGE_3mA2_24mA:
  249. *min = 3200;
  250. *max = 24000;
  251. break;
  252. default:
  253. *min = 0;
  254. *max = 1;
  255. break;
  256. }
  257. }
  258. static inline unsigned int ad5421_get_offset(struct ad5421_state *st)
  259. {
  260. unsigned int min, max;
  261. ad5421_get_current_min_max(st, &min, &max);
  262. return (min * (1 << 16)) / (max - min);
  263. }
  264. static int ad5421_read_raw(struct iio_dev *indio_dev,
  265. struct iio_chan_spec const *chan, int *val, int *val2, long m)
  266. {
  267. struct ad5421_state *st = iio_priv(indio_dev);
  268. unsigned int min, max;
  269. int ret;
  270. if (chan->type != IIO_CURRENT)
  271. return -EINVAL;
  272. switch (m) {
  273. case IIO_CHAN_INFO_RAW:
  274. ret = ad5421_read(indio_dev, AD5421_REG_DAC_DATA);
  275. if (ret < 0)
  276. return ret;
  277. *val = ret;
  278. return IIO_VAL_INT;
  279. case IIO_CHAN_INFO_SCALE:
  280. ad5421_get_current_min_max(st, &min, &max);
  281. *val = max - min;
  282. *val2 = (1 << 16) * 1000;
  283. return IIO_VAL_FRACTIONAL;
  284. case IIO_CHAN_INFO_OFFSET:
  285. *val = ad5421_get_offset(st);
  286. return IIO_VAL_INT;
  287. case IIO_CHAN_INFO_CALIBBIAS:
  288. ret = ad5421_read(indio_dev, AD5421_REG_OFFSET);
  289. if (ret < 0)
  290. return ret;
  291. *val = ret - 32768;
  292. return IIO_VAL_INT;
  293. case IIO_CHAN_INFO_CALIBSCALE:
  294. ret = ad5421_read(indio_dev, AD5421_REG_GAIN);
  295. if (ret < 0)
  296. return ret;
  297. *val = ret;
  298. return IIO_VAL_INT;
  299. }
  300. return -EINVAL;
  301. }
  302. static int ad5421_write_raw(struct iio_dev *indio_dev,
  303. struct iio_chan_spec const *chan, int val, int val2, long mask)
  304. {
  305. const unsigned int max_val = 1 << 16;
  306. switch (mask) {
  307. case IIO_CHAN_INFO_RAW:
  308. if (val >= max_val || val < 0)
  309. return -EINVAL;
  310. return ad5421_write(indio_dev, AD5421_REG_DAC_DATA, val);
  311. case IIO_CHAN_INFO_CALIBBIAS:
  312. val += 32768;
  313. if (val >= max_val || val < 0)
  314. return -EINVAL;
  315. return ad5421_write(indio_dev, AD5421_REG_OFFSET, val);
  316. case IIO_CHAN_INFO_CALIBSCALE:
  317. if (val >= max_val || val < 0)
  318. return -EINVAL;
  319. return ad5421_write(indio_dev, AD5421_REG_GAIN, val);
  320. default:
  321. break;
  322. }
  323. return -EINVAL;
  324. }
  325. static int ad5421_write_event_config(struct iio_dev *indio_dev,
  326. const struct iio_chan_spec *chan, enum iio_event_type type,
  327. enum iio_event_direction dir, int state)
  328. {
  329. struct ad5421_state *st = iio_priv(indio_dev);
  330. unsigned int mask;
  331. switch (chan->type) {
  332. case IIO_CURRENT:
  333. if (dir == IIO_EV_DIR_RISING)
  334. mask = AD5421_FAULT_OVER_CURRENT;
  335. else
  336. mask = AD5421_FAULT_UNDER_CURRENT;
  337. break;
  338. case IIO_TEMP:
  339. mask = AD5421_FAULT_TEMP_OVER_140;
  340. break;
  341. default:
  342. return -EINVAL;
  343. }
  344. mutex_lock(&indio_dev->mlock);
  345. if (state)
  346. st->fault_mask |= mask;
  347. else
  348. st->fault_mask &= ~mask;
  349. mutex_unlock(&indio_dev->mlock);
  350. return 0;
  351. }
  352. static int ad5421_read_event_config(struct iio_dev *indio_dev,
  353. const struct iio_chan_spec *chan, enum iio_event_type type,
  354. enum iio_event_direction dir)
  355. {
  356. struct ad5421_state *st = iio_priv(indio_dev);
  357. unsigned int mask;
  358. switch (chan->type) {
  359. case IIO_CURRENT:
  360. if (dir == IIO_EV_DIR_RISING)
  361. mask = AD5421_FAULT_OVER_CURRENT;
  362. else
  363. mask = AD5421_FAULT_UNDER_CURRENT;
  364. break;
  365. case IIO_TEMP:
  366. mask = AD5421_FAULT_TEMP_OVER_140;
  367. break;
  368. default:
  369. return -EINVAL;
  370. }
  371. return (bool)(st->fault_mask & mask);
  372. }
  373. static int ad5421_read_event_value(struct iio_dev *indio_dev,
  374. const struct iio_chan_spec *chan, enum iio_event_type type,
  375. enum iio_event_direction dir, enum iio_event_info info, int *val,
  376. int *val2)
  377. {
  378. int ret;
  379. switch (chan->type) {
  380. case IIO_CURRENT:
  381. ret = ad5421_read(indio_dev, AD5421_REG_DAC_DATA);
  382. if (ret < 0)
  383. return ret;
  384. *val = ret;
  385. break;
  386. case IIO_TEMP:
  387. *val = 140000;
  388. break;
  389. default:
  390. return -EINVAL;
  391. }
  392. return IIO_VAL_INT;
  393. }
  394. static const struct iio_info ad5421_info = {
  395. .read_raw = ad5421_read_raw,
  396. .write_raw = ad5421_write_raw,
  397. .read_event_config = ad5421_read_event_config,
  398. .write_event_config = ad5421_write_event_config,
  399. .read_event_value = ad5421_read_event_value,
  400. .driver_module = THIS_MODULE,
  401. };
  402. static int ad5421_probe(struct spi_device *spi)
  403. {
  404. struct ad5421_platform_data *pdata = dev_get_platdata(&spi->dev);
  405. struct iio_dev *indio_dev;
  406. struct ad5421_state *st;
  407. int ret;
  408. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  409. if (indio_dev == NULL) {
  410. dev_err(&spi->dev, "Failed to allocate iio device\n");
  411. return -ENOMEM;
  412. }
  413. st = iio_priv(indio_dev);
  414. spi_set_drvdata(spi, indio_dev);
  415. st->spi = spi;
  416. indio_dev->dev.parent = &spi->dev;
  417. indio_dev->name = "ad5421";
  418. indio_dev->info = &ad5421_info;
  419. indio_dev->modes = INDIO_DIRECT_MODE;
  420. indio_dev->channels = ad5421_channels;
  421. indio_dev->num_channels = ARRAY_SIZE(ad5421_channels);
  422. st->ctrl = AD5421_CTRL_WATCHDOG_DISABLE |
  423. AD5421_CTRL_AUTO_FAULT_READBACK;
  424. if (pdata) {
  425. st->current_range = pdata->current_range;
  426. if (pdata->external_vref)
  427. st->ctrl |= AD5421_CTRL_PWR_DOWN_INT_VREF;
  428. } else {
  429. st->current_range = AD5421_CURRENT_RANGE_4mA_20mA;
  430. }
  431. /* write initial ctrl register value */
  432. ad5421_update_ctrl(indio_dev, 0, 0);
  433. if (spi->irq) {
  434. ret = devm_request_threaded_irq(&spi->dev, spi->irq,
  435. NULL,
  436. ad5421_fault_handler,
  437. IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
  438. "ad5421 fault",
  439. indio_dev);
  440. if (ret)
  441. return ret;
  442. }
  443. return devm_iio_device_register(&spi->dev, indio_dev);
  444. }
  445. static struct spi_driver ad5421_driver = {
  446. .driver = {
  447. .name = "ad5421",
  448. },
  449. .probe = ad5421_probe,
  450. };
  451. module_spi_driver(ad5421_driver);
  452. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  453. MODULE_DESCRIPTION("Analog Devices AD5421 DAC");
  454. MODULE_LICENSE("GPL v2");
  455. MODULE_ALIAS("spi:ad5421");