ad5064.c 25 KB

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  1. /*
  2. * AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1, AD5065, AD5625, AD5625R,
  3. * AD5627, AD5627R, AD5628, AD5629R, AD5645R, AD5647R, AD5648, AD5665, AD5665R,
  4. * AD5666, AD5667, AD5667R, AD5668, AD5669R, LTC2606, LTC2607, LTC2609, LTC2616,
  5. * LTC2617, LTC2619, LTC2626, LTC2627, LTC2629 Digital to analog converters
  6. * driver
  7. *
  8. * Copyright 2011 Analog Devices Inc.
  9. *
  10. * Licensed under the GPL-2.
  11. */
  12. #include <linux/device.h>
  13. #include <linux/err.h>
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/i2c.h>
  18. #include <linux/slab.h>
  19. #include <linux/sysfs.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <asm/unaligned.h>
  22. #include <linux/iio/iio.h>
  23. #include <linux/iio/sysfs.h>
  24. #define AD5064_MAX_DAC_CHANNELS 8
  25. #define AD5064_MAX_VREFS 4
  26. #define AD5064_ADDR(x) ((x) << 20)
  27. #define AD5064_CMD(x) ((x) << 24)
  28. #define AD5064_ADDR_ALL_DAC 0xF
  29. #define AD5064_CMD_WRITE_INPUT_N 0x0
  30. #define AD5064_CMD_UPDATE_DAC_N 0x1
  31. #define AD5064_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2
  32. #define AD5064_CMD_WRITE_INPUT_N_UPDATE_N 0x3
  33. #define AD5064_CMD_POWERDOWN_DAC 0x4
  34. #define AD5064_CMD_CLEAR 0x5
  35. #define AD5064_CMD_LDAC_MASK 0x6
  36. #define AD5064_CMD_RESET 0x7
  37. #define AD5064_CMD_CONFIG 0x8
  38. #define AD5064_CMD_RESET_V2 0x5
  39. #define AD5064_CMD_CONFIG_V2 0x7
  40. #define AD5064_CONFIG_DAISY_CHAIN_ENABLE BIT(1)
  41. #define AD5064_CONFIG_INT_VREF_ENABLE BIT(0)
  42. #define AD5064_LDAC_PWRDN_NONE 0x0
  43. #define AD5064_LDAC_PWRDN_1K 0x1
  44. #define AD5064_LDAC_PWRDN_100K 0x2
  45. #define AD5064_LDAC_PWRDN_3STATE 0x3
  46. /**
  47. * enum ad5064_regmap_type - Register layout variant
  48. * @AD5064_REGMAP_ADI: Old Analog Devices register map layout
  49. * @AD5064_REGMAP_ADI2: New Analog Devices register map layout
  50. * @AD5064_REGMAP_LTC: LTC register map layout
  51. */
  52. enum ad5064_regmap_type {
  53. AD5064_REGMAP_ADI,
  54. AD5064_REGMAP_ADI2,
  55. AD5064_REGMAP_LTC,
  56. };
  57. /**
  58. * struct ad5064_chip_info - chip specific information
  59. * @shared_vref: whether the vref supply is shared between channels
  60. * @internal_vref: internal reference voltage. 0 if the chip has no
  61. internal vref.
  62. * @channel: channel specification
  63. * @num_channels: number of channels
  64. * @regmap_type: register map layout variant
  65. */
  66. struct ad5064_chip_info {
  67. bool shared_vref;
  68. unsigned long internal_vref;
  69. const struct iio_chan_spec *channels;
  70. unsigned int num_channels;
  71. enum ad5064_regmap_type regmap_type;
  72. };
  73. struct ad5064_state;
  74. typedef int (*ad5064_write_func)(struct ad5064_state *st, unsigned int cmd,
  75. unsigned int addr, unsigned int val);
  76. /**
  77. * struct ad5064_state - driver instance specific data
  78. * @dev: the device for this driver instance
  79. * @chip_info: chip model specific constants, available modes etc
  80. * @vref_reg: vref supply regulators
  81. * @pwr_down: whether channel is powered down
  82. * @pwr_down_mode: channel's current power down mode
  83. * @dac_cache: current DAC raw value (chip does not support readback)
  84. * @use_internal_vref: set to true if the internal reference voltage should be
  85. * used.
  86. * @write: register write callback
  87. * @data: i2c/spi transfer buffers
  88. */
  89. struct ad5064_state {
  90. struct device *dev;
  91. const struct ad5064_chip_info *chip_info;
  92. struct regulator_bulk_data vref_reg[AD5064_MAX_VREFS];
  93. bool pwr_down[AD5064_MAX_DAC_CHANNELS];
  94. u8 pwr_down_mode[AD5064_MAX_DAC_CHANNELS];
  95. unsigned int dac_cache[AD5064_MAX_DAC_CHANNELS];
  96. bool use_internal_vref;
  97. ad5064_write_func write;
  98. /*
  99. * DMA (thus cache coherency maintenance) requires the
  100. * transfer buffers to live in their own cache lines.
  101. */
  102. union {
  103. u8 i2c[3];
  104. __be32 spi;
  105. } data ____cacheline_aligned;
  106. };
  107. enum ad5064_type {
  108. ID_AD5024,
  109. ID_AD5025,
  110. ID_AD5044,
  111. ID_AD5045,
  112. ID_AD5064,
  113. ID_AD5064_1,
  114. ID_AD5065,
  115. ID_AD5625,
  116. ID_AD5625R_1V25,
  117. ID_AD5625R_2V5,
  118. ID_AD5627,
  119. ID_AD5627R_1V25,
  120. ID_AD5627R_2V5,
  121. ID_AD5628_1,
  122. ID_AD5628_2,
  123. ID_AD5629_1,
  124. ID_AD5629_2,
  125. ID_AD5645R_1V25,
  126. ID_AD5645R_2V5,
  127. ID_AD5647R_1V25,
  128. ID_AD5647R_2V5,
  129. ID_AD5648_1,
  130. ID_AD5648_2,
  131. ID_AD5665,
  132. ID_AD5665R_1V25,
  133. ID_AD5665R_2V5,
  134. ID_AD5666_1,
  135. ID_AD5666_2,
  136. ID_AD5667,
  137. ID_AD5667R_1V25,
  138. ID_AD5667R_2V5,
  139. ID_AD5668_1,
  140. ID_AD5668_2,
  141. ID_AD5669_1,
  142. ID_AD5669_2,
  143. ID_LTC2606,
  144. ID_LTC2607,
  145. ID_LTC2609,
  146. ID_LTC2616,
  147. ID_LTC2617,
  148. ID_LTC2619,
  149. ID_LTC2626,
  150. ID_LTC2627,
  151. ID_LTC2629,
  152. };
  153. static int ad5064_write(struct ad5064_state *st, unsigned int cmd,
  154. unsigned int addr, unsigned int val, unsigned int shift)
  155. {
  156. val <<= shift;
  157. return st->write(st, cmd, addr, val);
  158. }
  159. static int ad5064_sync_powerdown_mode(struct ad5064_state *st,
  160. const struct iio_chan_spec *chan)
  161. {
  162. unsigned int val, address;
  163. unsigned int shift;
  164. int ret;
  165. if (st->chip_info->regmap_type == AD5064_REGMAP_LTC) {
  166. val = 0;
  167. address = chan->address;
  168. } else {
  169. if (st->chip_info->regmap_type == AD5064_REGMAP_ADI2)
  170. shift = 4;
  171. else
  172. shift = 8;
  173. val = (0x1 << chan->address);
  174. address = 0;
  175. if (st->pwr_down[chan->channel])
  176. val |= st->pwr_down_mode[chan->channel] << shift;
  177. }
  178. ret = ad5064_write(st, AD5064_CMD_POWERDOWN_DAC, address, val, 0);
  179. return ret;
  180. }
  181. static const char * const ad5064_powerdown_modes[] = {
  182. "1kohm_to_gnd",
  183. "100kohm_to_gnd",
  184. "three_state",
  185. };
  186. static const char * const ltc2617_powerdown_modes[] = {
  187. "90kohm_to_gnd",
  188. };
  189. static int ad5064_get_powerdown_mode(struct iio_dev *indio_dev,
  190. const struct iio_chan_spec *chan)
  191. {
  192. struct ad5064_state *st = iio_priv(indio_dev);
  193. return st->pwr_down_mode[chan->channel] - 1;
  194. }
  195. static int ad5064_set_powerdown_mode(struct iio_dev *indio_dev,
  196. const struct iio_chan_spec *chan, unsigned int mode)
  197. {
  198. struct ad5064_state *st = iio_priv(indio_dev);
  199. int ret;
  200. mutex_lock(&indio_dev->mlock);
  201. st->pwr_down_mode[chan->channel] = mode + 1;
  202. ret = ad5064_sync_powerdown_mode(st, chan);
  203. mutex_unlock(&indio_dev->mlock);
  204. return ret;
  205. }
  206. static const struct iio_enum ad5064_powerdown_mode_enum = {
  207. .items = ad5064_powerdown_modes,
  208. .num_items = ARRAY_SIZE(ad5064_powerdown_modes),
  209. .get = ad5064_get_powerdown_mode,
  210. .set = ad5064_set_powerdown_mode,
  211. };
  212. static const struct iio_enum ltc2617_powerdown_mode_enum = {
  213. .items = ltc2617_powerdown_modes,
  214. .num_items = ARRAY_SIZE(ltc2617_powerdown_modes),
  215. .get = ad5064_get_powerdown_mode,
  216. .set = ad5064_set_powerdown_mode,
  217. };
  218. static ssize_t ad5064_read_dac_powerdown(struct iio_dev *indio_dev,
  219. uintptr_t private, const struct iio_chan_spec *chan, char *buf)
  220. {
  221. struct ad5064_state *st = iio_priv(indio_dev);
  222. return sprintf(buf, "%d\n", st->pwr_down[chan->channel]);
  223. }
  224. static ssize_t ad5064_write_dac_powerdown(struct iio_dev *indio_dev,
  225. uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
  226. size_t len)
  227. {
  228. struct ad5064_state *st = iio_priv(indio_dev);
  229. bool pwr_down;
  230. int ret;
  231. ret = strtobool(buf, &pwr_down);
  232. if (ret)
  233. return ret;
  234. mutex_lock(&indio_dev->mlock);
  235. st->pwr_down[chan->channel] = pwr_down;
  236. ret = ad5064_sync_powerdown_mode(st, chan);
  237. mutex_unlock(&indio_dev->mlock);
  238. return ret ? ret : len;
  239. }
  240. static int ad5064_get_vref(struct ad5064_state *st,
  241. struct iio_chan_spec const *chan)
  242. {
  243. unsigned int i;
  244. if (st->use_internal_vref)
  245. return st->chip_info->internal_vref;
  246. i = st->chip_info->shared_vref ? 0 : chan->channel;
  247. return regulator_get_voltage(st->vref_reg[i].consumer);
  248. }
  249. static int ad5064_read_raw(struct iio_dev *indio_dev,
  250. struct iio_chan_spec const *chan,
  251. int *val,
  252. int *val2,
  253. long m)
  254. {
  255. struct ad5064_state *st = iio_priv(indio_dev);
  256. int scale_uv;
  257. switch (m) {
  258. case IIO_CHAN_INFO_RAW:
  259. *val = st->dac_cache[chan->channel];
  260. return IIO_VAL_INT;
  261. case IIO_CHAN_INFO_SCALE:
  262. scale_uv = ad5064_get_vref(st, chan);
  263. if (scale_uv < 0)
  264. return scale_uv;
  265. *val = scale_uv / 1000;
  266. *val2 = chan->scan_type.realbits;
  267. return IIO_VAL_FRACTIONAL_LOG2;
  268. default:
  269. break;
  270. }
  271. return -EINVAL;
  272. }
  273. static int ad5064_write_raw(struct iio_dev *indio_dev,
  274. struct iio_chan_spec const *chan, int val, int val2, long mask)
  275. {
  276. struct ad5064_state *st = iio_priv(indio_dev);
  277. int ret;
  278. switch (mask) {
  279. case IIO_CHAN_INFO_RAW:
  280. if (val >= (1 << chan->scan_type.realbits) || val < 0)
  281. return -EINVAL;
  282. mutex_lock(&indio_dev->mlock);
  283. ret = ad5064_write(st, AD5064_CMD_WRITE_INPUT_N_UPDATE_N,
  284. chan->address, val, chan->scan_type.shift);
  285. if (ret == 0)
  286. st->dac_cache[chan->channel] = val;
  287. mutex_unlock(&indio_dev->mlock);
  288. break;
  289. default:
  290. ret = -EINVAL;
  291. }
  292. return ret;
  293. }
  294. static const struct iio_info ad5064_info = {
  295. .read_raw = ad5064_read_raw,
  296. .write_raw = ad5064_write_raw,
  297. .driver_module = THIS_MODULE,
  298. };
  299. static const struct iio_chan_spec_ext_info ad5064_ext_info[] = {
  300. {
  301. .name = "powerdown",
  302. .read = ad5064_read_dac_powerdown,
  303. .write = ad5064_write_dac_powerdown,
  304. .shared = IIO_SEPARATE,
  305. },
  306. IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5064_powerdown_mode_enum),
  307. IIO_ENUM_AVAILABLE("powerdown_mode", &ad5064_powerdown_mode_enum),
  308. { },
  309. };
  310. static const struct iio_chan_spec_ext_info ltc2617_ext_info[] = {
  311. {
  312. .name = "powerdown",
  313. .read = ad5064_read_dac_powerdown,
  314. .write = ad5064_write_dac_powerdown,
  315. .shared = IIO_SEPARATE,
  316. },
  317. IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ltc2617_powerdown_mode_enum),
  318. IIO_ENUM_AVAILABLE("powerdown_mode", &ltc2617_powerdown_mode_enum),
  319. { },
  320. };
  321. #define AD5064_CHANNEL(chan, addr, bits, _shift, _ext_info) { \
  322. .type = IIO_VOLTAGE, \
  323. .indexed = 1, \
  324. .output = 1, \
  325. .channel = (chan), \
  326. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  327. BIT(IIO_CHAN_INFO_SCALE), \
  328. .address = addr, \
  329. .scan_type = { \
  330. .sign = 'u', \
  331. .realbits = (bits), \
  332. .storagebits = 16, \
  333. .shift = (_shift), \
  334. }, \
  335. .ext_info = (_ext_info), \
  336. }
  337. #define DECLARE_AD5064_CHANNELS(name, bits, shift, ext_info) \
  338. const struct iio_chan_spec name[] = { \
  339. AD5064_CHANNEL(0, 0, bits, shift, ext_info), \
  340. AD5064_CHANNEL(1, 1, bits, shift, ext_info), \
  341. AD5064_CHANNEL(2, 2, bits, shift, ext_info), \
  342. AD5064_CHANNEL(3, 3, bits, shift, ext_info), \
  343. AD5064_CHANNEL(4, 4, bits, shift, ext_info), \
  344. AD5064_CHANNEL(5, 5, bits, shift, ext_info), \
  345. AD5064_CHANNEL(6, 6, bits, shift, ext_info), \
  346. AD5064_CHANNEL(7, 7, bits, shift, ext_info), \
  347. }
  348. #define DECLARE_AD5065_CHANNELS(name, bits, shift, ext_info) \
  349. const struct iio_chan_spec name[] = { \
  350. AD5064_CHANNEL(0, 0, bits, shift, ext_info), \
  351. AD5064_CHANNEL(1, 3, bits, shift, ext_info), \
  352. }
  353. static DECLARE_AD5064_CHANNELS(ad5024_channels, 12, 8, ad5064_ext_info);
  354. static DECLARE_AD5064_CHANNELS(ad5044_channels, 14, 6, ad5064_ext_info);
  355. static DECLARE_AD5064_CHANNELS(ad5064_channels, 16, 4, ad5064_ext_info);
  356. static DECLARE_AD5065_CHANNELS(ad5025_channels, 12, 8, ad5064_ext_info);
  357. static DECLARE_AD5065_CHANNELS(ad5045_channels, 14, 6, ad5064_ext_info);
  358. static DECLARE_AD5065_CHANNELS(ad5065_channels, 16, 4, ad5064_ext_info);
  359. static DECLARE_AD5064_CHANNELS(ad5629_channels, 12, 4, ad5064_ext_info);
  360. static DECLARE_AD5064_CHANNELS(ad5645_channels, 14, 2, ad5064_ext_info);
  361. static DECLARE_AD5064_CHANNELS(ad5669_channels, 16, 0, ad5064_ext_info);
  362. static DECLARE_AD5064_CHANNELS(ltc2607_channels, 16, 0, ltc2617_ext_info);
  363. static DECLARE_AD5064_CHANNELS(ltc2617_channels, 14, 2, ltc2617_ext_info);
  364. static DECLARE_AD5064_CHANNELS(ltc2627_channels, 12, 4, ltc2617_ext_info);
  365. static const struct ad5064_chip_info ad5064_chip_info_tbl[] = {
  366. [ID_AD5024] = {
  367. .shared_vref = false,
  368. .channels = ad5024_channels,
  369. .num_channels = 4,
  370. .regmap_type = AD5064_REGMAP_ADI,
  371. },
  372. [ID_AD5025] = {
  373. .shared_vref = false,
  374. .channels = ad5025_channels,
  375. .num_channels = 2,
  376. .regmap_type = AD5064_REGMAP_ADI,
  377. },
  378. [ID_AD5044] = {
  379. .shared_vref = false,
  380. .channels = ad5044_channels,
  381. .num_channels = 4,
  382. .regmap_type = AD5064_REGMAP_ADI,
  383. },
  384. [ID_AD5045] = {
  385. .shared_vref = false,
  386. .channels = ad5045_channels,
  387. .num_channels = 2,
  388. .regmap_type = AD5064_REGMAP_ADI,
  389. },
  390. [ID_AD5064] = {
  391. .shared_vref = false,
  392. .channels = ad5064_channels,
  393. .num_channels = 4,
  394. .regmap_type = AD5064_REGMAP_ADI,
  395. },
  396. [ID_AD5064_1] = {
  397. .shared_vref = true,
  398. .channels = ad5064_channels,
  399. .num_channels = 4,
  400. .regmap_type = AD5064_REGMAP_ADI,
  401. },
  402. [ID_AD5065] = {
  403. .shared_vref = false,
  404. .channels = ad5065_channels,
  405. .num_channels = 2,
  406. .regmap_type = AD5064_REGMAP_ADI,
  407. },
  408. [ID_AD5625] = {
  409. .shared_vref = true,
  410. .channels = ad5629_channels,
  411. .num_channels = 4,
  412. .regmap_type = AD5064_REGMAP_ADI2
  413. },
  414. [ID_AD5625R_1V25] = {
  415. .shared_vref = true,
  416. .internal_vref = 1250000,
  417. .channels = ad5629_channels,
  418. .num_channels = 4,
  419. .regmap_type = AD5064_REGMAP_ADI2
  420. },
  421. [ID_AD5625R_2V5] = {
  422. .shared_vref = true,
  423. .internal_vref = 2500000,
  424. .channels = ad5629_channels,
  425. .num_channels = 4,
  426. .regmap_type = AD5064_REGMAP_ADI2
  427. },
  428. [ID_AD5627] = {
  429. .shared_vref = true,
  430. .channels = ad5629_channels,
  431. .num_channels = 2,
  432. .regmap_type = AD5064_REGMAP_ADI2
  433. },
  434. [ID_AD5627R_1V25] = {
  435. .shared_vref = true,
  436. .internal_vref = 1250000,
  437. .channels = ad5629_channels,
  438. .num_channels = 2,
  439. .regmap_type = AD5064_REGMAP_ADI2
  440. },
  441. [ID_AD5627R_2V5] = {
  442. .shared_vref = true,
  443. .internal_vref = 2500000,
  444. .channels = ad5629_channels,
  445. .num_channels = 2,
  446. .regmap_type = AD5064_REGMAP_ADI2
  447. },
  448. [ID_AD5628_1] = {
  449. .shared_vref = true,
  450. .internal_vref = 2500000,
  451. .channels = ad5024_channels,
  452. .num_channels = 8,
  453. .regmap_type = AD5064_REGMAP_ADI,
  454. },
  455. [ID_AD5628_2] = {
  456. .shared_vref = true,
  457. .internal_vref = 5000000,
  458. .channels = ad5024_channels,
  459. .num_channels = 8,
  460. .regmap_type = AD5064_REGMAP_ADI,
  461. },
  462. [ID_AD5629_1] = {
  463. .shared_vref = true,
  464. .internal_vref = 2500000,
  465. .channels = ad5629_channels,
  466. .num_channels = 8,
  467. .regmap_type = AD5064_REGMAP_ADI,
  468. },
  469. [ID_AD5629_2] = {
  470. .shared_vref = true,
  471. .internal_vref = 5000000,
  472. .channels = ad5629_channels,
  473. .num_channels = 8,
  474. .regmap_type = AD5064_REGMAP_ADI,
  475. },
  476. [ID_AD5645R_1V25] = {
  477. .shared_vref = true,
  478. .internal_vref = 1250000,
  479. .channels = ad5645_channels,
  480. .num_channels = 4,
  481. .regmap_type = AD5064_REGMAP_ADI2
  482. },
  483. [ID_AD5645R_2V5] = {
  484. .shared_vref = true,
  485. .internal_vref = 2500000,
  486. .channels = ad5645_channels,
  487. .num_channels = 4,
  488. .regmap_type = AD5064_REGMAP_ADI2
  489. },
  490. [ID_AD5647R_1V25] = {
  491. .shared_vref = true,
  492. .internal_vref = 1250000,
  493. .channels = ad5645_channels,
  494. .num_channels = 2,
  495. .regmap_type = AD5064_REGMAP_ADI2
  496. },
  497. [ID_AD5647R_2V5] = {
  498. .shared_vref = true,
  499. .internal_vref = 2500000,
  500. .channels = ad5645_channels,
  501. .num_channels = 2,
  502. .regmap_type = AD5064_REGMAP_ADI2
  503. },
  504. [ID_AD5648_1] = {
  505. .shared_vref = true,
  506. .internal_vref = 2500000,
  507. .channels = ad5044_channels,
  508. .num_channels = 8,
  509. .regmap_type = AD5064_REGMAP_ADI,
  510. },
  511. [ID_AD5648_2] = {
  512. .shared_vref = true,
  513. .internal_vref = 5000000,
  514. .channels = ad5044_channels,
  515. .num_channels = 8,
  516. .regmap_type = AD5064_REGMAP_ADI,
  517. },
  518. [ID_AD5665] = {
  519. .shared_vref = true,
  520. .channels = ad5669_channels,
  521. .num_channels = 4,
  522. .regmap_type = AD5064_REGMAP_ADI2
  523. },
  524. [ID_AD5665R_1V25] = {
  525. .shared_vref = true,
  526. .internal_vref = 1250000,
  527. .channels = ad5669_channels,
  528. .num_channels = 4,
  529. .regmap_type = AD5064_REGMAP_ADI2
  530. },
  531. [ID_AD5665R_2V5] = {
  532. .shared_vref = true,
  533. .internal_vref = 2500000,
  534. .channels = ad5669_channels,
  535. .num_channels = 4,
  536. .regmap_type = AD5064_REGMAP_ADI2
  537. },
  538. [ID_AD5666_1] = {
  539. .shared_vref = true,
  540. .internal_vref = 2500000,
  541. .channels = ad5064_channels,
  542. .num_channels = 4,
  543. .regmap_type = AD5064_REGMAP_ADI,
  544. },
  545. [ID_AD5666_2] = {
  546. .shared_vref = true,
  547. .internal_vref = 5000000,
  548. .channels = ad5064_channels,
  549. .num_channels = 4,
  550. .regmap_type = AD5064_REGMAP_ADI,
  551. },
  552. [ID_AD5667] = {
  553. .shared_vref = true,
  554. .channels = ad5669_channels,
  555. .num_channels = 2,
  556. .regmap_type = AD5064_REGMAP_ADI2
  557. },
  558. [ID_AD5667R_1V25] = {
  559. .shared_vref = true,
  560. .internal_vref = 1250000,
  561. .channels = ad5669_channels,
  562. .num_channels = 2,
  563. .regmap_type = AD5064_REGMAP_ADI2
  564. },
  565. [ID_AD5667R_2V5] = {
  566. .shared_vref = true,
  567. .internal_vref = 2500000,
  568. .channels = ad5669_channels,
  569. .num_channels = 2,
  570. .regmap_type = AD5064_REGMAP_ADI2
  571. },
  572. [ID_AD5668_1] = {
  573. .shared_vref = true,
  574. .internal_vref = 2500000,
  575. .channels = ad5064_channels,
  576. .num_channels = 8,
  577. .regmap_type = AD5064_REGMAP_ADI,
  578. },
  579. [ID_AD5668_2] = {
  580. .shared_vref = true,
  581. .internal_vref = 5000000,
  582. .channels = ad5064_channels,
  583. .num_channels = 8,
  584. .regmap_type = AD5064_REGMAP_ADI,
  585. },
  586. [ID_AD5669_1] = {
  587. .shared_vref = true,
  588. .internal_vref = 2500000,
  589. .channels = ad5669_channels,
  590. .num_channels = 8,
  591. .regmap_type = AD5064_REGMAP_ADI,
  592. },
  593. [ID_AD5669_2] = {
  594. .shared_vref = true,
  595. .internal_vref = 5000000,
  596. .channels = ad5669_channels,
  597. .num_channels = 8,
  598. .regmap_type = AD5064_REGMAP_ADI,
  599. },
  600. [ID_LTC2606] = {
  601. .shared_vref = true,
  602. .internal_vref = 0,
  603. .channels = ltc2607_channels,
  604. .num_channels = 1,
  605. .regmap_type = AD5064_REGMAP_LTC,
  606. },
  607. [ID_LTC2607] = {
  608. .shared_vref = true,
  609. .internal_vref = 0,
  610. .channels = ltc2607_channels,
  611. .num_channels = 2,
  612. .regmap_type = AD5064_REGMAP_LTC,
  613. },
  614. [ID_LTC2609] = {
  615. .shared_vref = false,
  616. .internal_vref = 0,
  617. .channels = ltc2607_channels,
  618. .num_channels = 4,
  619. .regmap_type = AD5064_REGMAP_LTC,
  620. },
  621. [ID_LTC2616] = {
  622. .shared_vref = true,
  623. .internal_vref = 0,
  624. .channels = ltc2617_channels,
  625. .num_channels = 1,
  626. .regmap_type = AD5064_REGMAP_LTC,
  627. },
  628. [ID_LTC2617] = {
  629. .shared_vref = true,
  630. .internal_vref = 0,
  631. .channels = ltc2617_channels,
  632. .num_channels = 2,
  633. .regmap_type = AD5064_REGMAP_LTC,
  634. },
  635. [ID_LTC2619] = {
  636. .shared_vref = false,
  637. .internal_vref = 0,
  638. .channels = ltc2617_channels,
  639. .num_channels = 4,
  640. .regmap_type = AD5064_REGMAP_LTC,
  641. },
  642. [ID_LTC2626] = {
  643. .shared_vref = true,
  644. .internal_vref = 0,
  645. .channels = ltc2627_channels,
  646. .num_channels = 1,
  647. .regmap_type = AD5064_REGMAP_LTC,
  648. },
  649. [ID_LTC2627] = {
  650. .shared_vref = true,
  651. .internal_vref = 0,
  652. .channels = ltc2627_channels,
  653. .num_channels = 2,
  654. .regmap_type = AD5064_REGMAP_LTC,
  655. },
  656. [ID_LTC2629] = {
  657. .shared_vref = false,
  658. .internal_vref = 0,
  659. .channels = ltc2627_channels,
  660. .num_channels = 4,
  661. .regmap_type = AD5064_REGMAP_LTC,
  662. },
  663. };
  664. static inline unsigned int ad5064_num_vref(struct ad5064_state *st)
  665. {
  666. return st->chip_info->shared_vref ? 1 : st->chip_info->num_channels;
  667. }
  668. static const char * const ad5064_vref_names[] = {
  669. "vrefA",
  670. "vrefB",
  671. "vrefC",
  672. "vrefD",
  673. };
  674. static const char * const ad5064_vref_name(struct ad5064_state *st,
  675. unsigned int vref)
  676. {
  677. return st->chip_info->shared_vref ? "vref" : ad5064_vref_names[vref];
  678. }
  679. static int ad5064_set_config(struct ad5064_state *st, unsigned int val)
  680. {
  681. unsigned int cmd;
  682. switch (st->chip_info->regmap_type) {
  683. case AD5064_REGMAP_ADI2:
  684. cmd = AD5064_CMD_CONFIG_V2;
  685. break;
  686. default:
  687. cmd = AD5064_CMD_CONFIG;
  688. break;
  689. }
  690. return ad5064_write(st, cmd, 0, val, 0);
  691. }
  692. static int ad5064_probe(struct device *dev, enum ad5064_type type,
  693. const char *name, ad5064_write_func write)
  694. {
  695. struct iio_dev *indio_dev;
  696. struct ad5064_state *st;
  697. unsigned int midscale;
  698. unsigned int i;
  699. int ret;
  700. indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
  701. if (indio_dev == NULL)
  702. return -ENOMEM;
  703. st = iio_priv(indio_dev);
  704. dev_set_drvdata(dev, indio_dev);
  705. st->chip_info = &ad5064_chip_info_tbl[type];
  706. st->dev = dev;
  707. st->write = write;
  708. for (i = 0; i < ad5064_num_vref(st); ++i)
  709. st->vref_reg[i].supply = ad5064_vref_name(st, i);
  710. ret = devm_regulator_bulk_get(dev, ad5064_num_vref(st),
  711. st->vref_reg);
  712. if (ret) {
  713. if (!st->chip_info->internal_vref)
  714. return ret;
  715. st->use_internal_vref = true;
  716. ret = ad5064_set_config(st, AD5064_CONFIG_INT_VREF_ENABLE);
  717. if (ret) {
  718. dev_err(dev, "Failed to enable internal vref: %d\n",
  719. ret);
  720. return ret;
  721. }
  722. } else {
  723. ret = regulator_bulk_enable(ad5064_num_vref(st), st->vref_reg);
  724. if (ret)
  725. return ret;
  726. }
  727. indio_dev->dev.parent = dev;
  728. indio_dev->name = name;
  729. indio_dev->info = &ad5064_info;
  730. indio_dev->modes = INDIO_DIRECT_MODE;
  731. indio_dev->channels = st->chip_info->channels;
  732. indio_dev->num_channels = st->chip_info->num_channels;
  733. midscale = (1 << indio_dev->channels[0].scan_type.realbits) / 2;
  734. for (i = 0; i < st->chip_info->num_channels; ++i) {
  735. st->pwr_down_mode[i] = AD5064_LDAC_PWRDN_1K;
  736. st->dac_cache[i] = midscale;
  737. }
  738. ret = iio_device_register(indio_dev);
  739. if (ret)
  740. goto error_disable_reg;
  741. return 0;
  742. error_disable_reg:
  743. if (!st->use_internal_vref)
  744. regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
  745. return ret;
  746. }
  747. static int ad5064_remove(struct device *dev)
  748. {
  749. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  750. struct ad5064_state *st = iio_priv(indio_dev);
  751. iio_device_unregister(indio_dev);
  752. if (!st->use_internal_vref)
  753. regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
  754. return 0;
  755. }
  756. #if IS_ENABLED(CONFIG_SPI_MASTER)
  757. static int ad5064_spi_write(struct ad5064_state *st, unsigned int cmd,
  758. unsigned int addr, unsigned int val)
  759. {
  760. struct spi_device *spi = to_spi_device(st->dev);
  761. st->data.spi = cpu_to_be32(AD5064_CMD(cmd) | AD5064_ADDR(addr) | val);
  762. return spi_write(spi, &st->data.spi, sizeof(st->data.spi));
  763. }
  764. static int ad5064_spi_probe(struct spi_device *spi)
  765. {
  766. const struct spi_device_id *id = spi_get_device_id(spi);
  767. return ad5064_probe(&spi->dev, id->driver_data, id->name,
  768. ad5064_spi_write);
  769. }
  770. static int ad5064_spi_remove(struct spi_device *spi)
  771. {
  772. return ad5064_remove(&spi->dev);
  773. }
  774. static const struct spi_device_id ad5064_spi_ids[] = {
  775. {"ad5024", ID_AD5024},
  776. {"ad5025", ID_AD5025},
  777. {"ad5044", ID_AD5044},
  778. {"ad5045", ID_AD5045},
  779. {"ad5064", ID_AD5064},
  780. {"ad5064-1", ID_AD5064_1},
  781. {"ad5065", ID_AD5065},
  782. {"ad5628-1", ID_AD5628_1},
  783. {"ad5628-2", ID_AD5628_2},
  784. {"ad5648-1", ID_AD5648_1},
  785. {"ad5648-2", ID_AD5648_2},
  786. {"ad5666-1", ID_AD5666_1},
  787. {"ad5666-2", ID_AD5666_2},
  788. {"ad5668-1", ID_AD5668_1},
  789. {"ad5668-2", ID_AD5668_2},
  790. {"ad5668-3", ID_AD5668_2}, /* similar enough to ad5668-2 */
  791. {}
  792. };
  793. MODULE_DEVICE_TABLE(spi, ad5064_spi_ids);
  794. static struct spi_driver ad5064_spi_driver = {
  795. .driver = {
  796. .name = "ad5064",
  797. },
  798. .probe = ad5064_spi_probe,
  799. .remove = ad5064_spi_remove,
  800. .id_table = ad5064_spi_ids,
  801. };
  802. static int __init ad5064_spi_register_driver(void)
  803. {
  804. return spi_register_driver(&ad5064_spi_driver);
  805. }
  806. static void ad5064_spi_unregister_driver(void)
  807. {
  808. spi_unregister_driver(&ad5064_spi_driver);
  809. }
  810. #else
  811. static inline int ad5064_spi_register_driver(void) { return 0; }
  812. static inline void ad5064_spi_unregister_driver(void) { }
  813. #endif
  814. #if IS_ENABLED(CONFIG_I2C)
  815. static int ad5064_i2c_write(struct ad5064_state *st, unsigned int cmd,
  816. unsigned int addr, unsigned int val)
  817. {
  818. struct i2c_client *i2c = to_i2c_client(st->dev);
  819. unsigned int cmd_shift;
  820. int ret;
  821. switch (st->chip_info->regmap_type) {
  822. case AD5064_REGMAP_ADI2:
  823. cmd_shift = 3;
  824. break;
  825. default:
  826. cmd_shift = 4;
  827. break;
  828. }
  829. st->data.i2c[0] = (cmd << cmd_shift) | addr;
  830. put_unaligned_be16(val, &st->data.i2c[1]);
  831. ret = i2c_master_send(i2c, st->data.i2c, 3);
  832. if (ret < 0)
  833. return ret;
  834. return 0;
  835. }
  836. static int ad5064_i2c_probe(struct i2c_client *i2c,
  837. const struct i2c_device_id *id)
  838. {
  839. return ad5064_probe(&i2c->dev, id->driver_data, id->name,
  840. ad5064_i2c_write);
  841. }
  842. static int ad5064_i2c_remove(struct i2c_client *i2c)
  843. {
  844. return ad5064_remove(&i2c->dev);
  845. }
  846. static const struct i2c_device_id ad5064_i2c_ids[] = {
  847. {"ad5625", ID_AD5625 },
  848. {"ad5625r-1v25", ID_AD5625R_1V25 },
  849. {"ad5625r-2v5", ID_AD5625R_2V5 },
  850. {"ad5627", ID_AD5627 },
  851. {"ad5627r-1v25", ID_AD5627R_1V25 },
  852. {"ad5627r-2v5", ID_AD5627R_2V5 },
  853. {"ad5629-1", ID_AD5629_1},
  854. {"ad5629-2", ID_AD5629_2},
  855. {"ad5629-3", ID_AD5629_2}, /* similar enough to ad5629-2 */
  856. {"ad5645r-1v25", ID_AD5645R_1V25 },
  857. {"ad5645r-2v5", ID_AD5645R_2V5 },
  858. {"ad5665", ID_AD5665 },
  859. {"ad5665r-1v25", ID_AD5665R_1V25 },
  860. {"ad5665r-2v5", ID_AD5665R_2V5 },
  861. {"ad5667", ID_AD5667 },
  862. {"ad5667r-1v25", ID_AD5667R_1V25 },
  863. {"ad5667r-2v5", ID_AD5667R_2V5 },
  864. {"ad5669-1", ID_AD5669_1},
  865. {"ad5669-2", ID_AD5669_2},
  866. {"ad5669-3", ID_AD5669_2}, /* similar enough to ad5669-2 */
  867. {"ltc2606", ID_LTC2606},
  868. {"ltc2607", ID_LTC2607},
  869. {"ltc2609", ID_LTC2609},
  870. {"ltc2616", ID_LTC2616},
  871. {"ltc2617", ID_LTC2617},
  872. {"ltc2619", ID_LTC2619},
  873. {"ltc2626", ID_LTC2626},
  874. {"ltc2627", ID_LTC2627},
  875. {"ltc2629", ID_LTC2629},
  876. {}
  877. };
  878. MODULE_DEVICE_TABLE(i2c, ad5064_i2c_ids);
  879. static struct i2c_driver ad5064_i2c_driver = {
  880. .driver = {
  881. .name = "ad5064",
  882. },
  883. .probe = ad5064_i2c_probe,
  884. .remove = ad5064_i2c_remove,
  885. .id_table = ad5064_i2c_ids,
  886. };
  887. static int __init ad5064_i2c_register_driver(void)
  888. {
  889. return i2c_add_driver(&ad5064_i2c_driver);
  890. }
  891. static void __exit ad5064_i2c_unregister_driver(void)
  892. {
  893. i2c_del_driver(&ad5064_i2c_driver);
  894. }
  895. #else
  896. static inline int ad5064_i2c_register_driver(void) { return 0; }
  897. static inline void ad5064_i2c_unregister_driver(void) { }
  898. #endif
  899. static int __init ad5064_init(void)
  900. {
  901. int ret;
  902. ret = ad5064_spi_register_driver();
  903. if (ret)
  904. return ret;
  905. ret = ad5064_i2c_register_driver();
  906. if (ret) {
  907. ad5064_spi_unregister_driver();
  908. return ret;
  909. }
  910. return 0;
  911. }
  912. module_init(ad5064_init);
  913. static void __exit ad5064_exit(void)
  914. {
  915. ad5064_i2c_unregister_driver();
  916. ad5064_spi_unregister_driver();
  917. }
  918. module_exit(ad5064_exit);
  919. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  920. MODULE_DESCRIPTION("Analog Devices AD5024 and similar multi-channel DACs");
  921. MODULE_LICENSE("GPL v2");