ina2xx-adc.c 18 KB

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  1. /*
  2. * INA2XX Current and Power Monitors
  3. *
  4. * Copyright 2015 Baylibre SAS.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Based on linux/drivers/iio/adc/ad7291.c
  11. * Copyright 2010-2011 Analog Devices Inc.
  12. *
  13. * Based on linux/drivers/hwmon/ina2xx.c
  14. * Copyright 2012 Lothar Felten <l-felten@ti.com>
  15. *
  16. * Licensed under the GPL-2 or later.
  17. *
  18. * IIO driver for INA219-220-226-230-231
  19. *
  20. * Configurable 7-bit I2C slave address from 0x40 to 0x4F
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/i2c.h>
  24. #include <linux/iio/kfifo_buf.h>
  25. #include <linux/iio/sysfs.h>
  26. #include <linux/kthread.h>
  27. #include <linux/module.h>
  28. #include <linux/regmap.h>
  29. #include <linux/util_macros.h>
  30. #include <linux/platform_data/ina2xx.h>
  31. /* INA2XX registers definition */
  32. #define INA2XX_CONFIG 0x00
  33. #define INA2XX_SHUNT_VOLTAGE 0x01 /* readonly */
  34. #define INA2XX_BUS_VOLTAGE 0x02 /* readonly */
  35. #define INA2XX_POWER 0x03 /* readonly */
  36. #define INA2XX_CURRENT 0x04 /* readonly */
  37. #define INA2XX_CALIBRATION 0x05
  38. #define INA226_ALERT_MASK GENMASK(2, 1)
  39. #define INA266_CVRF BIT(3)
  40. #define INA2XX_MAX_REGISTERS 8
  41. /* settings - depend on use case */
  42. #define INA219_CONFIG_DEFAULT 0x399F /* PGA=8 */
  43. #define INA226_CONFIG_DEFAULT 0x4327
  44. #define INA226_DEFAULT_AVG 4
  45. #define INA226_DEFAULT_IT 1110
  46. #define INA2XX_RSHUNT_DEFAULT 10000
  47. /*
  48. * bit mask for reading the averaging setting in the configuration register
  49. * FIXME: use regmap_fields.
  50. */
  51. #define INA2XX_MODE_MASK GENMASK(3, 0)
  52. #define INA226_AVG_MASK GENMASK(11, 9)
  53. #define INA226_SHIFT_AVG(val) ((val) << 9)
  54. /* Integration time for VBus */
  55. #define INA226_ITB_MASK GENMASK(8, 6)
  56. #define INA226_SHIFT_ITB(val) ((val) << 6)
  57. /* Integration time for VShunt */
  58. #define INA226_ITS_MASK GENMASK(5, 3)
  59. #define INA226_SHIFT_ITS(val) ((val) << 3)
  60. /* Cosmetic macro giving the sampling period for a full P=UxI cycle */
  61. #define SAMPLING_PERIOD(c) ((c->int_time_vbus + c->int_time_vshunt) \
  62. * c->avg)
  63. static bool ina2xx_is_writeable_reg(struct device *dev, unsigned int reg)
  64. {
  65. return (reg == INA2XX_CONFIG) || (reg > INA2XX_CURRENT);
  66. }
  67. static bool ina2xx_is_volatile_reg(struct device *dev, unsigned int reg)
  68. {
  69. return (reg != INA2XX_CONFIG);
  70. }
  71. static inline bool is_signed_reg(unsigned int reg)
  72. {
  73. return (reg == INA2XX_SHUNT_VOLTAGE) || (reg == INA2XX_CURRENT);
  74. }
  75. static const struct regmap_config ina2xx_regmap_config = {
  76. .reg_bits = 8,
  77. .val_bits = 16,
  78. .max_register = INA2XX_MAX_REGISTERS,
  79. .writeable_reg = ina2xx_is_writeable_reg,
  80. .volatile_reg = ina2xx_is_volatile_reg,
  81. };
  82. enum ina2xx_ids { ina219, ina226 };
  83. struct ina2xx_config {
  84. u16 config_default;
  85. int calibration_factor;
  86. int shunt_div;
  87. int bus_voltage_shift;
  88. int bus_voltage_lsb; /* uV */
  89. int power_lsb; /* uW */
  90. };
  91. struct ina2xx_chip_info {
  92. struct regmap *regmap;
  93. struct task_struct *task;
  94. const struct ina2xx_config *config;
  95. struct mutex state_lock;
  96. unsigned int shunt_resistor;
  97. int avg;
  98. int int_time_vbus; /* Bus voltage integration time uS */
  99. int int_time_vshunt; /* Shunt voltage integration time uS */
  100. bool allow_async_readout;
  101. };
  102. static const struct ina2xx_config ina2xx_config[] = {
  103. [ina219] = {
  104. .config_default = INA219_CONFIG_DEFAULT,
  105. .calibration_factor = 40960000,
  106. .shunt_div = 100,
  107. .bus_voltage_shift = 3,
  108. .bus_voltage_lsb = 4000,
  109. .power_lsb = 20000,
  110. },
  111. [ina226] = {
  112. .config_default = INA226_CONFIG_DEFAULT,
  113. .calibration_factor = 5120000,
  114. .shunt_div = 400,
  115. .bus_voltage_shift = 0,
  116. .bus_voltage_lsb = 1250,
  117. .power_lsb = 25000,
  118. },
  119. };
  120. static int ina2xx_read_raw(struct iio_dev *indio_dev,
  121. struct iio_chan_spec const *chan,
  122. int *val, int *val2, long mask)
  123. {
  124. int ret;
  125. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  126. unsigned int regval;
  127. switch (mask) {
  128. case IIO_CHAN_INFO_RAW:
  129. ret = regmap_read(chip->regmap, chan->address, &regval);
  130. if (ret)
  131. return ret;
  132. if (is_signed_reg(chan->address))
  133. *val = (s16) regval;
  134. else
  135. *val = regval;
  136. return IIO_VAL_INT;
  137. case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
  138. *val = chip->avg;
  139. return IIO_VAL_INT;
  140. case IIO_CHAN_INFO_INT_TIME:
  141. *val = 0;
  142. if (chan->address == INA2XX_SHUNT_VOLTAGE)
  143. *val2 = chip->int_time_vshunt;
  144. else
  145. *val2 = chip->int_time_vbus;
  146. return IIO_VAL_INT_PLUS_MICRO;
  147. case IIO_CHAN_INFO_SAMP_FREQ:
  148. /*
  149. * Sample freq is read only, it is a consequence of
  150. * 1/AVG*(CT_bus+CT_shunt).
  151. */
  152. *val = DIV_ROUND_CLOSEST(1000000, SAMPLING_PERIOD(chip));
  153. return IIO_VAL_INT;
  154. case IIO_CHAN_INFO_SCALE:
  155. switch (chan->address) {
  156. case INA2XX_SHUNT_VOLTAGE:
  157. /* processed (mV) = raw/shunt_div */
  158. *val2 = chip->config->shunt_div;
  159. *val = 1;
  160. return IIO_VAL_FRACTIONAL;
  161. case INA2XX_BUS_VOLTAGE:
  162. /* processed (mV) = raw*lsb (uV) / (1000 << shift) */
  163. *val = chip->config->bus_voltage_lsb;
  164. *val2 = 1000 << chip->config->bus_voltage_shift;
  165. return IIO_VAL_FRACTIONAL;
  166. case INA2XX_POWER:
  167. /* processed (mW) = raw*lsb (uW) / 1000 */
  168. *val = chip->config->power_lsb;
  169. *val2 = 1000;
  170. return IIO_VAL_FRACTIONAL;
  171. case INA2XX_CURRENT:
  172. /* processed (mA) = raw (mA) */
  173. *val = 1;
  174. return IIO_VAL_INT;
  175. }
  176. }
  177. return -EINVAL;
  178. }
  179. /*
  180. * Available averaging rates for ina226. The indices correspond with
  181. * the bit values expected by the chip (according to the ina226 datasheet,
  182. * table 3 AVG bit settings, found at
  183. * http://www.ti.com/lit/ds/symlink/ina226.pdf.
  184. */
  185. static const int ina226_avg_tab[] = { 1, 4, 16, 64, 128, 256, 512, 1024 };
  186. static int ina226_set_average(struct ina2xx_chip_info *chip, unsigned int val,
  187. unsigned int *config)
  188. {
  189. int bits;
  190. if (val > 1024 || val < 1)
  191. return -EINVAL;
  192. bits = find_closest(val, ina226_avg_tab,
  193. ARRAY_SIZE(ina226_avg_tab));
  194. chip->avg = ina226_avg_tab[bits];
  195. *config &= ~INA226_AVG_MASK;
  196. *config |= INA226_SHIFT_AVG(bits) & INA226_AVG_MASK;
  197. return 0;
  198. }
  199. /* Conversion times in uS */
  200. static const int ina226_conv_time_tab[] = { 140, 204, 332, 588, 1100,
  201. 2116, 4156, 8244 };
  202. static int ina226_set_int_time_vbus(struct ina2xx_chip_info *chip,
  203. unsigned int val_us, unsigned int *config)
  204. {
  205. int bits;
  206. if (val_us > 8244 || val_us < 140)
  207. return -EINVAL;
  208. bits = find_closest(val_us, ina226_conv_time_tab,
  209. ARRAY_SIZE(ina226_conv_time_tab));
  210. chip->int_time_vbus = ina226_conv_time_tab[bits];
  211. *config &= ~INA226_ITB_MASK;
  212. *config |= INA226_SHIFT_ITB(bits) & INA226_ITB_MASK;
  213. return 0;
  214. }
  215. static int ina226_set_int_time_vshunt(struct ina2xx_chip_info *chip,
  216. unsigned int val_us, unsigned int *config)
  217. {
  218. int bits;
  219. if (val_us > 8244 || val_us < 140)
  220. return -EINVAL;
  221. bits = find_closest(val_us, ina226_conv_time_tab,
  222. ARRAY_SIZE(ina226_conv_time_tab));
  223. chip->int_time_vshunt = ina226_conv_time_tab[bits];
  224. *config &= ~INA226_ITS_MASK;
  225. *config |= INA226_SHIFT_ITS(bits) & INA226_ITS_MASK;
  226. return 0;
  227. }
  228. static int ina2xx_write_raw(struct iio_dev *indio_dev,
  229. struct iio_chan_spec const *chan,
  230. int val, int val2, long mask)
  231. {
  232. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  233. unsigned int config, tmp;
  234. int ret;
  235. if (iio_buffer_enabled(indio_dev))
  236. return -EBUSY;
  237. mutex_lock(&chip->state_lock);
  238. ret = regmap_read(chip->regmap, INA2XX_CONFIG, &config);
  239. if (ret)
  240. goto err;
  241. tmp = config;
  242. switch (mask) {
  243. case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
  244. ret = ina226_set_average(chip, val, &tmp);
  245. break;
  246. case IIO_CHAN_INFO_INT_TIME:
  247. if (chan->address == INA2XX_SHUNT_VOLTAGE)
  248. ret = ina226_set_int_time_vshunt(chip, val2, &tmp);
  249. else
  250. ret = ina226_set_int_time_vbus(chip, val2, &tmp);
  251. break;
  252. default:
  253. ret = -EINVAL;
  254. }
  255. if (!ret && (tmp != config))
  256. ret = regmap_write(chip->regmap, INA2XX_CONFIG, tmp);
  257. err:
  258. mutex_unlock(&chip->state_lock);
  259. return ret;
  260. }
  261. static ssize_t ina2xx_allow_async_readout_show(struct device *dev,
  262. struct device_attribute *attr,
  263. char *buf)
  264. {
  265. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  266. return sprintf(buf, "%d\n", chip->allow_async_readout);
  267. }
  268. static ssize_t ina2xx_allow_async_readout_store(struct device *dev,
  269. struct device_attribute *attr,
  270. const char *buf, size_t len)
  271. {
  272. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  273. bool val;
  274. int ret;
  275. ret = strtobool((const char *) buf, &val);
  276. if (ret)
  277. return ret;
  278. chip->allow_async_readout = val;
  279. return len;
  280. }
  281. /*
  282. * Set current LSB to 1mA, shunt is in uOhms
  283. * (equation 13 in datasheet). We hardcode a Current_LSB
  284. * of 1.0 x10-6. The only remaining parameter is RShunt.
  285. * There is no need to expose the CALIBRATION register
  286. * to the user for now. But we need to reset this register
  287. * if the user updates RShunt after driver init, e.g upon
  288. * reading an EEPROM/Probe-type value.
  289. */
  290. static int ina2xx_set_calibration(struct ina2xx_chip_info *chip)
  291. {
  292. u16 regval = DIV_ROUND_CLOSEST(chip->config->calibration_factor,
  293. chip->shunt_resistor);
  294. return regmap_write(chip->regmap, INA2XX_CALIBRATION, regval);
  295. }
  296. static int set_shunt_resistor(struct ina2xx_chip_info *chip, unsigned int val)
  297. {
  298. if (val <= 0 || val > chip->config->calibration_factor)
  299. return -EINVAL;
  300. chip->shunt_resistor = val;
  301. return 0;
  302. }
  303. static ssize_t ina2xx_shunt_resistor_show(struct device *dev,
  304. struct device_attribute *attr,
  305. char *buf)
  306. {
  307. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  308. return sprintf(buf, "%d\n", chip->shunt_resistor);
  309. }
  310. static ssize_t ina2xx_shunt_resistor_store(struct device *dev,
  311. struct device_attribute *attr,
  312. const char *buf, size_t len)
  313. {
  314. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  315. unsigned long val;
  316. int ret;
  317. ret = kstrtoul((const char *) buf, 10, &val);
  318. if (ret)
  319. return ret;
  320. ret = set_shunt_resistor(chip, val);
  321. if (ret)
  322. return ret;
  323. /* Update the Calibration register */
  324. ret = ina2xx_set_calibration(chip);
  325. if (ret)
  326. return ret;
  327. return len;
  328. }
  329. #define INA2XX_CHAN(_type, _index, _address) { \
  330. .type = (_type), \
  331. .address = (_address), \
  332. .indexed = 1, \
  333. .channel = (_index), \
  334. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
  335. | BIT(IIO_CHAN_INFO_SCALE), \
  336. .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
  337. BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
  338. .scan_index = (_index), \
  339. .scan_type = { \
  340. .sign = 'u', \
  341. .realbits = 16, \
  342. .storagebits = 16, \
  343. .endianness = IIO_CPU, \
  344. } \
  345. }
  346. /*
  347. * Sampling Freq is a consequence of the integration times of
  348. * the Voltage channels.
  349. */
  350. #define INA2XX_CHAN_VOLTAGE(_index, _address) { \
  351. .type = IIO_VOLTAGE, \
  352. .address = (_address), \
  353. .indexed = 1, \
  354. .channel = (_index), \
  355. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  356. BIT(IIO_CHAN_INFO_SCALE) | \
  357. BIT(IIO_CHAN_INFO_INT_TIME), \
  358. .scan_index = (_index), \
  359. .scan_type = { \
  360. .sign = 'u', \
  361. .realbits = 16, \
  362. .storagebits = 16, \
  363. .endianness = IIO_LE, \
  364. } \
  365. }
  366. static const struct iio_chan_spec ina2xx_channels[] = {
  367. INA2XX_CHAN_VOLTAGE(0, INA2XX_SHUNT_VOLTAGE),
  368. INA2XX_CHAN_VOLTAGE(1, INA2XX_BUS_VOLTAGE),
  369. INA2XX_CHAN(IIO_POWER, 2, INA2XX_POWER),
  370. INA2XX_CHAN(IIO_CURRENT, 3, INA2XX_CURRENT),
  371. IIO_CHAN_SOFT_TIMESTAMP(4),
  372. };
  373. static int ina2xx_work_buffer(struct iio_dev *indio_dev)
  374. {
  375. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  376. unsigned short data[8];
  377. int bit, ret, i = 0;
  378. s64 time_a, time_b;
  379. unsigned int alert;
  380. time_a = iio_get_time_ns(indio_dev);
  381. /*
  382. * Because the timer thread and the chip conversion clock
  383. * are asynchronous, the period difference will eventually
  384. * result in reading V[k-1] again, or skip V[k] at time Tk.
  385. * In order to resync the timer with the conversion process
  386. * we check the ConVersionReadyFlag.
  387. * On hardware that supports using the ALERT pin to toggle a
  388. * GPIO a triggered buffer could be used instead.
  389. * For now, we pay for that extra read of the ALERT register
  390. */
  391. if (!chip->allow_async_readout)
  392. do {
  393. ret = regmap_read(chip->regmap, INA226_ALERT_MASK,
  394. &alert);
  395. if (ret < 0)
  396. return ret;
  397. alert &= INA266_CVRF;
  398. } while (!alert);
  399. /*
  400. * Single register reads: bulk_read will not work with ina226
  401. * as there is no auto-increment of the address register for
  402. * data length longer than 16bits.
  403. */
  404. for_each_set_bit(bit, indio_dev->active_scan_mask,
  405. indio_dev->masklength) {
  406. unsigned int val;
  407. ret = regmap_read(chip->regmap,
  408. INA2XX_SHUNT_VOLTAGE + bit, &val);
  409. if (ret < 0)
  410. return ret;
  411. data[i++] = val;
  412. }
  413. time_b = iio_get_time_ns(indio_dev);
  414. iio_push_to_buffers_with_timestamp(indio_dev,
  415. (unsigned int *)data, time_a);
  416. return (unsigned long)(time_b - time_a) / 1000;
  417. };
  418. static int ina2xx_capture_thread(void *data)
  419. {
  420. struct iio_dev *indio_dev = data;
  421. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  422. unsigned int sampling_us = SAMPLING_PERIOD(chip);
  423. int buffer_us;
  424. /*
  425. * Poll a bit faster than the chip internal Fs, in case
  426. * we wish to sync with the conversion ready flag.
  427. */
  428. if (!chip->allow_async_readout)
  429. sampling_us -= 200;
  430. do {
  431. buffer_us = ina2xx_work_buffer(indio_dev);
  432. if (buffer_us < 0)
  433. return buffer_us;
  434. if (sampling_us > buffer_us)
  435. udelay(sampling_us - buffer_us);
  436. } while (!kthread_should_stop());
  437. return 0;
  438. }
  439. static int ina2xx_buffer_enable(struct iio_dev *indio_dev)
  440. {
  441. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  442. unsigned int sampling_us = SAMPLING_PERIOD(chip);
  443. dev_dbg(&indio_dev->dev, "Enabling buffer w/ scan_mask %02x, freq = %d, avg =%u\n",
  444. (unsigned int)(*indio_dev->active_scan_mask),
  445. 1000000 / sampling_us, chip->avg);
  446. dev_dbg(&indio_dev->dev, "Expected work period: %u us\n", sampling_us);
  447. dev_dbg(&indio_dev->dev, "Async readout mode: %d\n",
  448. chip->allow_async_readout);
  449. chip->task = kthread_run(ina2xx_capture_thread, (void *)indio_dev,
  450. "%s:%d-%uus", indio_dev->name, indio_dev->id,
  451. sampling_us);
  452. return PTR_ERR_OR_ZERO(chip->task);
  453. }
  454. static int ina2xx_buffer_disable(struct iio_dev *indio_dev)
  455. {
  456. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  457. if (chip->task) {
  458. kthread_stop(chip->task);
  459. chip->task = NULL;
  460. }
  461. return 0;
  462. }
  463. static const struct iio_buffer_setup_ops ina2xx_setup_ops = {
  464. .postenable = &ina2xx_buffer_enable,
  465. .predisable = &ina2xx_buffer_disable,
  466. };
  467. static int ina2xx_debug_reg(struct iio_dev *indio_dev,
  468. unsigned reg, unsigned writeval, unsigned *readval)
  469. {
  470. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  471. if (!readval)
  472. return regmap_write(chip->regmap, reg, writeval);
  473. return regmap_read(chip->regmap, reg, readval);
  474. }
  475. /* Possible integration times for vshunt and vbus */
  476. static IIO_CONST_ATTR_INT_TIME_AVAIL("0.000140 0.000204 0.000332 0.000588 0.001100 0.002116 0.004156 0.008244");
  477. static IIO_DEVICE_ATTR(in_allow_async_readout, S_IRUGO | S_IWUSR,
  478. ina2xx_allow_async_readout_show,
  479. ina2xx_allow_async_readout_store, 0);
  480. static IIO_DEVICE_ATTR(in_shunt_resistor, S_IRUGO | S_IWUSR,
  481. ina2xx_shunt_resistor_show,
  482. ina2xx_shunt_resistor_store, 0);
  483. static struct attribute *ina2xx_attributes[] = {
  484. &iio_dev_attr_in_allow_async_readout.dev_attr.attr,
  485. &iio_const_attr_integration_time_available.dev_attr.attr,
  486. &iio_dev_attr_in_shunt_resistor.dev_attr.attr,
  487. NULL,
  488. };
  489. static const struct attribute_group ina2xx_attribute_group = {
  490. .attrs = ina2xx_attributes,
  491. };
  492. static const struct iio_info ina2xx_info = {
  493. .driver_module = THIS_MODULE,
  494. .attrs = &ina2xx_attribute_group,
  495. .read_raw = ina2xx_read_raw,
  496. .write_raw = ina2xx_write_raw,
  497. .debugfs_reg_access = ina2xx_debug_reg,
  498. };
  499. /* Initialize the configuration and calibration registers. */
  500. static int ina2xx_init(struct ina2xx_chip_info *chip, unsigned int config)
  501. {
  502. int ret = regmap_write(chip->regmap, INA2XX_CONFIG, config);
  503. if (ret)
  504. return ret;
  505. return ina2xx_set_calibration(chip);
  506. }
  507. static int ina2xx_probe(struct i2c_client *client,
  508. const struct i2c_device_id *id)
  509. {
  510. struct ina2xx_chip_info *chip;
  511. struct iio_dev *indio_dev;
  512. struct iio_buffer *buffer;
  513. unsigned int val;
  514. int ret;
  515. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
  516. if (!indio_dev)
  517. return -ENOMEM;
  518. chip = iio_priv(indio_dev);
  519. /* This is only used for device removal purposes. */
  520. i2c_set_clientdata(client, indio_dev);
  521. chip->regmap = devm_regmap_init_i2c(client, &ina2xx_regmap_config);
  522. if (IS_ERR(chip->regmap)) {
  523. dev_err(&client->dev, "failed to allocate register map\n");
  524. return PTR_ERR(chip->regmap);
  525. }
  526. chip->config = &ina2xx_config[id->driver_data];
  527. mutex_init(&chip->state_lock);
  528. if (of_property_read_u32(client->dev.of_node,
  529. "shunt-resistor", &val) < 0) {
  530. struct ina2xx_platform_data *pdata =
  531. dev_get_platdata(&client->dev);
  532. if (pdata)
  533. val = pdata->shunt_uohms;
  534. else
  535. val = INA2XX_RSHUNT_DEFAULT;
  536. }
  537. ret = set_shunt_resistor(chip, val);
  538. if (ret)
  539. return ret;
  540. /* Patch the current config register with default. */
  541. val = chip->config->config_default;
  542. if (id->driver_data == ina226) {
  543. ina226_set_average(chip, INA226_DEFAULT_AVG, &val);
  544. ina226_set_int_time_vbus(chip, INA226_DEFAULT_IT, &val);
  545. ina226_set_int_time_vshunt(chip, INA226_DEFAULT_IT, &val);
  546. }
  547. ret = ina2xx_init(chip, val);
  548. if (ret) {
  549. dev_err(&client->dev, "error configuring the device\n");
  550. return ret;
  551. }
  552. indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
  553. indio_dev->dev.parent = &client->dev;
  554. indio_dev->dev.of_node = client->dev.of_node;
  555. indio_dev->channels = ina2xx_channels;
  556. indio_dev->num_channels = ARRAY_SIZE(ina2xx_channels);
  557. indio_dev->name = id->name;
  558. indio_dev->info = &ina2xx_info;
  559. indio_dev->setup_ops = &ina2xx_setup_ops;
  560. buffer = devm_iio_kfifo_allocate(&indio_dev->dev);
  561. if (!buffer)
  562. return -ENOMEM;
  563. iio_device_attach_buffer(indio_dev, buffer);
  564. return iio_device_register(indio_dev);
  565. }
  566. static int ina2xx_remove(struct i2c_client *client)
  567. {
  568. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  569. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  570. iio_device_unregister(indio_dev);
  571. /* Powerdown */
  572. return regmap_update_bits(chip->regmap, INA2XX_CONFIG,
  573. INA2XX_MODE_MASK, 0);
  574. }
  575. static const struct i2c_device_id ina2xx_id[] = {
  576. {"ina219", ina219},
  577. {"ina220", ina219},
  578. {"ina226", ina226},
  579. {"ina230", ina226},
  580. {"ina231", ina226},
  581. {}
  582. };
  583. MODULE_DEVICE_TABLE(i2c, ina2xx_id);
  584. static struct i2c_driver ina2xx_driver = {
  585. .driver = {
  586. .name = KBUILD_MODNAME,
  587. },
  588. .probe = ina2xx_probe,
  589. .remove = ina2xx_remove,
  590. .id_table = ina2xx_id,
  591. };
  592. module_i2c_driver(ina2xx_driver);
  593. MODULE_AUTHOR("Marc Titinger <marc.titinger@baylibre.com>");
  594. MODULE_DESCRIPTION("Texas Instruments INA2XX ADC driver");
  595. MODULE_LICENSE("GPL v2");