gpio-syscon.c 6.7 KB

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  1. /*
  2. * SYSCON GPIO driver
  3. *
  4. * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #include <linux/err.h>
  12. #include <linux/gpio.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/regmap.h>
  18. #include <linux/mfd/syscon.h>
  19. #define GPIO_SYSCON_FEAT_IN BIT(0)
  20. #define GPIO_SYSCON_FEAT_OUT BIT(1)
  21. #define GPIO_SYSCON_FEAT_DIR BIT(2)
  22. /* SYSCON driver is designed to use 32-bit wide registers */
  23. #define SYSCON_REG_SIZE (4)
  24. #define SYSCON_REG_BITS (SYSCON_REG_SIZE * 8)
  25. /**
  26. * struct syscon_gpio_data - Configuration for the device.
  27. * compatible: SYSCON driver compatible string.
  28. * flags: Set of GPIO_SYSCON_FEAT_ flags:
  29. * GPIO_SYSCON_FEAT_IN: GPIOs supports input,
  30. * GPIO_SYSCON_FEAT_OUT: GPIOs supports output,
  31. * GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction.
  32. * bit_count: Number of bits used as GPIOs.
  33. * dat_bit_offset: Offset (in bits) to the first GPIO bit.
  34. * dir_bit_offset: Optional offset (in bits) to the first bit to switch
  35. * GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag).
  36. * set: HW specific callback to assigns output value
  37. * for signal "offset"
  38. */
  39. struct syscon_gpio_data {
  40. const char *compatible;
  41. unsigned int flags;
  42. unsigned int bit_count;
  43. unsigned int dat_bit_offset;
  44. unsigned int dir_bit_offset;
  45. void (*set)(struct gpio_chip *chip,
  46. unsigned offset, int value);
  47. };
  48. struct syscon_gpio_priv {
  49. struct gpio_chip chip;
  50. struct regmap *syscon;
  51. const struct syscon_gpio_data *data;
  52. u32 dreg_offset;
  53. u32 dir_reg_offset;
  54. };
  55. static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset)
  56. {
  57. struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
  58. unsigned int val, offs;
  59. int ret;
  60. offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
  61. ret = regmap_read(priv->syscon,
  62. (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val);
  63. if (ret)
  64. return ret;
  65. return !!(val & BIT(offs % SYSCON_REG_BITS));
  66. }
  67. static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  68. {
  69. struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
  70. unsigned int offs;
  71. offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
  72. regmap_update_bits(priv->syscon,
  73. (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
  74. BIT(offs % SYSCON_REG_BITS),
  75. val ? BIT(offs % SYSCON_REG_BITS) : 0);
  76. }
  77. static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
  78. {
  79. struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
  80. if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
  81. unsigned int offs;
  82. offs = priv->dir_reg_offset +
  83. priv->data->dir_bit_offset + offset;
  84. regmap_update_bits(priv->syscon,
  85. (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
  86. BIT(offs % SYSCON_REG_BITS), 0);
  87. }
  88. return 0;
  89. }
  90. static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val)
  91. {
  92. struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
  93. if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
  94. unsigned int offs;
  95. offs = priv->dir_reg_offset +
  96. priv->data->dir_bit_offset + offset;
  97. regmap_update_bits(priv->syscon,
  98. (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
  99. BIT(offs % SYSCON_REG_BITS),
  100. BIT(offs % SYSCON_REG_BITS));
  101. }
  102. priv->data->set(chip, offset, val);
  103. return 0;
  104. }
  105. static const struct syscon_gpio_data clps711x_mctrl_gpio = {
  106. /* ARM CLPS711X SYSFLG1 Bits 8-10 */
  107. .compatible = "cirrus,ep7209-syscon1",
  108. .flags = GPIO_SYSCON_FEAT_IN,
  109. .bit_count = 3,
  110. .dat_bit_offset = 0x40 * 8 + 8,
  111. };
  112. #define KEYSTONE_LOCK_BIT BIT(0)
  113. static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  114. {
  115. struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
  116. unsigned int offs;
  117. int ret;
  118. offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
  119. if (!val)
  120. return;
  121. ret = regmap_update_bits(
  122. priv->syscon,
  123. (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
  124. BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT,
  125. BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT);
  126. if (ret < 0)
  127. dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
  128. }
  129. static const struct syscon_gpio_data keystone_dsp_gpio = {
  130. /* ARM Keystone 2 */
  131. .compatible = NULL,
  132. .flags = GPIO_SYSCON_FEAT_OUT,
  133. .bit_count = 28,
  134. .dat_bit_offset = 4,
  135. .set = keystone_gpio_set,
  136. };
  137. static const struct of_device_id syscon_gpio_ids[] = {
  138. {
  139. .compatible = "cirrus,ep7209-mctrl-gpio",
  140. .data = &clps711x_mctrl_gpio,
  141. },
  142. {
  143. .compatible = "ti,keystone-dsp-gpio",
  144. .data = &keystone_dsp_gpio,
  145. },
  146. { }
  147. };
  148. MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
  149. static int syscon_gpio_probe(struct platform_device *pdev)
  150. {
  151. struct device *dev = &pdev->dev;
  152. const struct of_device_id *of_id;
  153. struct syscon_gpio_priv *priv;
  154. struct device_node *np = dev->of_node;
  155. int ret;
  156. of_id = of_match_device(syscon_gpio_ids, dev);
  157. if (!of_id)
  158. return -ENODEV;
  159. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  160. if (!priv)
  161. return -ENOMEM;
  162. priv->data = of_id->data;
  163. if (priv->data->compatible) {
  164. priv->syscon = syscon_regmap_lookup_by_compatible(
  165. priv->data->compatible);
  166. if (IS_ERR(priv->syscon))
  167. return PTR_ERR(priv->syscon);
  168. } else {
  169. priv->syscon =
  170. syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");
  171. if (IS_ERR(priv->syscon))
  172. return PTR_ERR(priv->syscon);
  173. ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1,
  174. &priv->dreg_offset);
  175. if (ret)
  176. dev_err(dev, "can't read the data register offset!\n");
  177. priv->dreg_offset <<= 3;
  178. ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2,
  179. &priv->dir_reg_offset);
  180. if (ret)
  181. dev_dbg(dev, "can't read the dir register offset!\n");
  182. priv->dir_reg_offset <<= 3;
  183. }
  184. priv->chip.parent = dev;
  185. priv->chip.owner = THIS_MODULE;
  186. priv->chip.label = dev_name(dev);
  187. priv->chip.base = -1;
  188. priv->chip.ngpio = priv->data->bit_count;
  189. priv->chip.get = syscon_gpio_get;
  190. if (priv->data->flags & GPIO_SYSCON_FEAT_IN)
  191. priv->chip.direction_input = syscon_gpio_dir_in;
  192. if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) {
  193. priv->chip.set = priv->data->set ? : syscon_gpio_set;
  194. priv->chip.direction_output = syscon_gpio_dir_out;
  195. }
  196. platform_set_drvdata(pdev, priv);
  197. return devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
  198. }
  199. static struct platform_driver syscon_gpio_driver = {
  200. .driver = {
  201. .name = "gpio-syscon",
  202. .of_match_table = syscon_gpio_ids,
  203. },
  204. .probe = syscon_gpio_probe,
  205. };
  206. module_platform_driver(syscon_gpio_driver);
  207. MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
  208. MODULE_DESCRIPTION("SYSCON GPIO driver");
  209. MODULE_LICENSE("GPL");