gpio-merrifield.c 11 KB

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  1. /*
  2. * Intel Merrifield SoC GPIO driver
  3. *
  4. * Copyright (c) 2016 Intel Corporation.
  5. * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/bitops.h>
  12. #include <linux/gpio/driver.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/module.h>
  17. #include <linux/pci.h>
  18. #include <linux/pinctrl/consumer.h>
  19. #define GCCR 0x000 /* controller configuration */
  20. #define GPLR 0x004 /* pin level r/o */
  21. #define GPDR 0x01c /* pin direction */
  22. #define GPSR 0x034 /* pin set w/o */
  23. #define GPCR 0x04c /* pin clear w/o */
  24. #define GRER 0x064 /* rising edge detect */
  25. #define GFER 0x07c /* falling edge detect */
  26. #define GFBR 0x094 /* glitch filter bypass */
  27. #define GIMR 0x0ac /* interrupt mask */
  28. #define GISR 0x0c4 /* interrupt source */
  29. #define GITR 0x300 /* input type */
  30. #define GLPR 0x318 /* level input polarity */
  31. #define GWMR 0x400 /* wake mask */
  32. #define GWSR 0x418 /* wake source */
  33. #define GSIR 0xc00 /* secure input */
  34. /* Intel Merrifield has 192 GPIO pins */
  35. #define MRFLD_NGPIO 192
  36. struct mrfld_gpio_pinrange {
  37. unsigned int gpio_base;
  38. unsigned int pin_base;
  39. unsigned int npins;
  40. };
  41. #define GPIO_PINRANGE(gstart, gend, pstart) \
  42. { \
  43. .gpio_base = (gstart), \
  44. .pin_base = (pstart), \
  45. .npins = (gend) - (gstart) + 1, \
  46. }
  47. struct mrfld_gpio {
  48. struct gpio_chip chip;
  49. void __iomem *reg_base;
  50. raw_spinlock_t lock;
  51. struct device *dev;
  52. };
  53. static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = {
  54. GPIO_PINRANGE(0, 11, 146),
  55. GPIO_PINRANGE(12, 13, 144),
  56. GPIO_PINRANGE(14, 15, 35),
  57. GPIO_PINRANGE(16, 16, 164),
  58. GPIO_PINRANGE(17, 18, 105),
  59. GPIO_PINRANGE(19, 22, 101),
  60. GPIO_PINRANGE(23, 30, 107),
  61. GPIO_PINRANGE(32, 43, 67),
  62. GPIO_PINRANGE(44, 63, 195),
  63. GPIO_PINRANGE(64, 67, 140),
  64. GPIO_PINRANGE(68, 69, 165),
  65. GPIO_PINRANGE(70, 71, 65),
  66. GPIO_PINRANGE(72, 76, 228),
  67. GPIO_PINRANGE(77, 86, 37),
  68. GPIO_PINRANGE(87, 87, 48),
  69. GPIO_PINRANGE(88, 88, 47),
  70. GPIO_PINRANGE(89, 96, 49),
  71. GPIO_PINRANGE(97, 97, 34),
  72. GPIO_PINRANGE(102, 119, 83),
  73. GPIO_PINRANGE(120, 123, 79),
  74. GPIO_PINRANGE(124, 135, 115),
  75. GPIO_PINRANGE(137, 142, 158),
  76. GPIO_PINRANGE(154, 163, 24),
  77. GPIO_PINRANGE(164, 176, 215),
  78. GPIO_PINRANGE(177, 189, 127),
  79. GPIO_PINRANGE(190, 191, 178),
  80. };
  81. static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
  82. unsigned int reg_type_offset)
  83. {
  84. struct mrfld_gpio *priv = gpiochip_get_data(chip);
  85. u8 reg = offset / 32;
  86. return priv->reg_base + reg_type_offset + reg * 4;
  87. }
  88. static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset)
  89. {
  90. void __iomem *gplr = gpio_reg(chip, offset, GPLR);
  91. return !!(readl(gplr) & BIT(offset % 32));
  92. }
  93. static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset,
  94. int value)
  95. {
  96. struct mrfld_gpio *priv = gpiochip_get_data(chip);
  97. void __iomem *gpsr, *gpcr;
  98. unsigned long flags;
  99. raw_spin_lock_irqsave(&priv->lock, flags);
  100. if (value) {
  101. gpsr = gpio_reg(chip, offset, GPSR);
  102. writel(BIT(offset % 32), gpsr);
  103. } else {
  104. gpcr = gpio_reg(chip, offset, GPCR);
  105. writel(BIT(offset % 32), gpcr);
  106. }
  107. raw_spin_unlock_irqrestore(&priv->lock, flags);
  108. }
  109. static int mrfld_gpio_direction_input(struct gpio_chip *chip,
  110. unsigned int offset)
  111. {
  112. struct mrfld_gpio *priv = gpiochip_get_data(chip);
  113. void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
  114. unsigned long flags;
  115. u32 value;
  116. raw_spin_lock_irqsave(&priv->lock, flags);
  117. value = readl(gpdr);
  118. value &= ~BIT(offset % 32);
  119. writel(value, gpdr);
  120. raw_spin_unlock_irqrestore(&priv->lock, flags);
  121. return 0;
  122. }
  123. static int mrfld_gpio_direction_output(struct gpio_chip *chip,
  124. unsigned int offset, int value)
  125. {
  126. struct mrfld_gpio *priv = gpiochip_get_data(chip);
  127. void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
  128. unsigned long flags;
  129. mrfld_gpio_set(chip, offset, value);
  130. raw_spin_lock_irqsave(&priv->lock, flags);
  131. value = readl(gpdr);
  132. value |= BIT(offset % 32);
  133. writel(value, gpdr);
  134. raw_spin_unlock_irqrestore(&priv->lock, flags);
  135. return 0;
  136. }
  137. static void mrfld_irq_ack(struct irq_data *d)
  138. {
  139. struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
  140. u32 gpio = irqd_to_hwirq(d);
  141. void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR);
  142. unsigned long flags;
  143. raw_spin_lock_irqsave(&priv->lock, flags);
  144. writel(BIT(gpio % 32), gisr);
  145. raw_spin_unlock_irqrestore(&priv->lock, flags);
  146. }
  147. static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask)
  148. {
  149. struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
  150. u32 gpio = irqd_to_hwirq(d);
  151. void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR);
  152. unsigned long flags;
  153. u32 value;
  154. raw_spin_lock_irqsave(&priv->lock, flags);
  155. if (unmask)
  156. value = readl(gimr) | BIT(gpio % 32);
  157. else
  158. value = readl(gimr) & ~BIT(gpio % 32);
  159. writel(value, gimr);
  160. raw_spin_unlock_irqrestore(&priv->lock, flags);
  161. }
  162. static void mrfld_irq_mask(struct irq_data *d)
  163. {
  164. mrfld_irq_unmask_mask(d, false);
  165. }
  166. static void mrfld_irq_unmask(struct irq_data *d)
  167. {
  168. mrfld_irq_unmask_mask(d, true);
  169. }
  170. static int mrfld_irq_set_type(struct irq_data *d, unsigned int type)
  171. {
  172. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  173. struct mrfld_gpio *priv = gpiochip_get_data(gc);
  174. u32 gpio = irqd_to_hwirq(d);
  175. void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
  176. void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
  177. void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
  178. void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
  179. unsigned long flags;
  180. u32 value;
  181. raw_spin_lock_irqsave(&priv->lock, flags);
  182. if (type & IRQ_TYPE_EDGE_RISING)
  183. value = readl(grer) | BIT(gpio % 32);
  184. else
  185. value = readl(grer) & ~BIT(gpio % 32);
  186. writel(value, grer);
  187. if (type & IRQ_TYPE_EDGE_FALLING)
  188. value = readl(gfer) | BIT(gpio % 32);
  189. else
  190. value = readl(gfer) & ~BIT(gpio % 32);
  191. writel(value, gfer);
  192. /*
  193. * To prevent glitches from triggering an unintended level interrupt,
  194. * configure GLPR register first and then configure GITR.
  195. */
  196. if (type & IRQ_TYPE_LEVEL_LOW)
  197. value = readl(glpr) | BIT(gpio % 32);
  198. else
  199. value = readl(glpr) & ~BIT(gpio % 32);
  200. writel(value, glpr);
  201. if (type & IRQ_TYPE_LEVEL_MASK) {
  202. value = readl(gitr) | BIT(gpio % 32);
  203. writel(value, gitr);
  204. irq_set_handler_locked(d, handle_level_irq);
  205. } else if (type & IRQ_TYPE_EDGE_BOTH) {
  206. value = readl(gitr) & ~BIT(gpio % 32);
  207. writel(value, gitr);
  208. irq_set_handler_locked(d, handle_edge_irq);
  209. }
  210. raw_spin_unlock_irqrestore(&priv->lock, flags);
  211. return 0;
  212. }
  213. static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on)
  214. {
  215. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  216. struct mrfld_gpio *priv = gpiochip_get_data(gc);
  217. u32 gpio = irqd_to_hwirq(d);
  218. void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR);
  219. void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR);
  220. unsigned long flags;
  221. u32 value;
  222. raw_spin_lock_irqsave(&priv->lock, flags);
  223. /* Clear the existing wake status */
  224. writel(BIT(gpio % 32), gwsr);
  225. if (on)
  226. value = readl(gwmr) | BIT(gpio % 32);
  227. else
  228. value = readl(gwmr) & ~BIT(gpio % 32);
  229. writel(value, gwmr);
  230. raw_spin_unlock_irqrestore(&priv->lock, flags);
  231. dev_dbg(priv->dev, "%sable wake for gpio %u\n", on ? "en" : "dis", gpio);
  232. return 0;
  233. }
  234. static struct irq_chip mrfld_irqchip = {
  235. .name = "gpio-merrifield",
  236. .irq_ack = mrfld_irq_ack,
  237. .irq_mask = mrfld_irq_mask,
  238. .irq_unmask = mrfld_irq_unmask,
  239. .irq_set_type = mrfld_irq_set_type,
  240. .irq_set_wake = mrfld_irq_set_wake,
  241. };
  242. static void mrfld_irq_handler(struct irq_desc *desc)
  243. {
  244. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  245. struct mrfld_gpio *priv = gpiochip_get_data(gc);
  246. struct irq_chip *irqchip = irq_desc_get_chip(desc);
  247. unsigned long base, gpio;
  248. chained_irq_enter(irqchip, desc);
  249. /* Check GPIO controller to check which pin triggered the interrupt */
  250. for (base = 0; base < priv->chip.ngpio; base += 32) {
  251. void __iomem *gisr = gpio_reg(&priv->chip, base, GISR);
  252. void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR);
  253. unsigned long pending, enabled;
  254. pending = readl(gisr);
  255. enabled = readl(gimr);
  256. /* Only interrupts that are enabled */
  257. pending &= enabled;
  258. for_each_set_bit(gpio, &pending, 32) {
  259. unsigned int irq;
  260. irq = irq_find_mapping(gc->irqdomain, base + gpio);
  261. generic_handle_irq(irq);
  262. }
  263. }
  264. chained_irq_exit(irqchip, desc);
  265. }
  266. static void mrfld_irq_init_hw(struct mrfld_gpio *priv)
  267. {
  268. void __iomem *reg;
  269. unsigned int base;
  270. for (base = 0; base < priv->chip.ngpio; base += 32) {
  271. /* Clear the rising-edge detect register */
  272. reg = gpio_reg(&priv->chip, base, GRER);
  273. writel(0, reg);
  274. /* Clear the falling-edge detect register */
  275. reg = gpio_reg(&priv->chip, base, GFER);
  276. writel(0, reg);
  277. }
  278. }
  279. static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  280. {
  281. const struct mrfld_gpio_pinrange *range;
  282. struct mrfld_gpio *priv;
  283. u32 gpio_base, irq_base;
  284. void __iomem *base;
  285. unsigned int i;
  286. int retval;
  287. retval = pcim_enable_device(pdev);
  288. if (retval)
  289. return retval;
  290. retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev));
  291. if (retval) {
  292. dev_err(&pdev->dev, "I/O memory mapping error\n");
  293. return retval;
  294. }
  295. base = pcim_iomap_table(pdev)[1];
  296. irq_base = readl(base);
  297. gpio_base = readl(sizeof(u32) + base);
  298. /* Release the IO mapping, since we already get the info from BAR1 */
  299. pcim_iounmap_regions(pdev, BIT(1));
  300. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  301. if (!priv) {
  302. dev_err(&pdev->dev, "can't allocate chip data\n");
  303. return -ENOMEM;
  304. }
  305. priv->dev = &pdev->dev;
  306. priv->reg_base = pcim_iomap_table(pdev)[0];
  307. priv->chip.label = dev_name(&pdev->dev);
  308. priv->chip.parent = &pdev->dev;
  309. priv->chip.request = gpiochip_generic_request;
  310. priv->chip.free = gpiochip_generic_free;
  311. priv->chip.direction_input = mrfld_gpio_direction_input;
  312. priv->chip.direction_output = mrfld_gpio_direction_output;
  313. priv->chip.get = mrfld_gpio_get;
  314. priv->chip.set = mrfld_gpio_set;
  315. priv->chip.base = gpio_base;
  316. priv->chip.ngpio = MRFLD_NGPIO;
  317. priv->chip.can_sleep = false;
  318. raw_spin_lock_init(&priv->lock);
  319. pci_set_drvdata(pdev, priv);
  320. retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
  321. if (retval) {
  322. dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
  323. return retval;
  324. }
  325. for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
  326. range = &mrfld_gpio_ranges[i];
  327. retval = gpiochip_add_pin_range(&priv->chip,
  328. "pinctrl-merrifield",
  329. range->gpio_base,
  330. range->pin_base,
  331. range->npins);
  332. if (retval) {
  333. dev_err(&pdev->dev, "failed to add GPIO pin range\n");
  334. return retval;
  335. }
  336. }
  337. retval = gpiochip_irqchip_add(&priv->chip, &mrfld_irqchip, irq_base,
  338. handle_simple_irq, IRQ_TYPE_NONE);
  339. if (retval) {
  340. dev_err(&pdev->dev, "could not connect irqchip to gpiochip\n");
  341. return retval;
  342. }
  343. mrfld_irq_init_hw(priv);
  344. gpiochip_set_chained_irqchip(&priv->chip, &mrfld_irqchip, pdev->irq,
  345. mrfld_irq_handler);
  346. return 0;
  347. }
  348. static const struct pci_device_id mrfld_gpio_ids[] = {
  349. { PCI_VDEVICE(INTEL, 0x1199) },
  350. { }
  351. };
  352. MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids);
  353. static struct pci_driver mrfld_gpio_driver = {
  354. .name = "gpio-merrifield",
  355. .id_table = mrfld_gpio_ids,
  356. .probe = mrfld_gpio_probe,
  357. };
  358. module_pci_driver(mrfld_gpio_driver);
  359. MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
  360. MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver");
  361. MODULE_LICENSE("GPL v2");