sfi.c 14 KB

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  1. /*
  2. * intel_mid_sfi.c: Intel MID SFI initialization code
  3. *
  4. * (C) Copyright 2013 Intel Corporation
  5. * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; version 2
  10. * of the License.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/scatterlist.h>
  16. #include <linux/sfi.h>
  17. #include <linux/intel_pmic_gpio.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/i2c.h>
  20. #include <linux/skbuff.h>
  21. #include <linux/gpio.h>
  22. #include <linux/gpio_keys.h>
  23. #include <linux/input.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/irq.h>
  26. #include <linux/export.h>
  27. #include <linux/notifier.h>
  28. #include <linux/mmc/core.h>
  29. #include <linux/mmc/card.h>
  30. #include <linux/blkdev.h>
  31. #include <asm/setup.h>
  32. #include <asm/mpspec_def.h>
  33. #include <asm/hw_irq.h>
  34. #include <asm/apic.h>
  35. #include <asm/io_apic.h>
  36. #include <asm/intel-mid.h>
  37. #include <asm/intel_mid_vrtc.h>
  38. #include <asm/io.h>
  39. #include <asm/i8259.h>
  40. #include <asm/intel_scu_ipc.h>
  41. #include <asm/apb_timer.h>
  42. #include <asm/reboot.h>
  43. #define SFI_SIG_OEM0 "OEM0"
  44. #define MAX_IPCDEVS 24
  45. #define MAX_SCU_SPI 24
  46. #define MAX_SCU_I2C 24
  47. static struct platform_device *ipc_devs[MAX_IPCDEVS];
  48. static struct spi_board_info *spi_devs[MAX_SCU_SPI];
  49. static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
  50. static struct sfi_gpio_table_entry *gpio_table;
  51. static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
  52. static int ipc_next_dev;
  53. static int spi_next_dev;
  54. static int i2c_next_dev;
  55. static int i2c_bus[MAX_SCU_I2C];
  56. static int gpio_num_entry;
  57. static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
  58. int sfi_mrtc_num;
  59. int sfi_mtimer_num;
  60. struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
  61. EXPORT_SYMBOL_GPL(sfi_mrtc_array);
  62. struct blocking_notifier_head intel_scu_notifier =
  63. BLOCKING_NOTIFIER_INIT(intel_scu_notifier);
  64. EXPORT_SYMBOL_GPL(intel_scu_notifier);
  65. #define intel_mid_sfi_get_pdata(dev, priv) \
  66. ((dev)->get_platform_data ? (dev)->get_platform_data(priv) : NULL)
  67. /* parse all the mtimer info to a static mtimer array */
  68. int __init sfi_parse_mtmr(struct sfi_table_header *table)
  69. {
  70. struct sfi_table_simple *sb;
  71. struct sfi_timer_table_entry *pentry;
  72. struct mpc_intsrc mp_irq;
  73. int totallen;
  74. sb = (struct sfi_table_simple *)table;
  75. if (!sfi_mtimer_num) {
  76. sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
  77. struct sfi_timer_table_entry);
  78. pentry = (struct sfi_timer_table_entry *) sb->pentry;
  79. totallen = sfi_mtimer_num * sizeof(*pentry);
  80. memcpy(sfi_mtimer_array, pentry, totallen);
  81. }
  82. pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
  83. pentry = sfi_mtimer_array;
  84. for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
  85. pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz, irq = %d\n",
  86. totallen, (u32)pentry->phys_addr,
  87. pentry->freq_hz, pentry->irq);
  88. mp_irq.type = MP_INTSRC;
  89. mp_irq.irqtype = mp_INT;
  90. /* triggering mode edge bit 2-3, active high polarity bit 0-1 */
  91. mp_irq.irqflag = 5;
  92. mp_irq.srcbus = MP_BUS_ISA;
  93. mp_irq.srcbusirq = pentry->irq; /* IRQ */
  94. mp_irq.dstapic = MP_APIC_ALL;
  95. mp_irq.dstirq = pentry->irq;
  96. mp_save_irq(&mp_irq);
  97. mp_map_gsi_to_irq(pentry->irq, IOAPIC_MAP_ALLOC, NULL);
  98. }
  99. return 0;
  100. }
  101. struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
  102. {
  103. int i;
  104. if (hint < sfi_mtimer_num) {
  105. if (!sfi_mtimer_usage[hint]) {
  106. pr_debug("hint taken for timer %d irq %d\n",
  107. hint, sfi_mtimer_array[hint].irq);
  108. sfi_mtimer_usage[hint] = 1;
  109. return &sfi_mtimer_array[hint];
  110. }
  111. }
  112. /* take the first timer available */
  113. for (i = 0; i < sfi_mtimer_num;) {
  114. if (!sfi_mtimer_usage[i]) {
  115. sfi_mtimer_usage[i] = 1;
  116. return &sfi_mtimer_array[i];
  117. }
  118. i++;
  119. }
  120. return NULL;
  121. }
  122. void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
  123. {
  124. int i;
  125. for (i = 0; i < sfi_mtimer_num;) {
  126. if (mtmr->irq == sfi_mtimer_array[i].irq) {
  127. sfi_mtimer_usage[i] = 0;
  128. return;
  129. }
  130. i++;
  131. }
  132. }
  133. /* parse all the mrtc info to a global mrtc array */
  134. int __init sfi_parse_mrtc(struct sfi_table_header *table)
  135. {
  136. struct sfi_table_simple *sb;
  137. struct sfi_rtc_table_entry *pentry;
  138. struct mpc_intsrc mp_irq;
  139. int totallen;
  140. sb = (struct sfi_table_simple *)table;
  141. if (!sfi_mrtc_num) {
  142. sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
  143. struct sfi_rtc_table_entry);
  144. pentry = (struct sfi_rtc_table_entry *)sb->pentry;
  145. totallen = sfi_mrtc_num * sizeof(*pentry);
  146. memcpy(sfi_mrtc_array, pentry, totallen);
  147. }
  148. pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
  149. pentry = sfi_mrtc_array;
  150. for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
  151. pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
  152. totallen, (u32)pentry->phys_addr, pentry->irq);
  153. mp_irq.type = MP_INTSRC;
  154. mp_irq.irqtype = mp_INT;
  155. mp_irq.irqflag = 0xf; /* level trigger and active low */
  156. mp_irq.srcbus = MP_BUS_ISA;
  157. mp_irq.srcbusirq = pentry->irq; /* IRQ */
  158. mp_irq.dstapic = MP_APIC_ALL;
  159. mp_irq.dstirq = pentry->irq;
  160. mp_save_irq(&mp_irq);
  161. mp_map_gsi_to_irq(pentry->irq, IOAPIC_MAP_ALLOC, NULL);
  162. }
  163. return 0;
  164. }
  165. /*
  166. * Parsing GPIO table first, since the DEVS table will need this table
  167. * to map the pin name to the actual pin.
  168. */
  169. static int __init sfi_parse_gpio(struct sfi_table_header *table)
  170. {
  171. struct sfi_table_simple *sb;
  172. struct sfi_gpio_table_entry *pentry;
  173. int num, i;
  174. if (gpio_table)
  175. return 0;
  176. sb = (struct sfi_table_simple *)table;
  177. num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
  178. pentry = (struct sfi_gpio_table_entry *)sb->pentry;
  179. gpio_table = kmemdup(pentry, num * sizeof(*pentry), GFP_KERNEL);
  180. if (!gpio_table)
  181. return -1;
  182. gpio_num_entry = num;
  183. pr_debug("GPIO pin info:\n");
  184. for (i = 0; i < num; i++, pentry++)
  185. pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
  186. " pin = %d\n", i,
  187. pentry->controller_name,
  188. pentry->pin_name,
  189. pentry->pin_no);
  190. return 0;
  191. }
  192. int get_gpio_by_name(const char *name)
  193. {
  194. struct sfi_gpio_table_entry *pentry = gpio_table;
  195. int i;
  196. if (!pentry)
  197. return -1;
  198. for (i = 0; i < gpio_num_entry; i++, pentry++) {
  199. if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
  200. return pentry->pin_no;
  201. }
  202. return -EINVAL;
  203. }
  204. void __init intel_scu_device_register(struct platform_device *pdev)
  205. {
  206. if (ipc_next_dev == MAX_IPCDEVS)
  207. pr_err("too many SCU IPC devices");
  208. else
  209. ipc_devs[ipc_next_dev++] = pdev;
  210. }
  211. static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
  212. {
  213. struct spi_board_info *new_dev;
  214. if (spi_next_dev == MAX_SCU_SPI) {
  215. pr_err("too many SCU SPI devices");
  216. return;
  217. }
  218. new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
  219. if (!new_dev) {
  220. pr_err("failed to alloc mem for delayed spi dev %s\n",
  221. sdev->modalias);
  222. return;
  223. }
  224. *new_dev = *sdev;
  225. spi_devs[spi_next_dev++] = new_dev;
  226. }
  227. static void __init intel_scu_i2c_device_register(int bus,
  228. struct i2c_board_info *idev)
  229. {
  230. struct i2c_board_info *new_dev;
  231. if (i2c_next_dev == MAX_SCU_I2C) {
  232. pr_err("too many SCU I2C devices");
  233. return;
  234. }
  235. new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
  236. if (!new_dev) {
  237. pr_err("failed to alloc mem for delayed i2c dev %s\n",
  238. idev->type);
  239. return;
  240. }
  241. *new_dev = *idev;
  242. i2c_bus[i2c_next_dev] = bus;
  243. i2c_devs[i2c_next_dev++] = new_dev;
  244. }
  245. /* Called by IPC driver */
  246. void intel_scu_devices_create(void)
  247. {
  248. int i;
  249. for (i = 0; i < ipc_next_dev; i++)
  250. platform_device_add(ipc_devs[i]);
  251. for (i = 0; i < spi_next_dev; i++)
  252. spi_register_board_info(spi_devs[i], 1);
  253. for (i = 0; i < i2c_next_dev; i++) {
  254. struct i2c_adapter *adapter;
  255. struct i2c_client *client;
  256. adapter = i2c_get_adapter(i2c_bus[i]);
  257. if (adapter) {
  258. client = i2c_new_device(adapter, i2c_devs[i]);
  259. if (!client)
  260. pr_err("can't create i2c device %s\n",
  261. i2c_devs[i]->type);
  262. } else
  263. i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
  264. }
  265. intel_scu_notifier_post(SCU_AVAILABLE, NULL);
  266. }
  267. EXPORT_SYMBOL_GPL(intel_scu_devices_create);
  268. /* Called by IPC driver */
  269. void intel_scu_devices_destroy(void)
  270. {
  271. int i;
  272. intel_scu_notifier_post(SCU_DOWN, NULL);
  273. for (i = 0; i < ipc_next_dev; i++)
  274. platform_device_del(ipc_devs[i]);
  275. }
  276. EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);
  277. static void __init install_irq_resource(struct platform_device *pdev, int irq)
  278. {
  279. /* Single threaded */
  280. static struct resource res __initdata = {
  281. .name = "IRQ",
  282. .flags = IORESOURCE_IRQ,
  283. };
  284. res.start = irq;
  285. platform_device_add_resources(pdev, &res, 1);
  286. }
  287. static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *pentry,
  288. struct devs_id *dev)
  289. {
  290. struct platform_device *pdev;
  291. void *pdata = NULL;
  292. pr_debug("IPC bus, name = %16.16s, irq = 0x%2x\n",
  293. pentry->name, pentry->irq);
  294. pdata = intel_mid_sfi_get_pdata(dev, pentry);
  295. if (IS_ERR(pdata))
  296. return;
  297. pdev = platform_device_alloc(pentry->name, 0);
  298. if (pdev == NULL) {
  299. pr_err("out of memory for SFI platform device '%s'.\n",
  300. pentry->name);
  301. return;
  302. }
  303. install_irq_resource(pdev, pentry->irq);
  304. pdev->dev.platform_data = pdata;
  305. platform_device_add(pdev);
  306. }
  307. static void __init sfi_handle_spi_dev(struct sfi_device_table_entry *pentry,
  308. struct devs_id *dev)
  309. {
  310. struct spi_board_info spi_info;
  311. void *pdata = NULL;
  312. memset(&spi_info, 0, sizeof(spi_info));
  313. strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
  314. spi_info.irq = ((pentry->irq == (u8)0xff) ? 0 : pentry->irq);
  315. spi_info.bus_num = pentry->host_num;
  316. spi_info.chip_select = pentry->addr;
  317. spi_info.max_speed_hz = pentry->max_freq;
  318. pr_debug("SPI bus=%d, name=%16.16s, irq=0x%2x, max_freq=%d, cs=%d\n",
  319. spi_info.bus_num,
  320. spi_info.modalias,
  321. spi_info.irq,
  322. spi_info.max_speed_hz,
  323. spi_info.chip_select);
  324. pdata = intel_mid_sfi_get_pdata(dev, &spi_info);
  325. if (IS_ERR(pdata))
  326. return;
  327. spi_info.platform_data = pdata;
  328. if (dev->delay)
  329. intel_scu_spi_device_register(&spi_info);
  330. else
  331. spi_register_board_info(&spi_info, 1);
  332. }
  333. static void __init sfi_handle_i2c_dev(struct sfi_device_table_entry *pentry,
  334. struct devs_id *dev)
  335. {
  336. struct i2c_board_info i2c_info;
  337. void *pdata = NULL;
  338. memset(&i2c_info, 0, sizeof(i2c_info));
  339. strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
  340. i2c_info.irq = ((pentry->irq == (u8)0xff) ? 0 : pentry->irq);
  341. i2c_info.addr = pentry->addr;
  342. pr_debug("I2C bus = %d, name = %16.16s, irq = 0x%2x, addr = 0x%x\n",
  343. pentry->host_num,
  344. i2c_info.type,
  345. i2c_info.irq,
  346. i2c_info.addr);
  347. pdata = intel_mid_sfi_get_pdata(dev, &i2c_info);
  348. i2c_info.platform_data = pdata;
  349. if (IS_ERR(pdata))
  350. return;
  351. if (dev->delay)
  352. intel_scu_i2c_device_register(pentry->host_num, &i2c_info);
  353. else
  354. i2c_register_board_info(pentry->host_num, &i2c_info, 1);
  355. }
  356. static void __init sfi_handle_sd_dev(struct sfi_device_table_entry *pentry,
  357. struct devs_id *dev)
  358. {
  359. struct mid_sd_board_info sd_info;
  360. void *pdata;
  361. memset(&sd_info, 0, sizeof(sd_info));
  362. strncpy(sd_info.name, pentry->name, SFI_NAME_LEN);
  363. sd_info.bus_num = pentry->host_num;
  364. sd_info.max_clk = pentry->max_freq;
  365. sd_info.addr = pentry->addr;
  366. pr_debug("SD bus = %d, name = %16.16s, max_clk = %d, addr = 0x%x\n",
  367. sd_info.bus_num,
  368. sd_info.name,
  369. sd_info.max_clk,
  370. sd_info.addr);
  371. pdata = intel_mid_sfi_get_pdata(dev, &sd_info);
  372. if (IS_ERR(pdata))
  373. return;
  374. /* Nothing we can do with this for now */
  375. sd_info.platform_data = pdata;
  376. pr_debug("Successfully registered %16.16s", sd_info.name);
  377. }
  378. extern struct devs_id *const __x86_intel_mid_dev_start[],
  379. *const __x86_intel_mid_dev_end[];
  380. static struct devs_id __init *get_device_id(u8 type, char *name)
  381. {
  382. struct devs_id *const *dev_table;
  383. for (dev_table = __x86_intel_mid_dev_start;
  384. dev_table < __x86_intel_mid_dev_end; dev_table++) {
  385. struct devs_id *dev = *dev_table;
  386. if (dev->type == type &&
  387. !strncmp(dev->name, name, SFI_NAME_LEN)) {
  388. return dev;
  389. }
  390. }
  391. return NULL;
  392. }
  393. static int __init sfi_parse_devs(struct sfi_table_header *table)
  394. {
  395. struct sfi_table_simple *sb;
  396. struct sfi_device_table_entry *pentry;
  397. struct devs_id *dev = NULL;
  398. int num, i, ret;
  399. int polarity;
  400. struct irq_alloc_info info;
  401. sb = (struct sfi_table_simple *)table;
  402. num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
  403. pentry = (struct sfi_device_table_entry *)sb->pentry;
  404. for (i = 0; i < num; i++, pentry++) {
  405. int irq = pentry->irq;
  406. if (irq != (u8)0xff) { /* native RTE case */
  407. /* these SPI2 devices are not exposed to system as PCI
  408. * devices, but they have separate RTE entry in IOAPIC
  409. * so we have to enable them one by one here
  410. */
  411. if (intel_mid_identify_cpu() ==
  412. INTEL_MID_CPU_CHIP_TANGIER) {
  413. if (!strncmp(pentry->name, "r69001-ts-i2c", 13))
  414. /* active low */
  415. polarity = 1;
  416. else if (!strncmp(pentry->name,
  417. "synaptics_3202", 14))
  418. /* active low */
  419. polarity = 1;
  420. else if (irq == 41)
  421. /* fast_int_1 */
  422. polarity = 1;
  423. else
  424. /* active high */
  425. polarity = 0;
  426. } else {
  427. /* PNW and CLV go with active low */
  428. polarity = 1;
  429. }
  430. ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 1, polarity);
  431. ret = mp_map_gsi_to_irq(irq, IOAPIC_MAP_ALLOC, &info);
  432. WARN_ON(ret < 0);
  433. }
  434. dev = get_device_id(pentry->type, pentry->name);
  435. if (!dev)
  436. continue;
  437. if (dev->device_handler) {
  438. dev->device_handler(pentry, dev);
  439. } else {
  440. switch (pentry->type) {
  441. case SFI_DEV_TYPE_IPC:
  442. sfi_handle_ipc_dev(pentry, dev);
  443. break;
  444. case SFI_DEV_TYPE_SPI:
  445. sfi_handle_spi_dev(pentry, dev);
  446. break;
  447. case SFI_DEV_TYPE_I2C:
  448. sfi_handle_i2c_dev(pentry, dev);
  449. break;
  450. case SFI_DEV_TYPE_SD:
  451. sfi_handle_sd_dev(pentry, dev);
  452. break;
  453. case SFI_DEV_TYPE_UART:
  454. case SFI_DEV_TYPE_HSI:
  455. default:
  456. break;
  457. }
  458. }
  459. }
  460. return 0;
  461. }
  462. static int __init intel_mid_platform_init(void)
  463. {
  464. sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
  465. sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
  466. return 0;
  467. }
  468. arch_initcall(intel_mid_platform_init);