power.c 7.5 KB

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  1. /*
  2. * Performance events - AMD Processor Power Reporting Mechanism
  3. *
  4. * Copyright (C) 2016 Advanced Micro Devices, Inc.
  5. *
  6. * Author: Huang Rui <ray.huang@amd.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/slab.h>
  14. #include <linux/perf_event.h>
  15. #include <asm/cpu_device_id.h>
  16. #include "../perf_event.h"
  17. #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
  18. #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
  19. #define MSR_F15H_PTSC 0xc0010280
  20. /* Event code: LSB 8 bits, passed in attr->config any other bit is reserved. */
  21. #define AMD_POWER_EVENT_MASK 0xFFULL
  22. /*
  23. * Accumulated power status counters.
  24. */
  25. #define AMD_POWER_EVENTSEL_PKG 1
  26. /*
  27. * The ratio of compute unit power accumulator sample period to the
  28. * PTSC period.
  29. */
  30. static unsigned int cpu_pwr_sample_ratio;
  31. /* Maximum accumulated power of a compute unit. */
  32. static u64 max_cu_acc_power;
  33. static struct pmu pmu_class;
  34. /*
  35. * Accumulated power represents the sum of each compute unit's (CU) power
  36. * consumption. On any core of each CU we read the total accumulated power from
  37. * MSR_F15H_CU_PWR_ACCUMULATOR. cpu_mask represents CPU bit map of all cores
  38. * which are picked to measure the power for the CUs they belong to.
  39. */
  40. static cpumask_t cpu_mask;
  41. static void event_update(struct perf_event *event)
  42. {
  43. struct hw_perf_event *hwc = &event->hw;
  44. u64 prev_pwr_acc, new_pwr_acc, prev_ptsc, new_ptsc;
  45. u64 delta, tdelta;
  46. prev_pwr_acc = hwc->pwr_acc;
  47. prev_ptsc = hwc->ptsc;
  48. rdmsrl(MSR_F15H_CU_PWR_ACCUMULATOR, new_pwr_acc);
  49. rdmsrl(MSR_F15H_PTSC, new_ptsc);
  50. /*
  51. * Calculate the CU power consumption over a time period, the unit of
  52. * final value (delta) is micro-Watts. Then add it to the event count.
  53. */
  54. if (new_pwr_acc < prev_pwr_acc) {
  55. delta = max_cu_acc_power + new_pwr_acc;
  56. delta -= prev_pwr_acc;
  57. } else
  58. delta = new_pwr_acc - prev_pwr_acc;
  59. delta *= cpu_pwr_sample_ratio * 1000;
  60. tdelta = new_ptsc - prev_ptsc;
  61. do_div(delta, tdelta);
  62. local64_add(delta, &event->count);
  63. }
  64. static void __pmu_event_start(struct perf_event *event)
  65. {
  66. if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
  67. return;
  68. event->hw.state = 0;
  69. rdmsrl(MSR_F15H_PTSC, event->hw.ptsc);
  70. rdmsrl(MSR_F15H_CU_PWR_ACCUMULATOR, event->hw.pwr_acc);
  71. }
  72. static void pmu_event_start(struct perf_event *event, int mode)
  73. {
  74. __pmu_event_start(event);
  75. }
  76. static void pmu_event_stop(struct perf_event *event, int mode)
  77. {
  78. struct hw_perf_event *hwc = &event->hw;
  79. /* Mark event as deactivated and stopped. */
  80. if (!(hwc->state & PERF_HES_STOPPED))
  81. hwc->state |= PERF_HES_STOPPED;
  82. /* Check if software counter update is necessary. */
  83. if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
  84. /*
  85. * Drain the remaining delta count out of an event
  86. * that we are disabling:
  87. */
  88. event_update(event);
  89. hwc->state |= PERF_HES_UPTODATE;
  90. }
  91. }
  92. static int pmu_event_add(struct perf_event *event, int mode)
  93. {
  94. struct hw_perf_event *hwc = &event->hw;
  95. hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
  96. if (mode & PERF_EF_START)
  97. __pmu_event_start(event);
  98. return 0;
  99. }
  100. static void pmu_event_del(struct perf_event *event, int flags)
  101. {
  102. pmu_event_stop(event, PERF_EF_UPDATE);
  103. }
  104. static int pmu_event_init(struct perf_event *event)
  105. {
  106. u64 cfg = event->attr.config & AMD_POWER_EVENT_MASK;
  107. /* Only look at AMD power events. */
  108. if (event->attr.type != pmu_class.type)
  109. return -ENOENT;
  110. /* Unsupported modes and filters. */
  111. if (event->attr.exclude_user ||
  112. event->attr.exclude_kernel ||
  113. event->attr.exclude_hv ||
  114. event->attr.exclude_idle ||
  115. event->attr.exclude_host ||
  116. event->attr.exclude_guest ||
  117. /* no sampling */
  118. event->attr.sample_period)
  119. return -EINVAL;
  120. if (cfg != AMD_POWER_EVENTSEL_PKG)
  121. return -EINVAL;
  122. return 0;
  123. }
  124. static void pmu_event_read(struct perf_event *event)
  125. {
  126. event_update(event);
  127. }
  128. static ssize_t
  129. get_attr_cpumask(struct device *dev, struct device_attribute *attr, char *buf)
  130. {
  131. return cpumap_print_to_pagebuf(true, buf, &cpu_mask);
  132. }
  133. static DEVICE_ATTR(cpumask, S_IRUGO, get_attr_cpumask, NULL);
  134. static struct attribute *pmu_attrs[] = {
  135. &dev_attr_cpumask.attr,
  136. NULL,
  137. };
  138. static struct attribute_group pmu_attr_group = {
  139. .attrs = pmu_attrs,
  140. };
  141. /*
  142. * Currently it only supports to report the power of each
  143. * processor/package.
  144. */
  145. EVENT_ATTR_STR(power-pkg, power_pkg, "event=0x01");
  146. EVENT_ATTR_STR(power-pkg.unit, power_pkg_unit, "mWatts");
  147. /* Convert the count from micro-Watts to milli-Watts. */
  148. EVENT_ATTR_STR(power-pkg.scale, power_pkg_scale, "1.000000e-3");
  149. static struct attribute *events_attr[] = {
  150. EVENT_PTR(power_pkg),
  151. EVENT_PTR(power_pkg_unit),
  152. EVENT_PTR(power_pkg_scale),
  153. NULL,
  154. };
  155. static struct attribute_group pmu_events_group = {
  156. .name = "events",
  157. .attrs = events_attr,
  158. };
  159. PMU_FORMAT_ATTR(event, "config:0-7");
  160. static struct attribute *formats_attr[] = {
  161. &format_attr_event.attr,
  162. NULL,
  163. };
  164. static struct attribute_group pmu_format_group = {
  165. .name = "format",
  166. .attrs = formats_attr,
  167. };
  168. static const struct attribute_group *attr_groups[] = {
  169. &pmu_attr_group,
  170. &pmu_format_group,
  171. &pmu_events_group,
  172. NULL,
  173. };
  174. static struct pmu pmu_class = {
  175. .attr_groups = attr_groups,
  176. /* system-wide only */
  177. .task_ctx_nr = perf_invalid_context,
  178. .event_init = pmu_event_init,
  179. .add = pmu_event_add,
  180. .del = pmu_event_del,
  181. .start = pmu_event_start,
  182. .stop = pmu_event_stop,
  183. .read = pmu_event_read,
  184. };
  185. static int power_cpu_exit(unsigned int cpu)
  186. {
  187. int target;
  188. if (!cpumask_test_and_clear_cpu(cpu, &cpu_mask))
  189. return 0;
  190. /*
  191. * Find a new CPU on the same compute unit, if was set in cpumask
  192. * and still some CPUs on compute unit. Then migrate event and
  193. * context to new CPU.
  194. */
  195. target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
  196. if (target < nr_cpumask_bits) {
  197. cpumask_set_cpu(target, &cpu_mask);
  198. perf_pmu_migrate_context(&pmu_class, cpu, target);
  199. }
  200. return 0;
  201. }
  202. static int power_cpu_init(unsigned int cpu)
  203. {
  204. int target;
  205. /*
  206. * 1) If any CPU is set at cpu_mask in the same compute unit, do
  207. * nothing.
  208. * 2) If no CPU is set at cpu_mask in the same compute unit,
  209. * set current ONLINE CPU.
  210. *
  211. * Note: if there is a CPU aside of the new one already in the
  212. * sibling mask, then it is also in cpu_mask.
  213. */
  214. target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
  215. if (target >= nr_cpumask_bits)
  216. cpumask_set_cpu(cpu, &cpu_mask);
  217. return 0;
  218. }
  219. static const struct x86_cpu_id cpu_match[] = {
  220. { .vendor = X86_VENDOR_AMD, .family = 0x15 },
  221. {},
  222. };
  223. static int __init amd_power_pmu_init(void)
  224. {
  225. int ret;
  226. if (!x86_match_cpu(cpu_match))
  227. return -ENODEV;
  228. if (!boot_cpu_has(X86_FEATURE_ACC_POWER))
  229. return -ENODEV;
  230. cpu_pwr_sample_ratio = cpuid_ecx(0x80000007);
  231. if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &max_cu_acc_power)) {
  232. pr_err("Failed to read max compute unit power accumulator MSR\n");
  233. return -ENODEV;
  234. }
  235. cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_POWER_ONLINE,
  236. "AP_PERF_X86_AMD_POWER_ONLINE",
  237. power_cpu_init, power_cpu_exit);
  238. ret = perf_pmu_register(&pmu_class, "power", -1);
  239. if (WARN_ON(ret)) {
  240. pr_warn("AMD Power PMU registration failed\n");
  241. return ret;
  242. }
  243. pr_info("AMD Power PMU detected\n");
  244. return ret;
  245. }
  246. module_init(amd_power_pmu_init);
  247. static void __exit amd_power_pmu_exit(void)
  248. {
  249. cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_AMD_POWER_ONLINE);
  250. perf_pmu_unregister(&pmu_class);
  251. }
  252. module_exit(amd_power_pmu_exit);
  253. MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>");
  254. MODULE_DESCRIPTION("AMD Processor Power Reporting Mechanism");
  255. MODULE_LICENSE("GPL v2");