skl-sst.c 12 KB

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  1. /*
  2. * skl-sst.c - HDA DSP library functions for SKL platform
  3. *
  4. * Copyright (C) 2014-15, Intel Corporation.
  5. * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
  6. * Jeeja KP <jeeja.kp@intel.com>
  7. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as version 2, as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  16. * General Public License for more details.
  17. */
  18. #include <linux/module.h>
  19. #include <linux/delay.h>
  20. #include <linux/device.h>
  21. #include <linux/err.h>
  22. #include <linux/uuid.h>
  23. #include "../common/sst-dsp.h"
  24. #include "../common/sst-dsp-priv.h"
  25. #include "../common/sst-ipc.h"
  26. #include "skl-sst-ipc.h"
  27. #define SKL_BASEFW_TIMEOUT 300
  28. #define SKL_INIT_TIMEOUT 1000
  29. /* Intel HD Audio SRAM Window 0*/
  30. #define SKL_ADSP_SRAM0_BASE 0x8000
  31. /* Firmware status window */
  32. #define SKL_ADSP_FW_STATUS SKL_ADSP_SRAM0_BASE
  33. #define SKL_ADSP_ERROR_CODE (SKL_ADSP_FW_STATUS + 0x4)
  34. #define SKL_NUM_MODULES 1
  35. static bool skl_check_fw_status(struct sst_dsp *ctx, u32 status)
  36. {
  37. u32 cur_sts;
  38. cur_sts = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS) & SKL_FW_STS_MASK;
  39. return (cur_sts == status);
  40. }
  41. static int skl_transfer_firmware(struct sst_dsp *ctx,
  42. const void *basefw, u32 base_fw_size)
  43. {
  44. int ret = 0;
  45. ret = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx, basefw, base_fw_size);
  46. if (ret < 0)
  47. return ret;
  48. ret = sst_dsp_register_poll(ctx,
  49. SKL_ADSP_FW_STATUS,
  50. SKL_FW_STS_MASK,
  51. SKL_FW_RFW_START,
  52. SKL_BASEFW_TIMEOUT,
  53. "Firmware boot");
  54. ctx->cl_dev.ops.cl_stop_dma(ctx);
  55. return ret;
  56. }
  57. #define SKL_ADSP_FW_BIN_HDR_OFFSET 0x284
  58. static int skl_load_base_firmware(struct sst_dsp *ctx)
  59. {
  60. int ret = 0, i;
  61. struct skl_sst *skl = ctx->thread_context;
  62. struct firmware stripped_fw;
  63. u32 reg;
  64. skl->boot_complete = false;
  65. init_waitqueue_head(&skl->boot_wait);
  66. if (ctx->fw == NULL) {
  67. ret = reject_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
  68. if (ret < 0) {
  69. dev_err(ctx->dev, "Request firmware failed %d\n", ret);
  70. return -EIO;
  71. }
  72. }
  73. /* prase uuids on first boot */
  74. if (skl->is_first_boot) {
  75. ret = snd_skl_parse_uuids(ctx, ctx->fw, SKL_ADSP_FW_BIN_HDR_OFFSET, 0);
  76. if (ret < 0) {
  77. dev_err(ctx->dev, "UUID parsing err: %d\n", ret);
  78. release_firmware(ctx->fw);
  79. skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
  80. return ret;
  81. }
  82. }
  83. /* check for extended manifest */
  84. stripped_fw.data = ctx->fw->data;
  85. stripped_fw.size = ctx->fw->size;
  86. skl_dsp_strip_extended_manifest(&stripped_fw);
  87. ret = skl_dsp_boot(ctx);
  88. if (ret < 0) {
  89. dev_err(ctx->dev, "Boot dsp core failed ret: %d\n", ret);
  90. goto skl_load_base_firmware_failed;
  91. }
  92. ret = skl_cldma_prepare(ctx);
  93. if (ret < 0) {
  94. dev_err(ctx->dev, "CL dma prepare failed : %d\n", ret);
  95. goto skl_load_base_firmware_failed;
  96. }
  97. /* enable Interrupt */
  98. skl_ipc_int_enable(ctx);
  99. skl_ipc_op_int_enable(ctx);
  100. /* check ROM Status */
  101. for (i = SKL_INIT_TIMEOUT; i > 0; --i) {
  102. if (skl_check_fw_status(ctx, SKL_FW_INIT)) {
  103. dev_dbg(ctx->dev,
  104. "ROM loaded, we can continue with FW loading\n");
  105. break;
  106. }
  107. mdelay(1);
  108. }
  109. if (!i) {
  110. reg = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS);
  111. dev_err(ctx->dev,
  112. "Timeout waiting for ROM init done, reg:0x%x\n", reg);
  113. ret = -EIO;
  114. goto transfer_firmware_failed;
  115. }
  116. ret = skl_transfer_firmware(ctx, stripped_fw.data, stripped_fw.size);
  117. if (ret < 0) {
  118. dev_err(ctx->dev, "Transfer firmware failed%d\n", ret);
  119. goto transfer_firmware_failed;
  120. } else {
  121. ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
  122. msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
  123. if (ret == 0) {
  124. dev_err(ctx->dev, "DSP boot failed, FW Ready timed-out\n");
  125. ret = -EIO;
  126. goto transfer_firmware_failed;
  127. }
  128. dev_dbg(ctx->dev, "Download firmware successful%d\n", ret);
  129. skl->fw_loaded = true;
  130. }
  131. return 0;
  132. transfer_firmware_failed:
  133. ctx->cl_dev.ops.cl_cleanup_controller(ctx);
  134. skl_load_base_firmware_failed:
  135. skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
  136. release_firmware(ctx->fw);
  137. ctx->fw = NULL;
  138. return ret;
  139. }
  140. static int skl_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
  141. {
  142. int ret;
  143. struct skl_ipc_dxstate_info dx;
  144. struct skl_sst *skl = ctx->thread_context;
  145. unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
  146. /* If core0 is being turned on, we need to load the FW */
  147. if (core_id == SKL_DSP_CORE0_ID) {
  148. ret = skl_load_base_firmware(ctx);
  149. if (ret < 0) {
  150. dev_err(ctx->dev, "unable to load firmware\n");
  151. return ret;
  152. }
  153. }
  154. /*
  155. * If any core other than core 0 is being moved to D0, enable the
  156. * core and send the set dx IPC for the core.
  157. */
  158. if (core_id != SKL_DSP_CORE0_ID) {
  159. ret = skl_dsp_enable_core(ctx, core_mask);
  160. if (ret < 0)
  161. return ret;
  162. dx.core_mask = core_mask;
  163. dx.dx_mask = core_mask;
  164. ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID,
  165. SKL_BASE_FW_MODULE_ID, &dx);
  166. if (ret < 0) {
  167. dev_err(ctx->dev, "Failed to set dsp to D0:core id= %d\n",
  168. core_id);
  169. skl_dsp_disable_core(ctx, core_mask);
  170. }
  171. }
  172. skl->cores.state[core_id] = SKL_DSP_RUNNING;
  173. return ret;
  174. }
  175. static int skl_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
  176. {
  177. int ret;
  178. struct skl_ipc_dxstate_info dx;
  179. struct skl_sst *skl = ctx->thread_context;
  180. unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
  181. dx.core_mask = core_mask;
  182. dx.dx_mask = SKL_IPC_D3_MASK;
  183. ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID, SKL_BASE_FW_MODULE_ID, &dx);
  184. if (ret < 0)
  185. dev_err(ctx->dev, "set Dx core %d fail: %d\n", core_id, ret);
  186. if (core_id == SKL_DSP_CORE0_ID) {
  187. /* disable Interrupt */
  188. ctx->cl_dev.ops.cl_cleanup_controller(ctx);
  189. skl_cldma_int_disable(ctx);
  190. skl_ipc_op_int_disable(ctx);
  191. skl_ipc_int_disable(ctx);
  192. }
  193. ret = skl_dsp_disable_core(ctx, core_mask);
  194. if (ret < 0)
  195. return ret;
  196. skl->cores.state[core_id] = SKL_DSP_RESET;
  197. return ret;
  198. }
  199. static unsigned int skl_get_errorcode(struct sst_dsp *ctx)
  200. {
  201. return sst_dsp_shim_read(ctx, SKL_ADSP_ERROR_CODE);
  202. }
  203. /*
  204. * since get/set_module are called from DAPM context,
  205. * we don't need lock for usage count
  206. */
  207. static int skl_get_module(struct sst_dsp *ctx, u16 mod_id)
  208. {
  209. struct skl_module_table *module;
  210. list_for_each_entry(module, &ctx->module_list, list) {
  211. if (module->mod_info->mod_id == mod_id)
  212. return ++module->usage_cnt;
  213. }
  214. return -EINVAL;
  215. }
  216. static int skl_put_module(struct sst_dsp *ctx, u16 mod_id)
  217. {
  218. struct skl_module_table *module;
  219. list_for_each_entry(module, &ctx->module_list, list) {
  220. if (module->mod_info->mod_id == mod_id)
  221. return --module->usage_cnt;
  222. }
  223. return -EINVAL;
  224. }
  225. static struct skl_module_table *skl_fill_module_table(struct sst_dsp *ctx,
  226. char *mod_name, int mod_id)
  227. {
  228. const struct firmware *fw;
  229. struct skl_module_table *skl_module;
  230. unsigned int size;
  231. int ret;
  232. ret = reject_firmware(&fw, mod_name, ctx->dev);
  233. if (ret < 0) {
  234. dev_err(ctx->dev, "Request Module %s failed :%d\n",
  235. mod_name, ret);
  236. return NULL;
  237. }
  238. skl_module = devm_kzalloc(ctx->dev, sizeof(*skl_module), GFP_KERNEL);
  239. if (skl_module == NULL) {
  240. release_firmware(fw);
  241. return NULL;
  242. }
  243. size = sizeof(*skl_module->mod_info);
  244. skl_module->mod_info = devm_kzalloc(ctx->dev, size, GFP_KERNEL);
  245. if (skl_module->mod_info == NULL) {
  246. release_firmware(fw);
  247. return NULL;
  248. }
  249. skl_module->mod_info->mod_id = mod_id;
  250. skl_module->mod_info->fw = fw;
  251. list_add(&skl_module->list, &ctx->module_list);
  252. return skl_module;
  253. }
  254. /* get a module from it's unique ID */
  255. static struct skl_module_table *skl_module_get_from_id(
  256. struct sst_dsp *ctx, u16 mod_id)
  257. {
  258. struct skl_module_table *module;
  259. if (list_empty(&ctx->module_list)) {
  260. dev_err(ctx->dev, "Module list is empty\n");
  261. return NULL;
  262. }
  263. list_for_each_entry(module, &ctx->module_list, list) {
  264. if (module->mod_info->mod_id == mod_id)
  265. return module;
  266. }
  267. return NULL;
  268. }
  269. static int skl_transfer_module(struct sst_dsp *ctx,
  270. struct skl_load_module_info *module)
  271. {
  272. int ret;
  273. struct skl_sst *skl = ctx->thread_context;
  274. ret = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx, module->fw->data,
  275. module->fw->size);
  276. if (ret < 0)
  277. return ret;
  278. ret = skl_ipc_load_modules(&skl->ipc, SKL_NUM_MODULES,
  279. (void *)&module->mod_id);
  280. if (ret < 0)
  281. dev_err(ctx->dev, "Failed to Load module: %d\n", ret);
  282. ctx->cl_dev.ops.cl_stop_dma(ctx);
  283. return ret;
  284. }
  285. static int skl_load_module(struct sst_dsp *ctx, u16 mod_id, u8 *guid)
  286. {
  287. struct skl_module_table *module_entry = NULL;
  288. int ret = 0;
  289. char mod_name[64]; /* guid str = 32 chars + 4 hyphens */
  290. uuid_le *uuid_mod;
  291. uuid_mod = (uuid_le *)guid;
  292. snprintf(mod_name, sizeof(mod_name), "/*(DEBLOBBED)*/");
  293. module_entry = skl_module_get_from_id(ctx, mod_id);
  294. if (module_entry == NULL) {
  295. module_entry = skl_fill_module_table(ctx, mod_name, mod_id);
  296. if (module_entry == NULL) {
  297. dev_err(ctx->dev, "Failed to Load module\n");
  298. return -EINVAL;
  299. }
  300. }
  301. if (!module_entry->usage_cnt) {
  302. ret = skl_transfer_module(ctx, module_entry->mod_info);
  303. if (ret < 0) {
  304. dev_err(ctx->dev, "Failed to Load module\n");
  305. return ret;
  306. }
  307. }
  308. ret = skl_get_module(ctx, mod_id);
  309. return ret;
  310. }
  311. static int skl_unload_module(struct sst_dsp *ctx, u16 mod_id)
  312. {
  313. int usage_cnt;
  314. struct skl_sst *skl = ctx->thread_context;
  315. int ret = 0;
  316. usage_cnt = skl_put_module(ctx, mod_id);
  317. if (usage_cnt < 0) {
  318. dev_err(ctx->dev, "Module bad usage cnt!:%d\n", usage_cnt);
  319. return -EIO;
  320. }
  321. ret = skl_ipc_unload_modules(&skl->ipc,
  322. SKL_NUM_MODULES, &mod_id);
  323. if (ret < 0) {
  324. dev_err(ctx->dev, "Failed to UnLoad module\n");
  325. skl_get_module(ctx, mod_id);
  326. return ret;
  327. }
  328. return ret;
  329. }
  330. void skl_clear_module_cnt(struct sst_dsp *ctx)
  331. {
  332. struct skl_module_table *module;
  333. if (list_empty(&ctx->module_list))
  334. return;
  335. list_for_each_entry(module, &ctx->module_list, list) {
  336. module->usage_cnt = 0;
  337. }
  338. }
  339. EXPORT_SYMBOL_GPL(skl_clear_module_cnt);
  340. static void skl_clear_module_table(struct sst_dsp *ctx)
  341. {
  342. struct skl_module_table *module, *tmp;
  343. if (list_empty(&ctx->module_list))
  344. return;
  345. list_for_each_entry_safe(module, tmp, &ctx->module_list, list) {
  346. list_del(&module->list);
  347. release_firmware(module->mod_info->fw);
  348. }
  349. }
  350. static struct skl_dsp_fw_ops skl_fw_ops = {
  351. .set_state_D0 = skl_set_dsp_D0,
  352. .set_state_D3 = skl_set_dsp_D3,
  353. .load_fw = skl_load_base_firmware,
  354. .get_fw_errcode = skl_get_errorcode,
  355. .load_mod = skl_load_module,
  356. .unload_mod = skl_unload_module,
  357. };
  358. static struct sst_ops skl_ops = {
  359. .irq_handler = skl_dsp_sst_interrupt,
  360. .write = sst_shim32_write,
  361. .read = sst_shim32_read,
  362. .ram_read = sst_memcpy_fromio_32,
  363. .ram_write = sst_memcpy_toio_32,
  364. .free = skl_dsp_free,
  365. };
  366. static struct sst_dsp_device skl_dev = {
  367. .thread = skl_dsp_irq_thread_handler,
  368. .ops = &skl_ops,
  369. };
  370. int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
  371. const char *fw_name, struct skl_dsp_loader_ops dsp_ops, struct skl_sst **dsp)
  372. {
  373. struct skl_sst *skl;
  374. struct sst_dsp *sst;
  375. int ret;
  376. skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL);
  377. if (skl == NULL)
  378. return -ENOMEM;
  379. skl->dev = dev;
  380. skl_dev.thread_context = skl;
  381. INIT_LIST_HEAD(&skl->uuid_list);
  382. skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq);
  383. if (!skl->dsp) {
  384. dev_err(skl->dev, "%s: no device\n", __func__);
  385. return -ENODEV;
  386. }
  387. sst = skl->dsp;
  388. sst->fw_name = fw_name;
  389. sst->addr.lpe = mmio_base;
  390. sst->addr.shim = mmio_base;
  391. sst_dsp_mailbox_init(sst, (SKL_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
  392. SKL_ADSP_W0_UP_SZ, SKL_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
  393. INIT_LIST_HEAD(&sst->module_list);
  394. sst->dsp_ops = dsp_ops;
  395. sst->fw_ops = skl_fw_ops;
  396. ret = skl_ipc_init(dev, skl);
  397. if (ret)
  398. return ret;
  399. skl->cores.count = 2;
  400. skl->is_first_boot = true;
  401. if (dsp)
  402. *dsp = skl;
  403. return ret;
  404. }
  405. EXPORT_SYMBOL_GPL(skl_sst_dsp_init);
  406. int skl_sst_init_fw(struct device *dev, struct skl_sst *ctx)
  407. {
  408. int ret;
  409. struct sst_dsp *sst = ctx->dsp;
  410. ret = sst->fw_ops.load_fw(sst);
  411. if (ret < 0) {
  412. dev_err(dev, "Load base fw failed : %d\n", ret);
  413. return ret;
  414. }
  415. skl_dsp_init_core_state(sst);
  416. ctx->is_first_boot = false;
  417. return 0;
  418. }
  419. EXPORT_SYMBOL_GPL(skl_sst_init_fw);
  420. void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
  421. {
  422. if (ctx->dsp->fw)
  423. release_firmware(ctx->dsp->fw);
  424. skl_clear_module_table(ctx->dsp);
  425. skl_freeup_uuid_list(ctx);
  426. skl_ipc_free(&ctx->ipc);
  427. ctx->dsp->ops->free(ctx->dsp);
  428. if (ctx->boot_complete) {
  429. ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp);
  430. skl_cldma_int_disable(ctx->dsp);
  431. }
  432. }
  433. EXPORT_SYMBOL_GPL(skl_sst_dsp_cleanup);
  434. MODULE_LICENSE("GPL v2");
  435. MODULE_DESCRIPTION("Intel Skylake IPC driver");