skl-sst-ipc.c 27 KB

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  1. /*
  2. * skl-sst-ipc.c - Intel skl IPC Support
  3. *
  4. * Copyright (C) 2014-15, Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as version 2, as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. */
  15. #include <linux/device.h>
  16. #include "../common/sst-dsp.h"
  17. #include "../common/sst-dsp-priv.h"
  18. #include "skl.h"
  19. #include "skl-sst-dsp.h"
  20. #include "skl-sst-ipc.h"
  21. #include "sound/hdaudio_ext.h"
  22. #define IPC_IXC_STATUS_BITS 24
  23. /* Global Message - Generic */
  24. #define IPC_GLB_TYPE_SHIFT 24
  25. #define IPC_GLB_TYPE_MASK (0xf << IPC_GLB_TYPE_SHIFT)
  26. #define IPC_GLB_TYPE(x) ((x) << IPC_GLB_TYPE_SHIFT)
  27. /* Global Message - Reply */
  28. #define IPC_GLB_REPLY_STATUS_SHIFT 24
  29. #define IPC_GLB_REPLY_STATUS_MASK ((0x1 << IPC_GLB_REPLY_STATUS_SHIFT) - 1)
  30. #define IPC_GLB_REPLY_STATUS(x) ((x) << IPC_GLB_REPLY_STATUS_SHIFT)
  31. #define IPC_TIMEOUT_MSECS 3000
  32. #define IPC_EMPTY_LIST_SIZE 8
  33. #define IPC_MSG_TARGET_SHIFT 30
  34. #define IPC_MSG_TARGET_MASK 0x1
  35. #define IPC_MSG_TARGET(x) (((x) & IPC_MSG_TARGET_MASK) \
  36. << IPC_MSG_TARGET_SHIFT)
  37. #define IPC_MSG_DIR_SHIFT 29
  38. #define IPC_MSG_DIR_MASK 0x1
  39. #define IPC_MSG_DIR(x) (((x) & IPC_MSG_DIR_MASK) \
  40. << IPC_MSG_DIR_SHIFT)
  41. /* Global Notification Message */
  42. #define IPC_GLB_NOTIFY_TYPE_SHIFT 16
  43. #define IPC_GLB_NOTIFY_TYPE_MASK 0xFF
  44. #define IPC_GLB_NOTIFY_TYPE(x) (((x) >> IPC_GLB_NOTIFY_TYPE_SHIFT) \
  45. & IPC_GLB_NOTIFY_TYPE_MASK)
  46. #define IPC_GLB_NOTIFY_MSG_TYPE_SHIFT 24
  47. #define IPC_GLB_NOTIFY_MSG_TYPE_MASK 0x1F
  48. #define IPC_GLB_NOTIFY_MSG_TYPE(x) (((x) >> IPC_GLB_NOTIFY_MSG_TYPE_SHIFT) \
  49. & IPC_GLB_NOTIFY_MSG_TYPE_MASK)
  50. #define IPC_GLB_NOTIFY_RSP_SHIFT 29
  51. #define IPC_GLB_NOTIFY_RSP_MASK 0x1
  52. #define IPC_GLB_NOTIFY_RSP_TYPE(x) (((x) >> IPC_GLB_NOTIFY_RSP_SHIFT) \
  53. & IPC_GLB_NOTIFY_RSP_MASK)
  54. /* Pipeline operations */
  55. /* Create pipeline message */
  56. #define IPC_PPL_MEM_SIZE_SHIFT 0
  57. #define IPC_PPL_MEM_SIZE_MASK 0x7FF
  58. #define IPC_PPL_MEM_SIZE(x) (((x) & IPC_PPL_MEM_SIZE_MASK) \
  59. << IPC_PPL_MEM_SIZE_SHIFT)
  60. #define IPC_PPL_TYPE_SHIFT 11
  61. #define IPC_PPL_TYPE_MASK 0x1F
  62. #define IPC_PPL_TYPE(x) (((x) & IPC_PPL_TYPE_MASK) \
  63. << IPC_PPL_TYPE_SHIFT)
  64. #define IPC_INSTANCE_ID_SHIFT 16
  65. #define IPC_INSTANCE_ID_MASK 0xFF
  66. #define IPC_INSTANCE_ID(x) (((x) & IPC_INSTANCE_ID_MASK) \
  67. << IPC_INSTANCE_ID_SHIFT)
  68. /* Set pipeline state message */
  69. #define IPC_PPL_STATE_SHIFT 0
  70. #define IPC_PPL_STATE_MASK 0x1F
  71. #define IPC_PPL_STATE(x) (((x) & IPC_PPL_STATE_MASK) \
  72. << IPC_PPL_STATE_SHIFT)
  73. /* Module operations primary register */
  74. #define IPC_MOD_ID_SHIFT 0
  75. #define IPC_MOD_ID_MASK 0xFFFF
  76. #define IPC_MOD_ID(x) (((x) & IPC_MOD_ID_MASK) \
  77. << IPC_MOD_ID_SHIFT)
  78. #define IPC_MOD_INSTANCE_ID_SHIFT 16
  79. #define IPC_MOD_INSTANCE_ID_MASK 0xFF
  80. #define IPC_MOD_INSTANCE_ID(x) (((x) & IPC_MOD_INSTANCE_ID_MASK) \
  81. << IPC_MOD_INSTANCE_ID_SHIFT)
  82. /* Init instance message extension register */
  83. #define IPC_PARAM_BLOCK_SIZE_SHIFT 0
  84. #define IPC_PARAM_BLOCK_SIZE_MASK 0xFFFF
  85. #define IPC_PARAM_BLOCK_SIZE(x) (((x) & IPC_PARAM_BLOCK_SIZE_MASK) \
  86. << IPC_PARAM_BLOCK_SIZE_SHIFT)
  87. #define IPC_PPL_INSTANCE_ID_SHIFT 16
  88. #define IPC_PPL_INSTANCE_ID_MASK 0xFF
  89. #define IPC_PPL_INSTANCE_ID(x) (((x) & IPC_PPL_INSTANCE_ID_MASK) \
  90. << IPC_PPL_INSTANCE_ID_SHIFT)
  91. #define IPC_CORE_ID_SHIFT 24
  92. #define IPC_CORE_ID_MASK 0x1F
  93. #define IPC_CORE_ID(x) (((x) & IPC_CORE_ID_MASK) \
  94. << IPC_CORE_ID_SHIFT)
  95. #define IPC_DOMAIN_SHIFT 28
  96. #define IPC_DOMAIN_MASK 0x1
  97. #define IPC_DOMAIN(x) (((x) & IPC_DOMAIN_MASK) \
  98. << IPC_DOMAIN_SHIFT)
  99. /* Bind/Unbind message extension register */
  100. #define IPC_DST_MOD_ID_SHIFT 0
  101. #define IPC_DST_MOD_ID(x) (((x) & IPC_MOD_ID_MASK) \
  102. << IPC_DST_MOD_ID_SHIFT)
  103. #define IPC_DST_MOD_INSTANCE_ID_SHIFT 16
  104. #define IPC_DST_MOD_INSTANCE_ID(x) (((x) & IPC_MOD_INSTANCE_ID_MASK) \
  105. << IPC_DST_MOD_INSTANCE_ID_SHIFT)
  106. #define IPC_DST_QUEUE_SHIFT 24
  107. #define IPC_DST_QUEUE_MASK 0x7
  108. #define IPC_DST_QUEUE(x) (((x) & IPC_DST_QUEUE_MASK) \
  109. << IPC_DST_QUEUE_SHIFT)
  110. #define IPC_SRC_QUEUE_SHIFT 27
  111. #define IPC_SRC_QUEUE_MASK 0x7
  112. #define IPC_SRC_QUEUE(x) (((x) & IPC_SRC_QUEUE_MASK) \
  113. << IPC_SRC_QUEUE_SHIFT)
  114. /* Load Module count */
  115. #define IPC_LOAD_MODULE_SHIFT 0
  116. #define IPC_LOAD_MODULE_MASK 0xFF
  117. #define IPC_LOAD_MODULE_CNT(x) (((x) & IPC_LOAD_MODULE_MASK) \
  118. << IPC_LOAD_MODULE_SHIFT)
  119. /* Save pipeline messgae extension register */
  120. #define IPC_DMA_ID_SHIFT 0
  121. #define IPC_DMA_ID_MASK 0x1F
  122. #define IPC_DMA_ID(x) (((x) & IPC_DMA_ID_MASK) \
  123. << IPC_DMA_ID_SHIFT)
  124. /* Large Config message extension register */
  125. #define IPC_DATA_OFFSET_SZ_SHIFT 0
  126. #define IPC_DATA_OFFSET_SZ_MASK 0xFFFFF
  127. #define IPC_DATA_OFFSET_SZ(x) (((x) & IPC_DATA_OFFSET_SZ_MASK) \
  128. << IPC_DATA_OFFSET_SZ_SHIFT)
  129. #define IPC_DATA_OFFSET_SZ_CLEAR ~(IPC_DATA_OFFSET_SZ_MASK \
  130. << IPC_DATA_OFFSET_SZ_SHIFT)
  131. #define IPC_LARGE_PARAM_ID_SHIFT 20
  132. #define IPC_LARGE_PARAM_ID_MASK 0xFF
  133. #define IPC_LARGE_PARAM_ID(x) (((x) & IPC_LARGE_PARAM_ID_MASK) \
  134. << IPC_LARGE_PARAM_ID_SHIFT)
  135. #define IPC_FINAL_BLOCK_SHIFT 28
  136. #define IPC_FINAL_BLOCK_MASK 0x1
  137. #define IPC_FINAL_BLOCK(x) (((x) & IPC_FINAL_BLOCK_MASK) \
  138. << IPC_FINAL_BLOCK_SHIFT)
  139. #define IPC_INITIAL_BLOCK_SHIFT 29
  140. #define IPC_INITIAL_BLOCK_MASK 0x1
  141. #define IPC_INITIAL_BLOCK(x) (((x) & IPC_INITIAL_BLOCK_MASK) \
  142. << IPC_INITIAL_BLOCK_SHIFT)
  143. #define IPC_INITIAL_BLOCK_CLEAR ~(IPC_INITIAL_BLOCK_MASK \
  144. << IPC_INITIAL_BLOCK_SHIFT)
  145. enum skl_ipc_msg_target {
  146. IPC_FW_GEN_MSG = 0,
  147. IPC_MOD_MSG = 1
  148. };
  149. enum skl_ipc_msg_direction {
  150. IPC_MSG_REQUEST = 0,
  151. IPC_MSG_REPLY = 1
  152. };
  153. /* Global Message Types */
  154. enum skl_ipc_glb_type {
  155. IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
  156. IPC_GLB_LOAD_MULTIPLE_MODS = 15,
  157. IPC_GLB_UNLOAD_MULTIPLE_MODS = 16,
  158. IPC_GLB_CREATE_PPL = 17,
  159. IPC_GLB_DELETE_PPL = 18,
  160. IPC_GLB_SET_PPL_STATE = 19,
  161. IPC_GLB_GET_PPL_STATE = 20,
  162. IPC_GLB_GET_PPL_CONTEXT_SIZE = 21,
  163. IPC_GLB_SAVE_PPL = 22,
  164. IPC_GLB_RESTORE_PPL = 23,
  165. IPC_GLB_LOAD_LIBRARY = 24,
  166. IPC_GLB_NOTIFY = 26,
  167. IPC_GLB_MAX_IPC_MSG_NUMBER = 31 /* Maximum message number */
  168. };
  169. enum skl_ipc_glb_reply {
  170. IPC_GLB_REPLY_SUCCESS = 0,
  171. IPC_GLB_REPLY_UNKNOWN_MSG_TYPE = 1,
  172. IPC_GLB_REPLY_ERROR_INVALID_PARAM = 2,
  173. IPC_GLB_REPLY_BUSY = 3,
  174. IPC_GLB_REPLY_PENDING = 4,
  175. IPC_GLB_REPLY_FAILURE = 5,
  176. IPC_GLB_REPLY_INVALID_REQUEST = 6,
  177. IPC_GLB_REPLY_OUT_OF_MEMORY = 7,
  178. IPC_GLB_REPLY_OUT_OF_MIPS = 8,
  179. IPC_GLB_REPLY_INVALID_RESOURCE_ID = 9,
  180. IPC_GLB_REPLY_INVALID_RESOURCE_STATE = 10,
  181. IPC_GLB_REPLY_MOD_MGMT_ERROR = 100,
  182. IPC_GLB_REPLY_MOD_LOAD_CL_FAILED = 101,
  183. IPC_GLB_REPLY_MOD_LOAD_INVALID_HASH = 102,
  184. IPC_GLB_REPLY_MOD_UNLOAD_INST_EXIST = 103,
  185. IPC_GLB_REPLY_MOD_NOT_INITIALIZED = 104,
  186. IPC_GLB_REPLY_INVALID_CONFIG_PARAM_ID = 120,
  187. IPC_GLB_REPLY_INVALID_CONFIG_DATA_LEN = 121,
  188. IPC_GLB_REPLY_GATEWAY_NOT_INITIALIZED = 140,
  189. IPC_GLB_REPLY_GATEWAY_NOT_EXIST = 141,
  190. IPC_GLB_REPLY_PPL_NOT_INITIALIZED = 160,
  191. IPC_GLB_REPLY_PPL_NOT_EXIST = 161,
  192. IPC_GLB_REPLY_PPL_SAVE_FAILED = 162,
  193. IPC_GLB_REPLY_PPL_RESTORE_FAILED = 163,
  194. IPC_MAX_STATUS = ((1<<IPC_IXC_STATUS_BITS)-1)
  195. };
  196. enum skl_ipc_notification_type {
  197. IPC_GLB_NOTIFY_GLITCH = 0,
  198. IPC_GLB_NOTIFY_OVERRUN = 1,
  199. IPC_GLB_NOTIFY_UNDERRUN = 2,
  200. IPC_GLB_NOTIFY_END_STREAM = 3,
  201. IPC_GLB_NOTIFY_PHRASE_DETECTED = 4,
  202. IPC_GLB_NOTIFY_RESOURCE_EVENT = 5,
  203. IPC_GLB_NOTIFY_LOG_BUFFER_STATUS = 6,
  204. IPC_GLB_NOTIFY_TIMESTAMP_CAPTURED = 7,
  205. IPC_GLB_NOTIFY_FW_READY = 8
  206. };
  207. /* Module Message Types */
  208. enum skl_ipc_module_msg {
  209. IPC_MOD_INIT_INSTANCE = 0,
  210. IPC_MOD_CONFIG_GET = 1,
  211. IPC_MOD_CONFIG_SET = 2,
  212. IPC_MOD_LARGE_CONFIG_GET = 3,
  213. IPC_MOD_LARGE_CONFIG_SET = 4,
  214. IPC_MOD_BIND = 5,
  215. IPC_MOD_UNBIND = 6,
  216. IPC_MOD_SET_DX = 7
  217. };
  218. static void skl_ipc_tx_data_copy(struct ipc_message *msg, char *tx_data,
  219. size_t tx_size)
  220. {
  221. if (tx_size)
  222. memcpy(msg->tx_data, tx_data, tx_size);
  223. }
  224. static bool skl_ipc_is_dsp_busy(struct sst_dsp *dsp)
  225. {
  226. u32 hipci;
  227. hipci = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCI);
  228. return (hipci & SKL_ADSP_REG_HIPCI_BUSY);
  229. }
  230. /* Lock to be held by caller */
  231. static void skl_ipc_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
  232. {
  233. struct skl_ipc_header *header = (struct skl_ipc_header *)(&msg->header);
  234. if (msg->tx_size)
  235. sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
  236. sst_dsp_shim_write_unlocked(ipc->dsp, SKL_ADSP_REG_HIPCIE,
  237. header->extension);
  238. sst_dsp_shim_write_unlocked(ipc->dsp, SKL_ADSP_REG_HIPCI,
  239. header->primary | SKL_ADSP_REG_HIPCI_BUSY);
  240. }
  241. static struct ipc_message *skl_ipc_reply_get_msg(struct sst_generic_ipc *ipc,
  242. u64 ipc_header)
  243. {
  244. struct ipc_message *msg = NULL;
  245. struct skl_ipc_header *header = (struct skl_ipc_header *)(&ipc_header);
  246. if (list_empty(&ipc->rx_list)) {
  247. dev_err(ipc->dev, "ipc: rx list is empty but received 0x%x\n",
  248. header->primary);
  249. goto out;
  250. }
  251. msg = list_first_entry(&ipc->rx_list, struct ipc_message, list);
  252. out:
  253. return msg;
  254. }
  255. static int skl_ipc_process_notification(struct sst_generic_ipc *ipc,
  256. struct skl_ipc_header header)
  257. {
  258. struct skl_sst *skl = container_of(ipc, struct skl_sst, ipc);
  259. if (IPC_GLB_NOTIFY_MSG_TYPE(header.primary)) {
  260. switch (IPC_GLB_NOTIFY_TYPE(header.primary)) {
  261. case IPC_GLB_NOTIFY_UNDERRUN:
  262. dev_err(ipc->dev, "FW Underrun %x\n", header.primary);
  263. break;
  264. case IPC_GLB_NOTIFY_RESOURCE_EVENT:
  265. dev_err(ipc->dev, "MCPS Budget Violation: %x\n",
  266. header.primary);
  267. break;
  268. case IPC_GLB_NOTIFY_FW_READY:
  269. skl->boot_complete = true;
  270. wake_up(&skl->boot_wait);
  271. break;
  272. case IPC_GLB_NOTIFY_PHRASE_DETECTED:
  273. dev_dbg(ipc->dev, "***** Phrase Detected **********\n");
  274. /*
  275. * Per HW recomendation, After phrase detection,
  276. * clear the CGCTL.MISCBDCGE.
  277. *
  278. * This will be set back on stream closure
  279. */
  280. skl->enable_miscbdcge(ipc->dev, false);
  281. skl->miscbdcg_disabled = true;
  282. break;
  283. default:
  284. dev_err(ipc->dev, "ipc: Unhandled error msg=%x\n",
  285. header.primary);
  286. break;
  287. }
  288. }
  289. return 0;
  290. }
  291. static void skl_ipc_process_reply(struct sst_generic_ipc *ipc,
  292. struct skl_ipc_header header)
  293. {
  294. struct ipc_message *msg;
  295. u32 reply = header.primary & IPC_GLB_REPLY_STATUS_MASK;
  296. u64 *ipc_header = (u64 *)(&header);
  297. msg = skl_ipc_reply_get_msg(ipc, *ipc_header);
  298. if (msg == NULL) {
  299. dev_dbg(ipc->dev, "ipc: rx list is empty\n");
  300. return;
  301. }
  302. /* first process the header */
  303. switch (reply) {
  304. case IPC_GLB_REPLY_SUCCESS:
  305. dev_dbg(ipc->dev, "ipc FW reply %x: success\n", header.primary);
  306. /* copy the rx data from the mailbox */
  307. sst_dsp_inbox_read(ipc->dsp, msg->rx_data, msg->rx_size);
  308. break;
  309. case IPC_GLB_REPLY_OUT_OF_MEMORY:
  310. dev_err(ipc->dev, "ipc fw reply: %x: no memory\n", header.primary);
  311. msg->errno = -ENOMEM;
  312. break;
  313. case IPC_GLB_REPLY_BUSY:
  314. dev_err(ipc->dev, "ipc fw reply: %x: Busy\n", header.primary);
  315. msg->errno = -EBUSY;
  316. break;
  317. default:
  318. dev_err(ipc->dev, "Unknown ipc reply: 0x%x\n", reply);
  319. msg->errno = -EINVAL;
  320. break;
  321. }
  322. if (reply != IPC_GLB_REPLY_SUCCESS) {
  323. dev_err(ipc->dev, "ipc FW reply: reply=%d\n", reply);
  324. dev_err(ipc->dev, "FW Error Code: %u\n",
  325. ipc->dsp->fw_ops.get_fw_errcode(ipc->dsp));
  326. }
  327. list_del(&msg->list);
  328. sst_ipc_tx_msg_reply_complete(ipc, msg);
  329. }
  330. irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context)
  331. {
  332. struct sst_dsp *dsp = context;
  333. struct skl_sst *skl = sst_dsp_get_thread_context(dsp);
  334. struct sst_generic_ipc *ipc = &skl->ipc;
  335. struct skl_ipc_header header = {0};
  336. u32 hipcie, hipct, hipcte;
  337. int ipc_irq = 0;
  338. if (dsp->intr_status & SKL_ADSPIS_CL_DMA)
  339. skl_cldma_process_intr(dsp);
  340. /* Here we handle IPC interrupts only */
  341. if (!(dsp->intr_status & SKL_ADSPIS_IPC))
  342. return IRQ_NONE;
  343. hipcie = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCIE);
  344. hipct = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCT);
  345. /* reply message from DSP */
  346. if (hipcie & SKL_ADSP_REG_HIPCIE_DONE) {
  347. sst_dsp_shim_update_bits(dsp, SKL_ADSP_REG_HIPCCTL,
  348. SKL_ADSP_REG_HIPCCTL_DONE, 0);
  349. /* clear DONE bit - tell DSP we have completed the operation */
  350. sst_dsp_shim_update_bits_forced(dsp, SKL_ADSP_REG_HIPCIE,
  351. SKL_ADSP_REG_HIPCIE_DONE, SKL_ADSP_REG_HIPCIE_DONE);
  352. ipc_irq = 1;
  353. /* unmask Done interrupt */
  354. sst_dsp_shim_update_bits(dsp, SKL_ADSP_REG_HIPCCTL,
  355. SKL_ADSP_REG_HIPCCTL_DONE, SKL_ADSP_REG_HIPCCTL_DONE);
  356. }
  357. /* New message from DSP */
  358. if (hipct & SKL_ADSP_REG_HIPCT_BUSY) {
  359. hipcte = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCTE);
  360. header.primary = hipct;
  361. header.extension = hipcte;
  362. dev_dbg(dsp->dev, "IPC irq: Firmware respond primary:%x\n",
  363. header.primary);
  364. dev_dbg(dsp->dev, "IPC irq: Firmware respond extension:%x\n",
  365. header.extension);
  366. if (IPC_GLB_NOTIFY_RSP_TYPE(header.primary)) {
  367. /* Handle Immediate reply from DSP Core */
  368. skl_ipc_process_reply(ipc, header);
  369. } else {
  370. dev_dbg(dsp->dev, "IPC irq: Notification from firmware\n");
  371. skl_ipc_process_notification(ipc, header);
  372. }
  373. /* clear busy interrupt */
  374. sst_dsp_shim_update_bits_forced(dsp, SKL_ADSP_REG_HIPCT,
  375. SKL_ADSP_REG_HIPCT_BUSY, SKL_ADSP_REG_HIPCT_BUSY);
  376. ipc_irq = 1;
  377. }
  378. if (ipc_irq == 0)
  379. return IRQ_NONE;
  380. skl_ipc_int_enable(dsp);
  381. /* continue to send any remaining messages... */
  382. kthread_queue_work(&ipc->kworker, &ipc->kwork);
  383. return IRQ_HANDLED;
  384. }
  385. void skl_ipc_int_enable(struct sst_dsp *ctx)
  386. {
  387. sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_ADSPIC,
  388. SKL_ADSPIC_IPC, SKL_ADSPIC_IPC);
  389. }
  390. void skl_ipc_int_disable(struct sst_dsp *ctx)
  391. {
  392. sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
  393. SKL_ADSPIC_IPC, 0);
  394. }
  395. void skl_ipc_op_int_enable(struct sst_dsp *ctx)
  396. {
  397. /* enable IPC DONE interrupt */
  398. sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCCTL,
  399. SKL_ADSP_REG_HIPCCTL_DONE, SKL_ADSP_REG_HIPCCTL_DONE);
  400. /* Enable IPC BUSY interrupt */
  401. sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCCTL,
  402. SKL_ADSP_REG_HIPCCTL_BUSY, SKL_ADSP_REG_HIPCCTL_BUSY);
  403. }
  404. void skl_ipc_op_int_disable(struct sst_dsp *ctx)
  405. {
  406. /* disable IPC DONE interrupt */
  407. sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_HIPCCTL,
  408. SKL_ADSP_REG_HIPCCTL_DONE, 0);
  409. /* Disable IPC BUSY interrupt */
  410. sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_HIPCCTL,
  411. SKL_ADSP_REG_HIPCCTL_BUSY, 0);
  412. }
  413. bool skl_ipc_int_status(struct sst_dsp *ctx)
  414. {
  415. return sst_dsp_shim_read_unlocked(ctx,
  416. SKL_ADSP_REG_ADSPIS) & SKL_ADSPIS_IPC;
  417. }
  418. int skl_ipc_init(struct device *dev, struct skl_sst *skl)
  419. {
  420. struct sst_generic_ipc *ipc;
  421. int err;
  422. ipc = &skl->ipc;
  423. ipc->dsp = skl->dsp;
  424. ipc->dev = dev;
  425. ipc->tx_data_max_size = SKL_ADSP_W1_SZ;
  426. ipc->rx_data_max_size = SKL_ADSP_W0_UP_SZ;
  427. err = sst_ipc_init(ipc);
  428. if (err)
  429. return err;
  430. ipc->ops.tx_msg = skl_ipc_tx_msg;
  431. ipc->ops.tx_data_copy = skl_ipc_tx_data_copy;
  432. ipc->ops.is_dsp_busy = skl_ipc_is_dsp_busy;
  433. return 0;
  434. }
  435. void skl_ipc_free(struct sst_generic_ipc *ipc)
  436. {
  437. /* Disable IPC DONE interrupt */
  438. sst_dsp_shim_update_bits(ipc->dsp, SKL_ADSP_REG_HIPCCTL,
  439. SKL_ADSP_REG_HIPCCTL_DONE, 0);
  440. /* Disable IPC BUSY interrupt */
  441. sst_dsp_shim_update_bits(ipc->dsp, SKL_ADSP_REG_HIPCCTL,
  442. SKL_ADSP_REG_HIPCCTL_BUSY, 0);
  443. sst_ipc_fini(ipc);
  444. }
  445. int skl_ipc_create_pipeline(struct sst_generic_ipc *ipc,
  446. u16 ppl_mem_size, u8 ppl_type, u8 instance_id)
  447. {
  448. struct skl_ipc_header header = {0};
  449. u64 *ipc_header = (u64 *)(&header);
  450. int ret;
  451. header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
  452. header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
  453. header.primary |= IPC_GLB_TYPE(IPC_GLB_CREATE_PPL);
  454. header.primary |= IPC_INSTANCE_ID(instance_id);
  455. header.primary |= IPC_PPL_TYPE(ppl_type);
  456. header.primary |= IPC_PPL_MEM_SIZE(ppl_mem_size);
  457. dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
  458. ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
  459. if (ret < 0) {
  460. dev_err(ipc->dev, "ipc: create pipeline fail, err: %d\n", ret);
  461. return ret;
  462. }
  463. return ret;
  464. }
  465. EXPORT_SYMBOL_GPL(skl_ipc_create_pipeline);
  466. int skl_ipc_delete_pipeline(struct sst_generic_ipc *ipc, u8 instance_id)
  467. {
  468. struct skl_ipc_header header = {0};
  469. u64 *ipc_header = (u64 *)(&header);
  470. int ret;
  471. header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
  472. header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
  473. header.primary |= IPC_GLB_TYPE(IPC_GLB_DELETE_PPL);
  474. header.primary |= IPC_INSTANCE_ID(instance_id);
  475. dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
  476. ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
  477. if (ret < 0) {
  478. dev_err(ipc->dev, "ipc: delete pipeline failed, err %d\n", ret);
  479. return ret;
  480. }
  481. return 0;
  482. }
  483. EXPORT_SYMBOL_GPL(skl_ipc_delete_pipeline);
  484. int skl_ipc_set_pipeline_state(struct sst_generic_ipc *ipc,
  485. u8 instance_id, enum skl_ipc_pipeline_state state)
  486. {
  487. struct skl_ipc_header header = {0};
  488. u64 *ipc_header = (u64 *)(&header);
  489. int ret;
  490. header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
  491. header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
  492. header.primary |= IPC_GLB_TYPE(IPC_GLB_SET_PPL_STATE);
  493. header.primary |= IPC_INSTANCE_ID(instance_id);
  494. header.primary |= IPC_PPL_STATE(state);
  495. dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
  496. ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
  497. if (ret < 0) {
  498. dev_err(ipc->dev, "ipc: set pipeline state failed, err: %d\n", ret);
  499. return ret;
  500. }
  501. return ret;
  502. }
  503. EXPORT_SYMBOL_GPL(skl_ipc_set_pipeline_state);
  504. int
  505. skl_ipc_save_pipeline(struct sst_generic_ipc *ipc, u8 instance_id, int dma_id)
  506. {
  507. struct skl_ipc_header header = {0};
  508. u64 *ipc_header = (u64 *)(&header);
  509. int ret;
  510. header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
  511. header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
  512. header.primary |= IPC_GLB_TYPE(IPC_GLB_SAVE_PPL);
  513. header.primary |= IPC_INSTANCE_ID(instance_id);
  514. header.extension = IPC_DMA_ID(dma_id);
  515. dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
  516. ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
  517. if (ret < 0) {
  518. dev_err(ipc->dev, "ipc: save pipeline failed, err: %d\n", ret);
  519. return ret;
  520. }
  521. return ret;
  522. }
  523. EXPORT_SYMBOL_GPL(skl_ipc_save_pipeline);
  524. int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id)
  525. {
  526. struct skl_ipc_header header = {0};
  527. u64 *ipc_header = (u64 *)(&header);
  528. int ret;
  529. header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
  530. header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
  531. header.primary |= IPC_GLB_TYPE(IPC_GLB_RESTORE_PPL);
  532. header.primary |= IPC_INSTANCE_ID(instance_id);
  533. dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
  534. ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
  535. if (ret < 0) {
  536. dev_err(ipc->dev, "ipc: restore pipeline failed, err: %d\n", ret);
  537. return ret;
  538. }
  539. return ret;
  540. }
  541. EXPORT_SYMBOL_GPL(skl_ipc_restore_pipeline);
  542. int skl_ipc_set_dx(struct sst_generic_ipc *ipc, u8 instance_id,
  543. u16 module_id, struct skl_ipc_dxstate_info *dx)
  544. {
  545. struct skl_ipc_header header = {0};
  546. u64 *ipc_header = (u64 *)(&header);
  547. int ret;
  548. header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
  549. header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
  550. header.primary |= IPC_GLB_TYPE(IPC_MOD_SET_DX);
  551. header.primary |= IPC_MOD_INSTANCE_ID(instance_id);
  552. header.primary |= IPC_MOD_ID(module_id);
  553. dev_dbg(ipc->dev, "In %s primary =%x ext=%x\n", __func__,
  554. header.primary, header.extension);
  555. ret = sst_ipc_tx_message_wait(ipc, *ipc_header,
  556. dx, sizeof(*dx), NULL, 0);
  557. if (ret < 0) {
  558. dev_err(ipc->dev, "ipc: set dx failed, err %d\n", ret);
  559. return ret;
  560. }
  561. return ret;
  562. }
  563. EXPORT_SYMBOL_GPL(skl_ipc_set_dx);
  564. int skl_ipc_init_instance(struct sst_generic_ipc *ipc,
  565. struct skl_ipc_init_instance_msg *msg, void *param_data)
  566. {
  567. struct skl_ipc_header header = {0};
  568. u64 *ipc_header = (u64 *)(&header);
  569. int ret;
  570. u32 *buffer = (u32 *)param_data;
  571. /* param_block_size must be in dwords */
  572. u16 param_block_size = msg->param_data_size / sizeof(u32);
  573. print_hex_dump_debug("Param data:", DUMP_PREFIX_NONE,
  574. 16, 4, buffer, param_block_size, false);
  575. header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
  576. header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
  577. header.primary |= IPC_GLB_TYPE(IPC_MOD_INIT_INSTANCE);
  578. header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
  579. header.primary |= IPC_MOD_ID(msg->module_id);
  580. header.extension = IPC_CORE_ID(msg->core_id);
  581. header.extension |= IPC_PPL_INSTANCE_ID(msg->ppl_instance_id);
  582. header.extension |= IPC_PARAM_BLOCK_SIZE(param_block_size);
  583. header.extension |= IPC_DOMAIN(msg->domain);
  584. dev_dbg(ipc->dev, "In %s primary =%x ext=%x\n", __func__,
  585. header.primary, header.extension);
  586. ret = sst_ipc_tx_message_wait(ipc, *ipc_header, param_data,
  587. msg->param_data_size, NULL, 0);
  588. if (ret < 0) {
  589. dev_err(ipc->dev, "ipc: init instance failed\n");
  590. return ret;
  591. }
  592. return ret;
  593. }
  594. EXPORT_SYMBOL_GPL(skl_ipc_init_instance);
  595. int skl_ipc_bind_unbind(struct sst_generic_ipc *ipc,
  596. struct skl_ipc_bind_unbind_msg *msg)
  597. {
  598. struct skl_ipc_header header = {0};
  599. u64 *ipc_header = (u64 *)(&header);
  600. u8 bind_unbind = msg->bind ? IPC_MOD_BIND : IPC_MOD_UNBIND;
  601. int ret;
  602. header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
  603. header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
  604. header.primary |= IPC_GLB_TYPE(bind_unbind);
  605. header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
  606. header.primary |= IPC_MOD_ID(msg->module_id);
  607. header.extension = IPC_DST_MOD_ID(msg->dst_module_id);
  608. header.extension |= IPC_DST_MOD_INSTANCE_ID(msg->dst_instance_id);
  609. header.extension |= IPC_DST_QUEUE(msg->dst_queue);
  610. header.extension |= IPC_SRC_QUEUE(msg->src_queue);
  611. dev_dbg(ipc->dev, "In %s hdr=%x ext=%x\n", __func__, header.primary,
  612. header.extension);
  613. ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
  614. if (ret < 0) {
  615. dev_err(ipc->dev, "ipc: bind/unbind failed\n");
  616. return ret;
  617. }
  618. return ret;
  619. }
  620. EXPORT_SYMBOL_GPL(skl_ipc_bind_unbind);
  621. /*
  622. * In order to load a module we need to send IPC to initiate that. DMA will
  623. * performed to load the module memory. The FW supports multiple module load
  624. * at single shot, so we can send IPC with N modules represented by
  625. * module_cnt
  626. */
  627. int skl_ipc_load_modules(struct sst_generic_ipc *ipc,
  628. u8 module_cnt, void *data)
  629. {
  630. struct skl_ipc_header header = {0};
  631. u64 *ipc_header = (u64 *)(&header);
  632. int ret;
  633. header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
  634. header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
  635. header.primary |= IPC_GLB_TYPE(IPC_GLB_LOAD_MULTIPLE_MODS);
  636. header.primary |= IPC_LOAD_MODULE_CNT(module_cnt);
  637. ret = sst_ipc_tx_message_wait(ipc, *ipc_header, data,
  638. (sizeof(u16) * module_cnt), NULL, 0);
  639. if (ret < 0)
  640. dev_err(ipc->dev, "ipc: load modules failed :%d\n", ret);
  641. return ret;
  642. }
  643. EXPORT_SYMBOL_GPL(skl_ipc_load_modules);
  644. int skl_ipc_unload_modules(struct sst_generic_ipc *ipc, u8 module_cnt,
  645. void *data)
  646. {
  647. struct skl_ipc_header header = {0};
  648. u64 *ipc_header = (u64 *)(&header);
  649. int ret;
  650. header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
  651. header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
  652. header.primary |= IPC_GLB_TYPE(IPC_GLB_UNLOAD_MULTIPLE_MODS);
  653. header.primary |= IPC_LOAD_MODULE_CNT(module_cnt);
  654. ret = sst_ipc_tx_message_wait(ipc, *ipc_header, data,
  655. (sizeof(u16) * module_cnt), NULL, 0);
  656. if (ret < 0)
  657. dev_err(ipc->dev, "ipc: unload modules failed :%d\n", ret);
  658. return ret;
  659. }
  660. EXPORT_SYMBOL_GPL(skl_ipc_unload_modules);
  661. int skl_ipc_set_large_config(struct sst_generic_ipc *ipc,
  662. struct skl_ipc_large_config_msg *msg, u32 *param)
  663. {
  664. struct skl_ipc_header header = {0};
  665. u64 *ipc_header = (u64 *)(&header);
  666. int ret = 0;
  667. size_t sz_remaining, tx_size, data_offset;
  668. header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
  669. header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
  670. header.primary |= IPC_GLB_TYPE(IPC_MOD_LARGE_CONFIG_SET);
  671. header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
  672. header.primary |= IPC_MOD_ID(msg->module_id);
  673. header.extension = IPC_DATA_OFFSET_SZ(msg->param_data_size);
  674. header.extension |= IPC_LARGE_PARAM_ID(msg->large_param_id);
  675. header.extension |= IPC_FINAL_BLOCK(0);
  676. header.extension |= IPC_INITIAL_BLOCK(1);
  677. sz_remaining = msg->param_data_size;
  678. data_offset = 0;
  679. while (sz_remaining != 0) {
  680. tx_size = sz_remaining > SKL_ADSP_W1_SZ
  681. ? SKL_ADSP_W1_SZ : sz_remaining;
  682. if (tx_size == sz_remaining)
  683. header.extension |= IPC_FINAL_BLOCK(1);
  684. dev_dbg(ipc->dev, "In %s primary=%#x ext=%#x\n", __func__,
  685. header.primary, header.extension);
  686. dev_dbg(ipc->dev, "transmitting offset: %#x, size: %#x\n",
  687. (unsigned)data_offset, (unsigned)tx_size);
  688. ret = sst_ipc_tx_message_wait(ipc, *ipc_header,
  689. ((char *)param) + data_offset,
  690. tx_size, NULL, 0);
  691. if (ret < 0) {
  692. dev_err(ipc->dev,
  693. "ipc: set large config fail, err: %d\n", ret);
  694. return ret;
  695. }
  696. sz_remaining -= tx_size;
  697. data_offset = msg->param_data_size - sz_remaining;
  698. /* clear the fields */
  699. header.extension &= IPC_INITIAL_BLOCK_CLEAR;
  700. header.extension &= IPC_DATA_OFFSET_SZ_CLEAR;
  701. /* fill the fields */
  702. header.extension |= IPC_INITIAL_BLOCK(0);
  703. header.extension |= IPC_DATA_OFFSET_SZ(data_offset);
  704. }
  705. return ret;
  706. }
  707. EXPORT_SYMBOL_GPL(skl_ipc_set_large_config);
  708. int skl_ipc_get_large_config(struct sst_generic_ipc *ipc,
  709. struct skl_ipc_large_config_msg *msg, u32 *param)
  710. {
  711. struct skl_ipc_header header = {0};
  712. u64 *ipc_header = (u64 *)(&header);
  713. int ret = 0;
  714. size_t sz_remaining, rx_size, data_offset;
  715. header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
  716. header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
  717. header.primary |= IPC_GLB_TYPE(IPC_MOD_LARGE_CONFIG_GET);
  718. header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
  719. header.primary |= IPC_MOD_ID(msg->module_id);
  720. header.extension = IPC_DATA_OFFSET_SZ(msg->param_data_size);
  721. header.extension |= IPC_LARGE_PARAM_ID(msg->large_param_id);
  722. header.extension |= IPC_FINAL_BLOCK(1);
  723. header.extension |= IPC_INITIAL_BLOCK(1);
  724. sz_remaining = msg->param_data_size;
  725. data_offset = 0;
  726. while (sz_remaining != 0) {
  727. rx_size = sz_remaining > SKL_ADSP_W1_SZ
  728. ? SKL_ADSP_W1_SZ : sz_remaining;
  729. if (rx_size == sz_remaining)
  730. header.extension |= IPC_FINAL_BLOCK(1);
  731. ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0,
  732. ((char *)param) + data_offset,
  733. msg->param_data_size);
  734. if (ret < 0) {
  735. dev_err(ipc->dev,
  736. "ipc: get large config fail, err: %d\n", ret);
  737. return ret;
  738. }
  739. sz_remaining -= rx_size;
  740. data_offset = msg->param_data_size - sz_remaining;
  741. /* clear the fields */
  742. header.extension &= IPC_INITIAL_BLOCK_CLEAR;
  743. header.extension &= IPC_DATA_OFFSET_SZ_CLEAR;
  744. /* fill the fields */
  745. header.extension |= IPC_INITIAL_BLOCK(1);
  746. header.extension |= IPC_DATA_OFFSET_SZ(data_offset);
  747. }
  748. return ret;
  749. }
  750. EXPORT_SYMBOL_GPL(skl_ipc_get_large_config);
  751. int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc,
  752. u8 dma_id, u8 table_id)
  753. {
  754. struct skl_ipc_header header = {0};
  755. u64 *ipc_header = (u64 *)(&header);
  756. int ret = 0;
  757. header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
  758. header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
  759. header.primary |= IPC_GLB_TYPE(IPC_GLB_LOAD_LIBRARY);
  760. header.primary |= IPC_MOD_INSTANCE_ID(table_id);
  761. header.primary |= IPC_MOD_ID(dma_id);
  762. ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
  763. if (ret < 0)
  764. dev_err(ipc->dev, "ipc: load lib failed\n");
  765. return ret;
  766. }
  767. EXPORT_SYMBOL_GPL(skl_sst_ipc_load_library);