max9860.c 19 KB

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  1. /*
  2. * Driver for the MAX9860 Mono Audio Voice Codec
  3. *
  4. * https://datasheets.maximintegrated.com/en/ds/MAX9860.pdf
  5. *
  6. * The driver does not support sidetone since the DVST register field is
  7. * backwards with the mute near the maximum level instead of the minimum.
  8. *
  9. * Author: Peter Rosin <peda@axentia.s>
  10. * Copyright 2016 Axentia Technologies
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License
  14. * version 2 as published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/clk.h>
  24. #include <linux/kernel.h>
  25. #include <linux/pm_runtime.h>
  26. #include <linux/regmap.h>
  27. #include <linux/i2c.h>
  28. #include <linux/regulator/consumer.h>
  29. #include <sound/soc.h>
  30. #include <sound/soc-dapm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/tlv.h>
  33. #include "max9860.h"
  34. struct max9860_priv {
  35. struct regmap *regmap;
  36. struct regulator *dvddio;
  37. struct notifier_block dvddio_nb;
  38. u8 psclk;
  39. unsigned long pclk_rate;
  40. int fmt;
  41. };
  42. static int max9860_dvddio_event(struct notifier_block *nb,
  43. unsigned long event, void *data)
  44. {
  45. struct max9860_priv *max9860 = container_of(nb, struct max9860_priv,
  46. dvddio_nb);
  47. if (event & REGULATOR_EVENT_DISABLE) {
  48. regcache_mark_dirty(max9860->regmap);
  49. regcache_cache_only(max9860->regmap, true);
  50. }
  51. return 0;
  52. }
  53. static const struct reg_default max9860_reg_defaults[] = {
  54. { MAX9860_PWRMAN, 0x00 },
  55. { MAX9860_INTEN, 0x00 },
  56. { MAX9860_SYSCLK, 0x00 },
  57. { MAX9860_AUDIOCLKHIGH, 0x00 },
  58. { MAX9860_AUDIOCLKLOW, 0x00 },
  59. { MAX9860_IFC1A, 0x00 },
  60. { MAX9860_IFC1B, 0x00 },
  61. { MAX9860_VOICEFLTR, 0x00 },
  62. { MAX9860_DACATTN, 0x00 },
  63. { MAX9860_ADCLEVEL, 0x00 },
  64. { MAX9860_DACGAIN, 0x00 },
  65. { MAX9860_MICGAIN, 0x00 },
  66. { MAX9860_MICADC, 0x00 },
  67. { MAX9860_NOISEGATE, 0x00 },
  68. };
  69. static bool max9860_readable(struct device *dev, unsigned int reg)
  70. {
  71. switch (reg) {
  72. case MAX9860_INTRSTATUS ... MAX9860_MICGAIN:
  73. case MAX9860_MICADC ... MAX9860_PWRMAN:
  74. case MAX9860_REVISION:
  75. return true;
  76. }
  77. return false;
  78. }
  79. static bool max9860_writeable(struct device *dev, unsigned int reg)
  80. {
  81. switch (reg) {
  82. case MAX9860_INTEN ... MAX9860_MICGAIN:
  83. case MAX9860_MICADC ... MAX9860_PWRMAN:
  84. return true;
  85. }
  86. return false;
  87. }
  88. static bool max9860_volatile(struct device *dev, unsigned int reg)
  89. {
  90. switch (reg) {
  91. case MAX9860_INTRSTATUS:
  92. case MAX9860_MICREADBACK:
  93. return true;
  94. }
  95. return false;
  96. }
  97. static bool max9860_precious(struct device *dev, unsigned int reg)
  98. {
  99. switch (reg) {
  100. case MAX9860_INTRSTATUS:
  101. return true;
  102. }
  103. return false;
  104. }
  105. static const struct regmap_config max9860_regmap = {
  106. .reg_bits = 8,
  107. .val_bits = 8,
  108. .readable_reg = max9860_readable,
  109. .writeable_reg = max9860_writeable,
  110. .volatile_reg = max9860_volatile,
  111. .precious_reg = max9860_precious,
  112. .max_register = MAX9860_MAX_REGISTER,
  113. .reg_defaults = max9860_reg_defaults,
  114. .num_reg_defaults = ARRAY_SIZE(max9860_reg_defaults),
  115. .cache_type = REGCACHE_RBTREE,
  116. };
  117. static const DECLARE_TLV_DB_SCALE(dva_tlv, -9100, 100, 1);
  118. static const DECLARE_TLV_DB_SCALE(dvg_tlv, 0, 600, 0);
  119. static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
  120. static const DECLARE_TLV_DB_RANGE(pam_tlv,
  121. 0, MAX9860_PAM_MAX - 1, TLV_DB_SCALE_ITEM(-2000, 2000, 1),
  122. MAX9860_PAM_MAX, MAX9860_PAM_MAX, TLV_DB_SCALE_ITEM(3000, 0, 0));
  123. static const DECLARE_TLV_DB_SCALE(pgam_tlv, 0, 100, 0);
  124. static const DECLARE_TLV_DB_SCALE(anth_tlv, -7600, 400, 1);
  125. static const DECLARE_TLV_DB_SCALE(agcth_tlv, -1800, 100, 0);
  126. static const char * const agchld_text[] = {
  127. "AGC Disabled", "50ms", "100ms", "400ms"
  128. };
  129. static SOC_ENUM_SINGLE_DECL(agchld_enum, MAX9860_MICADC,
  130. MAX9860_AGCHLD_SHIFT, agchld_text);
  131. static const char * const agcsrc_text[] = {
  132. "Left ADC", "Left/Right ADC"
  133. };
  134. static SOC_ENUM_SINGLE_DECL(agcsrc_enum, MAX9860_MICADC,
  135. MAX9860_AGCSRC_SHIFT, agcsrc_text);
  136. static const char * const agcatk_text[] = {
  137. "3ms", "12ms", "50ms", "200ms"
  138. };
  139. static SOC_ENUM_SINGLE_DECL(agcatk_enum, MAX9860_MICADC,
  140. MAX9860_AGCATK_SHIFT, agcatk_text);
  141. static const char * const agcrls_text[] = {
  142. "78ms", "156ms", "312ms", "625ms",
  143. "1.25s", "2.5s", "5s", "10s"
  144. };
  145. static SOC_ENUM_SINGLE_DECL(agcrls_enum, MAX9860_MICADC,
  146. MAX9860_AGCRLS_SHIFT, agcrls_text);
  147. static const char * const filter_text[] = {
  148. "Disabled",
  149. "Elliptical HP 217Hz notch (16kHz)",
  150. "Butterworth HP 500Hz (16kHz)",
  151. "Elliptical HP 217Hz notch (8kHz)",
  152. "Butterworth HP 500Hz (8kHz)",
  153. "Butterworth HP 200Hz (48kHz)"
  154. };
  155. static SOC_ENUM_SINGLE_DECL(avflt_enum, MAX9860_VOICEFLTR,
  156. MAX9860_AVFLT_SHIFT, filter_text);
  157. static SOC_ENUM_SINGLE_DECL(dvflt_enum, MAX9860_VOICEFLTR,
  158. MAX9860_DVFLT_SHIFT, filter_text);
  159. static const struct snd_kcontrol_new max9860_controls[] = {
  160. SOC_SINGLE_TLV("Master Playback Volume", MAX9860_DACATTN,
  161. MAX9860_DVA_SHIFT, MAX9860_DVA_MUTE, 1, dva_tlv),
  162. SOC_SINGLE_TLV("DAC Gain Volume", MAX9860_DACGAIN,
  163. MAX9860_DVG_SHIFT, MAX9860_DVG_MAX, 0, dvg_tlv),
  164. SOC_DOUBLE_TLV("Line Capture Volume", MAX9860_ADCLEVEL,
  165. MAX9860_ADCLL_SHIFT, MAX9860_ADCRL_SHIFT, MAX9860_ADCxL_MIN, 1,
  166. adc_tlv),
  167. SOC_ENUM("AGC Hold Time", agchld_enum),
  168. SOC_ENUM("AGC/Noise Gate Source", agcsrc_enum),
  169. SOC_ENUM("AGC Attack Time", agcatk_enum),
  170. SOC_ENUM("AGC Release Time", agcrls_enum),
  171. SOC_SINGLE_TLV("Noise Gate Threshold Volume", MAX9860_NOISEGATE,
  172. MAX9860_ANTH_SHIFT, MAX9860_ANTH_MAX, 0, anth_tlv),
  173. SOC_SINGLE_TLV("AGC Signal Threshold Volume", MAX9860_NOISEGATE,
  174. MAX9860_AGCTH_SHIFT, MAX9860_AGCTH_MIN, 1, agcth_tlv),
  175. SOC_SINGLE_TLV("Mic PGA Volume", MAX9860_MICGAIN,
  176. MAX9860_PGAM_SHIFT, MAX9860_PGAM_MIN, 1, pgam_tlv),
  177. SOC_SINGLE_TLV("Mic Preamp Volume", MAX9860_MICGAIN,
  178. MAX9860_PAM_SHIFT, MAX9860_PAM_MAX, 0, pam_tlv),
  179. SOC_ENUM("ADC Filter", avflt_enum),
  180. SOC_ENUM("DAC Filter", dvflt_enum),
  181. };
  182. static const struct snd_soc_dapm_widget max9860_dapm_widgets[] = {
  183. SND_SOC_DAPM_INPUT("MICL"),
  184. SND_SOC_DAPM_INPUT("MICR"),
  185. SND_SOC_DAPM_ADC("ADCL", NULL, MAX9860_PWRMAN, MAX9860_ADCLEN_SHIFT, 0),
  186. SND_SOC_DAPM_ADC("ADCR", NULL, MAX9860_PWRMAN, MAX9860_ADCREN_SHIFT, 0),
  187. SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
  188. SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
  189. SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
  190. SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
  191. SND_SOC_DAPM_DAC("DAC", NULL, MAX9860_PWRMAN, MAX9860_DACEN_SHIFT, 0),
  192. SND_SOC_DAPM_OUTPUT("OUT"),
  193. SND_SOC_DAPM_SUPPLY("Supply", SND_SOC_NOPM, 0, 0,
  194. NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  195. SND_SOC_DAPM_REGULATOR_SUPPLY("AVDD", 0, 0),
  196. SND_SOC_DAPM_REGULATOR_SUPPLY("DVDD", 0, 0),
  197. SND_SOC_DAPM_CLOCK_SUPPLY("mclk"),
  198. };
  199. static const struct snd_soc_dapm_route max9860_dapm_routes[] = {
  200. { "ADCL", NULL, "MICL" },
  201. { "ADCR", NULL, "MICR" },
  202. { "AIFOUTL", NULL, "ADCL" },
  203. { "AIFOUTR", NULL, "ADCR" },
  204. { "DAC", NULL, "AIFINL" },
  205. { "DAC", NULL, "AIFINR" },
  206. { "OUT", NULL, "DAC" },
  207. { "Supply", NULL, "AVDD" },
  208. { "Supply", NULL, "DVDD" },
  209. { "Supply", NULL, "mclk" },
  210. { "DAC", NULL, "Supply" },
  211. { "ADCL", NULL, "Supply" },
  212. { "ADCR", NULL, "Supply" },
  213. };
  214. static int max9860_hw_params(struct snd_pcm_substream *substream,
  215. struct snd_pcm_hw_params *params,
  216. struct snd_soc_dai *dai)
  217. {
  218. struct snd_soc_codec *codec = dai->codec;
  219. struct max9860_priv *max9860 = snd_soc_codec_get_drvdata(codec);
  220. u8 master;
  221. u8 ifc1a = 0;
  222. u8 ifc1b = 0;
  223. u8 sysclk = 0;
  224. unsigned long n;
  225. int ret;
  226. dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n",
  227. params_rate(params),
  228. params_channels(params));
  229. if (params_channels(params) == 2)
  230. ifc1b |= MAX9860_ST;
  231. switch (max9860->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  232. case SND_SOC_DAIFMT_CBS_CFS:
  233. master = 0;
  234. break;
  235. case SND_SOC_DAIFMT_CBM_CFM:
  236. master = MAX9860_MASTER;
  237. break;
  238. default:
  239. return -EINVAL;
  240. }
  241. ifc1a |= master;
  242. if (master) {
  243. if (params_width(params) * params_channels(params) > 48)
  244. ifc1b |= MAX9860_BSEL_64X;
  245. else
  246. ifc1b |= MAX9860_BSEL_48X;
  247. }
  248. switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  249. case SND_SOC_DAIFMT_I2S:
  250. ifc1a |= MAX9860_DDLY;
  251. ifc1b |= MAX9860_ADLY;
  252. break;
  253. case SND_SOC_DAIFMT_LEFT_J:
  254. ifc1a |= MAX9860_WCI;
  255. break;
  256. case SND_SOC_DAIFMT_DSP_A:
  257. if (params_width(params) != 16) {
  258. dev_err(codec->dev,
  259. "DSP_A works for 16 bits per sample only.\n");
  260. return -EINVAL;
  261. }
  262. ifc1a |= MAX9860_DDLY | MAX9860_WCI | MAX9860_HIZ | MAX9860_TDM;
  263. ifc1b |= MAX9860_ADLY;
  264. break;
  265. case SND_SOC_DAIFMT_DSP_B:
  266. if (params_width(params) != 16) {
  267. dev_err(codec->dev,
  268. "DSP_B works for 16 bits per sample only.\n");
  269. return -EINVAL;
  270. }
  271. ifc1a |= MAX9860_WCI | MAX9860_HIZ | MAX9860_TDM;
  272. break;
  273. default:
  274. return -EINVAL;
  275. }
  276. switch (max9860->fmt & SND_SOC_DAIFMT_INV_MASK) {
  277. case SND_SOC_DAIFMT_NB_NF:
  278. break;
  279. case SND_SOC_DAIFMT_NB_IF:
  280. switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  281. case SND_SOC_DAIFMT_DSP_A:
  282. case SND_SOC_DAIFMT_DSP_B:
  283. return -EINVAL;
  284. }
  285. ifc1a ^= MAX9860_WCI;
  286. break;
  287. case SND_SOC_DAIFMT_IB_IF:
  288. switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  289. case SND_SOC_DAIFMT_DSP_A:
  290. case SND_SOC_DAIFMT_DSP_B:
  291. return -EINVAL;
  292. }
  293. ifc1a ^= MAX9860_WCI;
  294. /* fall through */
  295. case SND_SOC_DAIFMT_IB_NF:
  296. ifc1a ^= MAX9860_DBCI;
  297. ifc1b ^= MAX9860_ABCI;
  298. break;
  299. default:
  300. return -EINVAL;
  301. }
  302. dev_dbg(codec->dev, "IFC1A %02x\n", ifc1a);
  303. ret = regmap_write(max9860->regmap, MAX9860_IFC1A, ifc1a);
  304. if (ret) {
  305. dev_err(codec->dev, "Failed to set IFC1A: %d\n", ret);
  306. return ret;
  307. }
  308. dev_dbg(codec->dev, "IFC1B %02x\n", ifc1b);
  309. ret = regmap_write(max9860->regmap, MAX9860_IFC1B, ifc1b);
  310. if (ret) {
  311. dev_err(codec->dev, "Failed to set IFC1B: %d\n", ret);
  312. return ret;
  313. }
  314. /*
  315. * Check if Integer Clock Mode is possible, but avoid it in slave mode
  316. * since we then do not know if lrclk is derived from pclk and the
  317. * datasheet mentions that the frequencies have to match exactly in
  318. * order for this to work.
  319. */
  320. if (params_rate(params) == 8000 || params_rate(params) == 16000) {
  321. if (master) {
  322. switch (max9860->pclk_rate) {
  323. case 12000000:
  324. sysclk = MAX9860_FREQ_12MHZ;
  325. break;
  326. case 13000000:
  327. sysclk = MAX9860_FREQ_13MHZ;
  328. break;
  329. case 19200000:
  330. sysclk = MAX9860_FREQ_19_2MHZ;
  331. break;
  332. default:
  333. /*
  334. * Integer Clock Mode not possible. Leave
  335. * sysclk at zero and fall through to the
  336. * code below for PLL mode.
  337. */
  338. break;
  339. }
  340. if (sysclk && params_rate(params) == 16000)
  341. sysclk |= MAX9860_16KHZ;
  342. }
  343. }
  344. /*
  345. * Largest possible n:
  346. * 65536 * 96 * 48kHz / 10MHz -> 30199
  347. * Smallest possible n:
  348. * 65536 * 96 * 8kHz / 20MHz -> 2517
  349. * Both fit nicely in the available 15 bits, no need to apply any mask.
  350. */
  351. n = DIV_ROUND_CLOSEST_ULL(65536ULL * 96 * params_rate(params),
  352. max9860->pclk_rate);
  353. if (!sysclk) {
  354. /* PLL mode */
  355. if (params_rate(params) > 24000)
  356. sysclk |= MAX9860_16KHZ;
  357. if (!master)
  358. n |= 1; /* trigger rapid pll lock mode */
  359. }
  360. sysclk |= max9860->psclk;
  361. dev_dbg(codec->dev, "SYSCLK %02x\n", sysclk);
  362. ret = regmap_write(max9860->regmap,
  363. MAX9860_SYSCLK, sysclk);
  364. if (ret) {
  365. dev_err(codec->dev, "Failed to set SYSCLK: %d\n", ret);
  366. return ret;
  367. }
  368. dev_dbg(codec->dev, "N %lu\n", n);
  369. ret = regmap_write(max9860->regmap,
  370. MAX9860_AUDIOCLKHIGH, n >> 8);
  371. if (ret) {
  372. dev_err(codec->dev, "Failed to set NHI: %d\n", ret);
  373. return ret;
  374. }
  375. ret = regmap_write(max9860->regmap,
  376. MAX9860_AUDIOCLKLOW, n & 0xff);
  377. if (ret) {
  378. dev_err(codec->dev, "Failed to set NLO: %d\n", ret);
  379. return ret;
  380. }
  381. if (!master) {
  382. dev_dbg(codec->dev, "Enable PLL\n");
  383. ret = regmap_update_bits(max9860->regmap, MAX9860_AUDIOCLKHIGH,
  384. MAX9860_PLL, MAX9860_PLL);
  385. if (ret) {
  386. dev_err(codec->dev, "Failed to enable PLL: %d\n", ret);
  387. return ret;
  388. }
  389. }
  390. return 0;
  391. }
  392. static int max9860_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  393. {
  394. struct snd_soc_codec *codec = dai->codec;
  395. struct max9860_priv *max9860 = snd_soc_codec_get_drvdata(codec);
  396. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  397. case SND_SOC_DAIFMT_CBM_CFM:
  398. case SND_SOC_DAIFMT_CBS_CFS:
  399. max9860->fmt = fmt;
  400. return 0;
  401. default:
  402. return -EINVAL;
  403. }
  404. }
  405. static const struct snd_soc_dai_ops max9860_dai_ops = {
  406. .hw_params = max9860_hw_params,
  407. .set_fmt = max9860_set_fmt,
  408. };
  409. static struct snd_soc_dai_driver max9860_dai = {
  410. .name = "max9860-hifi",
  411. .playback = {
  412. .stream_name = "Playback",
  413. .channels_min = 1,
  414. .channels_max = 2,
  415. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  416. .rate_min = 8000,
  417. .rate_max = 48000,
  418. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  419. SNDRV_PCM_FMTBIT_S24_LE |
  420. SNDRV_PCM_FMTBIT_S32_LE,
  421. },
  422. .capture = {
  423. .stream_name = "Capture",
  424. .channels_min = 1,
  425. .channels_max = 2,
  426. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  427. .rate_min = 8000,
  428. .rate_max = 48000,
  429. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  430. SNDRV_PCM_FMTBIT_S24_LE |
  431. SNDRV_PCM_FMTBIT_S32_LE,
  432. },
  433. .ops = &max9860_dai_ops,
  434. .symmetric_rates = 1,
  435. };
  436. static int max9860_set_bias_level(struct snd_soc_codec *codec,
  437. enum snd_soc_bias_level level)
  438. {
  439. struct max9860_priv *max9860 = dev_get_drvdata(codec->dev);
  440. int ret;
  441. switch (level) {
  442. case SND_SOC_BIAS_ON:
  443. case SND_SOC_BIAS_PREPARE:
  444. break;
  445. case SND_SOC_BIAS_STANDBY:
  446. ret = regmap_update_bits(max9860->regmap, MAX9860_PWRMAN,
  447. MAX9860_SHDN, MAX9860_SHDN);
  448. if (ret) {
  449. dev_err(codec->dev, "Failed to remove SHDN: %d\n", ret);
  450. return ret;
  451. }
  452. break;
  453. case SND_SOC_BIAS_OFF:
  454. ret = regmap_update_bits(max9860->regmap, MAX9860_PWRMAN,
  455. MAX9860_SHDN, 0);
  456. if (ret) {
  457. dev_err(codec->dev, "Failed to request SHDN: %d\n",
  458. ret);
  459. return ret;
  460. }
  461. break;
  462. }
  463. return 0;
  464. }
  465. static struct snd_soc_codec_driver max9860_codec_driver = {
  466. .set_bias_level = max9860_set_bias_level,
  467. .idle_bias_off = true,
  468. .component_driver = {
  469. .controls = max9860_controls,
  470. .num_controls = ARRAY_SIZE(max9860_controls),
  471. .dapm_widgets = max9860_dapm_widgets,
  472. .num_dapm_widgets = ARRAY_SIZE(max9860_dapm_widgets),
  473. .dapm_routes = max9860_dapm_routes,
  474. .num_dapm_routes = ARRAY_SIZE(max9860_dapm_routes),
  475. },
  476. };
  477. #ifdef CONFIG_PM
  478. static int max9860_suspend(struct device *dev)
  479. {
  480. struct max9860_priv *max9860 = dev_get_drvdata(dev);
  481. int ret;
  482. ret = regmap_update_bits(max9860->regmap, MAX9860_SYSCLK,
  483. MAX9860_PSCLK, MAX9860_PSCLK_OFF);
  484. if (ret) {
  485. dev_err(dev, "Failed to disable clock: %d\n", ret);
  486. return ret;
  487. }
  488. regulator_disable(max9860->dvddio);
  489. return 0;
  490. }
  491. static int max9860_resume(struct device *dev)
  492. {
  493. struct max9860_priv *max9860 = dev_get_drvdata(dev);
  494. int ret;
  495. ret = regulator_enable(max9860->dvddio);
  496. if (ret) {
  497. dev_err(dev, "Failed to enable DVDDIO: %d\n", ret);
  498. return ret;
  499. }
  500. regcache_cache_only(max9860->regmap, false);
  501. ret = regcache_sync(max9860->regmap);
  502. if (ret) {
  503. dev_err(dev, "Failed to sync cache: %d\n", ret);
  504. return ret;
  505. }
  506. ret = regmap_update_bits(max9860->regmap, MAX9860_SYSCLK,
  507. MAX9860_PSCLK, max9860->psclk);
  508. if (ret) {
  509. dev_err(dev, "Failed to enable clock: %d\n", ret);
  510. return ret;
  511. }
  512. return 0;
  513. }
  514. #endif
  515. static const struct dev_pm_ops max9860_pm_ops = {
  516. SET_RUNTIME_PM_OPS(max9860_suspend, max9860_resume, NULL)
  517. };
  518. static int max9860_probe(struct i2c_client *i2c,
  519. const struct i2c_device_id *id)
  520. {
  521. struct device *dev = &i2c->dev;
  522. struct max9860_priv *max9860;
  523. int ret;
  524. struct clk *mclk;
  525. unsigned long mclk_rate;
  526. int i;
  527. int intr;
  528. max9860 = devm_kzalloc(dev, sizeof(struct max9860_priv), GFP_KERNEL);
  529. if (!max9860)
  530. return -ENOMEM;
  531. max9860->dvddio = devm_regulator_get(dev, "DVDDIO");
  532. if (IS_ERR(max9860->dvddio)) {
  533. ret = PTR_ERR(max9860->dvddio);
  534. if (ret != -EPROBE_DEFER)
  535. dev_err(dev, "Failed to get DVDDIO supply: %d\n", ret);
  536. return ret;
  537. }
  538. max9860->dvddio_nb.notifier_call = max9860_dvddio_event;
  539. ret = regulator_register_notifier(max9860->dvddio, &max9860->dvddio_nb);
  540. if (ret)
  541. dev_err(dev, "Failed to register DVDDIO notifier: %d\n", ret);
  542. ret = regulator_enable(max9860->dvddio);
  543. if (ret != 0) {
  544. dev_err(dev, "Failed to enable DVDDIO: %d\n", ret);
  545. return ret;
  546. }
  547. max9860->regmap = devm_regmap_init_i2c(i2c, &max9860_regmap);
  548. if (IS_ERR(max9860->regmap)) {
  549. ret = PTR_ERR(max9860->regmap);
  550. goto err_regulator;
  551. }
  552. dev_set_drvdata(dev, max9860);
  553. /*
  554. * mclk has to be in the 10MHz to 60MHz range.
  555. * psclk is used to scale mclk into pclk so that
  556. * pclk is in the 10MHz to 20MHz range.
  557. */
  558. mclk = clk_get(dev, "mclk");
  559. if (IS_ERR(mclk)) {
  560. ret = PTR_ERR(mclk);
  561. if (ret != -EPROBE_DEFER)
  562. dev_err(dev, "Failed to get MCLK: %d\n", ret);
  563. goto err_regulator;
  564. }
  565. mclk_rate = clk_get_rate(mclk);
  566. clk_put(mclk);
  567. if (mclk_rate > 60000000 || mclk_rate < 10000000) {
  568. dev_err(dev, "Bad mclk %luHz (needs 10MHz - 60MHz)\n",
  569. mclk_rate);
  570. ret = -EINVAL;
  571. goto err_regulator;
  572. }
  573. if (mclk_rate >= 40000000)
  574. max9860->psclk = 3;
  575. else if (mclk_rate >= 20000000)
  576. max9860->psclk = 2;
  577. else
  578. max9860->psclk = 1;
  579. max9860->pclk_rate = mclk_rate >> (max9860->psclk - 1);
  580. max9860->psclk <<= MAX9860_PSCLK_SHIFT;
  581. dev_dbg(dev, "mclk %lu pclk %lu\n", mclk_rate, max9860->pclk_rate);
  582. regcache_cache_bypass(max9860->regmap, true);
  583. for (i = 0; i < max9860_regmap.num_reg_defaults; ++i) {
  584. ret = regmap_write(max9860->regmap,
  585. max9860_regmap.reg_defaults[i].reg,
  586. max9860_regmap.reg_defaults[i].def);
  587. if (ret) {
  588. dev_err(dev, "Failed to initialize register %u: %d\n",
  589. max9860_regmap.reg_defaults[i].reg, ret);
  590. goto err_regulator;
  591. }
  592. }
  593. regcache_cache_bypass(max9860->regmap, false);
  594. ret = regmap_read(max9860->regmap, MAX9860_INTRSTATUS, &intr);
  595. if (ret) {
  596. dev_err(dev, "Failed to clear INTRSTATUS: %d\n", ret);
  597. goto err_regulator;
  598. }
  599. pm_runtime_set_active(dev);
  600. pm_runtime_enable(dev);
  601. pm_runtime_idle(dev);
  602. ret = snd_soc_register_codec(dev, &max9860_codec_driver,
  603. &max9860_dai, 1);
  604. if (ret) {
  605. dev_err(dev, "Failed to register CODEC: %d\n", ret);
  606. goto err_pm;
  607. }
  608. return 0;
  609. err_pm:
  610. pm_runtime_disable(dev);
  611. err_regulator:
  612. regulator_disable(max9860->dvddio);
  613. return ret;
  614. }
  615. static int max9860_remove(struct i2c_client *i2c)
  616. {
  617. struct device *dev = &i2c->dev;
  618. struct max9860_priv *max9860 = dev_get_drvdata(dev);
  619. snd_soc_unregister_codec(dev);
  620. pm_runtime_disable(dev);
  621. regulator_disable(max9860->dvddio);
  622. return 0;
  623. }
  624. static const struct i2c_device_id max9860_i2c_id[] = {
  625. { "max9860", },
  626. { }
  627. };
  628. MODULE_DEVICE_TABLE(i2c, max9860_i2c_id);
  629. static const struct of_device_id max9860_of_match[] = {
  630. { .compatible = "maxim,max9860", },
  631. { }
  632. };
  633. MODULE_DEVICE_TABLE(of, max9860_of_match);
  634. static struct i2c_driver max9860_i2c_driver = {
  635. .probe = max9860_probe,
  636. .remove = max9860_remove,
  637. .id_table = max9860_i2c_id,
  638. .driver = {
  639. .name = "max9860",
  640. .of_match_table = max9860_of_match,
  641. .pm = &max9860_pm_ops,
  642. },
  643. };
  644. module_i2c_driver(max9860_i2c_driver);
  645. MODULE_DESCRIPTION("ASoC MAX9860 Mono Audio Voice Codec driver");
  646. MODULE_AUTHOR("Peter Rosin <peda@axentia.se>");
  647. MODULE_LICENSE("GPL v2");