intel_soc_dts_iosf.c 12 KB

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  1. /*
  2. * intel_soc_dts_iosf.c
  3. * Copyright (c) 2015, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. */
  15. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  16. #include <linux/module.h>
  17. #include <linux/slab.h>
  18. #include <linux/interrupt.h>
  19. #include <asm/iosf_mbi.h>
  20. #include "intel_soc_dts_iosf.h"
  21. #define SOC_DTS_OFFSET_ENABLE 0xB0
  22. #define SOC_DTS_OFFSET_TEMP 0xB1
  23. #define SOC_DTS_OFFSET_PTPS 0xB2
  24. #define SOC_DTS_OFFSET_PTTS 0xB3
  25. #define SOC_DTS_OFFSET_PTTSS 0xB4
  26. #define SOC_DTS_OFFSET_PTMC 0x80
  27. #define SOC_DTS_TE_AUX0 0xB5
  28. #define SOC_DTS_TE_AUX1 0xB6
  29. #define SOC_DTS_AUX0_ENABLE_BIT BIT(0)
  30. #define SOC_DTS_AUX1_ENABLE_BIT BIT(1)
  31. #define SOC_DTS_CPU_MODULE0_ENABLE_BIT BIT(16)
  32. #define SOC_DTS_CPU_MODULE1_ENABLE_BIT BIT(17)
  33. #define SOC_DTS_TE_SCI_ENABLE BIT(9)
  34. #define SOC_DTS_TE_SMI_ENABLE BIT(10)
  35. #define SOC_DTS_TE_MSI_ENABLE BIT(11)
  36. #define SOC_DTS_TE_APICA_ENABLE BIT(14)
  37. #define SOC_DTS_PTMC_APIC_DEASSERT_BIT BIT(4)
  38. /* DTS encoding for TJ MAX temperature */
  39. #define SOC_DTS_TJMAX_ENCODING 0x7F
  40. /* Only 2 out of 4 is allowed for OSPM */
  41. #define SOC_MAX_DTS_TRIPS 2
  42. /* Mask for two trips in status bits */
  43. #define SOC_DTS_TRIP_MASK 0x03
  44. /* DTS0 and DTS 1 */
  45. #define SOC_MAX_DTS_SENSORS 2
  46. static int get_tj_max(u32 *tj_max)
  47. {
  48. u32 eax, edx;
  49. u32 val;
  50. int err;
  51. err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
  52. if (err)
  53. goto err_ret;
  54. else {
  55. val = (eax >> 16) & 0xff;
  56. if (val)
  57. *tj_max = val * 1000;
  58. else {
  59. err = -EINVAL;
  60. goto err_ret;
  61. }
  62. }
  63. return 0;
  64. err_ret:
  65. *tj_max = 0;
  66. return err;
  67. }
  68. static int sys_get_trip_temp(struct thermal_zone_device *tzd, int trip,
  69. int *temp)
  70. {
  71. int status;
  72. u32 out;
  73. struct intel_soc_dts_sensor_entry *dts;
  74. struct intel_soc_dts_sensors *sensors;
  75. dts = tzd->devdata;
  76. sensors = dts->sensors;
  77. mutex_lock(&sensors->dts_update_lock);
  78. status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
  79. SOC_DTS_OFFSET_PTPS, &out);
  80. mutex_unlock(&sensors->dts_update_lock);
  81. if (status)
  82. return status;
  83. out = (out >> (trip * 8)) & SOC_DTS_TJMAX_ENCODING;
  84. if (!out)
  85. *temp = 0;
  86. else
  87. *temp = sensors->tj_max - out * 1000;
  88. return 0;
  89. }
  90. static int update_trip_temp(struct intel_soc_dts_sensor_entry *dts,
  91. int thres_index, int temp,
  92. enum thermal_trip_type trip_type)
  93. {
  94. int status;
  95. u32 temp_out;
  96. u32 out;
  97. u32 store_ptps;
  98. u32 store_ptmc;
  99. u32 store_te_out;
  100. u32 te_out;
  101. u32 int_enable_bit = SOC_DTS_TE_APICA_ENABLE;
  102. struct intel_soc_dts_sensors *sensors = dts->sensors;
  103. if (sensors->intr_type == INTEL_SOC_DTS_INTERRUPT_MSI)
  104. int_enable_bit |= SOC_DTS_TE_MSI_ENABLE;
  105. temp_out = (sensors->tj_max - temp) / 1000;
  106. status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
  107. SOC_DTS_OFFSET_PTPS, &store_ptps);
  108. if (status)
  109. return status;
  110. out = (store_ptps & ~(0xFF << (thres_index * 8)));
  111. out |= (temp_out & 0xFF) << (thres_index * 8);
  112. status = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
  113. SOC_DTS_OFFSET_PTPS, out);
  114. if (status)
  115. return status;
  116. pr_debug("update_trip_temp PTPS = %x\n", out);
  117. status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
  118. SOC_DTS_OFFSET_PTMC, &out);
  119. if (status)
  120. goto err_restore_ptps;
  121. store_ptmc = out;
  122. status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
  123. SOC_DTS_TE_AUX0 + thres_index,
  124. &te_out);
  125. if (status)
  126. goto err_restore_ptmc;
  127. store_te_out = te_out;
  128. /* Enable for CPU module 0 and module 1 */
  129. out |= (SOC_DTS_CPU_MODULE0_ENABLE_BIT |
  130. SOC_DTS_CPU_MODULE1_ENABLE_BIT);
  131. if (temp) {
  132. if (thres_index)
  133. out |= SOC_DTS_AUX1_ENABLE_BIT;
  134. else
  135. out |= SOC_DTS_AUX0_ENABLE_BIT;
  136. te_out |= int_enable_bit;
  137. } else {
  138. if (thres_index)
  139. out &= ~SOC_DTS_AUX1_ENABLE_BIT;
  140. else
  141. out &= ~SOC_DTS_AUX0_ENABLE_BIT;
  142. te_out &= ~int_enable_bit;
  143. }
  144. status = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
  145. SOC_DTS_OFFSET_PTMC, out);
  146. if (status)
  147. goto err_restore_te_out;
  148. status = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
  149. SOC_DTS_TE_AUX0 + thres_index,
  150. te_out);
  151. if (status)
  152. goto err_restore_te_out;
  153. dts->trip_types[thres_index] = trip_type;
  154. return 0;
  155. err_restore_te_out:
  156. iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
  157. SOC_DTS_OFFSET_PTMC, store_te_out);
  158. err_restore_ptmc:
  159. iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
  160. SOC_DTS_OFFSET_PTMC, store_ptmc);
  161. err_restore_ptps:
  162. iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
  163. SOC_DTS_OFFSET_PTPS, store_ptps);
  164. /* Nothing we can do if restore fails */
  165. return status;
  166. }
  167. static int sys_set_trip_temp(struct thermal_zone_device *tzd, int trip,
  168. int temp)
  169. {
  170. struct intel_soc_dts_sensor_entry *dts = tzd->devdata;
  171. struct intel_soc_dts_sensors *sensors = dts->sensors;
  172. int status;
  173. if (temp > sensors->tj_max)
  174. return -EINVAL;
  175. mutex_lock(&sensors->dts_update_lock);
  176. status = update_trip_temp(tzd->devdata, trip, temp,
  177. dts->trip_types[trip]);
  178. mutex_unlock(&sensors->dts_update_lock);
  179. return status;
  180. }
  181. static int sys_get_trip_type(struct thermal_zone_device *tzd,
  182. int trip, enum thermal_trip_type *type)
  183. {
  184. struct intel_soc_dts_sensor_entry *dts;
  185. dts = tzd->devdata;
  186. *type = dts->trip_types[trip];
  187. return 0;
  188. }
  189. static int sys_get_curr_temp(struct thermal_zone_device *tzd,
  190. int *temp)
  191. {
  192. int status;
  193. u32 out;
  194. struct intel_soc_dts_sensor_entry *dts;
  195. struct intel_soc_dts_sensors *sensors;
  196. dts = tzd->devdata;
  197. sensors = dts->sensors;
  198. status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
  199. SOC_DTS_OFFSET_TEMP, &out);
  200. if (status)
  201. return status;
  202. out = (out & dts->temp_mask) >> dts->temp_shift;
  203. out -= SOC_DTS_TJMAX_ENCODING;
  204. *temp = sensors->tj_max - out * 1000;
  205. return 0;
  206. }
  207. static struct thermal_zone_device_ops tzone_ops = {
  208. .get_temp = sys_get_curr_temp,
  209. .get_trip_temp = sys_get_trip_temp,
  210. .get_trip_type = sys_get_trip_type,
  211. .set_trip_temp = sys_set_trip_temp,
  212. };
  213. static int soc_dts_enable(int id)
  214. {
  215. u32 out;
  216. int ret;
  217. ret = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
  218. SOC_DTS_OFFSET_ENABLE, &out);
  219. if (ret)
  220. return ret;
  221. if (!(out & BIT(id))) {
  222. out |= BIT(id);
  223. ret = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
  224. SOC_DTS_OFFSET_ENABLE, out);
  225. if (ret)
  226. return ret;
  227. }
  228. return ret;
  229. }
  230. static void remove_dts_thermal_zone(struct intel_soc_dts_sensor_entry *dts)
  231. {
  232. if (dts) {
  233. iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
  234. SOC_DTS_OFFSET_ENABLE, dts->store_status);
  235. thermal_zone_device_unregister(dts->tzone);
  236. }
  237. }
  238. static int add_dts_thermal_zone(int id, struct intel_soc_dts_sensor_entry *dts,
  239. bool notification_support, int trip_cnt,
  240. int read_only_trip_cnt)
  241. {
  242. char name[10];
  243. int trip_count = 0;
  244. int trip_mask = 0;
  245. u32 store_ptps;
  246. int ret;
  247. int i;
  248. /* Store status to restor on exit */
  249. ret = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
  250. SOC_DTS_OFFSET_ENABLE, &dts->store_status);
  251. if (ret)
  252. goto err_ret;
  253. dts->id = id;
  254. dts->temp_mask = 0x00FF << (id * 8);
  255. dts->temp_shift = id * 8;
  256. if (notification_support) {
  257. trip_count = min(SOC_MAX_DTS_TRIPS, trip_cnt);
  258. trip_mask = BIT(trip_count - read_only_trip_cnt) - 1;
  259. }
  260. /* Check if the writable trip we provide is not used by BIOS */
  261. ret = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
  262. SOC_DTS_OFFSET_PTPS, &store_ptps);
  263. if (ret)
  264. trip_mask = 0;
  265. else {
  266. for (i = 0; i < trip_count; ++i) {
  267. if (trip_mask & BIT(i))
  268. if (store_ptps & (0xff << (i * 8)))
  269. trip_mask &= ~BIT(i);
  270. }
  271. }
  272. dts->trip_mask = trip_mask;
  273. dts->trip_count = trip_count;
  274. snprintf(name, sizeof(name), "soc_dts%d", id);
  275. dts->tzone = thermal_zone_device_register(name,
  276. trip_count,
  277. trip_mask,
  278. dts, &tzone_ops,
  279. NULL, 0, 0);
  280. if (IS_ERR(dts->tzone)) {
  281. ret = PTR_ERR(dts->tzone);
  282. goto err_ret;
  283. }
  284. ret = soc_dts_enable(id);
  285. if (ret)
  286. goto err_enable;
  287. return 0;
  288. err_enable:
  289. thermal_zone_device_unregister(dts->tzone);
  290. err_ret:
  291. return ret;
  292. }
  293. int intel_soc_dts_iosf_add_read_only_critical_trip(
  294. struct intel_soc_dts_sensors *sensors, int critical_offset)
  295. {
  296. int i, j;
  297. for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
  298. for (j = 0; j < sensors->soc_dts[i].trip_count; ++j) {
  299. if (!(sensors->soc_dts[i].trip_mask & BIT(j))) {
  300. return update_trip_temp(&sensors->soc_dts[i], j,
  301. sensors->tj_max - critical_offset,
  302. THERMAL_TRIP_CRITICAL);
  303. }
  304. }
  305. }
  306. return -EINVAL;
  307. }
  308. EXPORT_SYMBOL_GPL(intel_soc_dts_iosf_add_read_only_critical_trip);
  309. void intel_soc_dts_iosf_interrupt_handler(struct intel_soc_dts_sensors *sensors)
  310. {
  311. u32 sticky_out;
  312. int status;
  313. u32 ptmc_out;
  314. unsigned long flags;
  315. spin_lock_irqsave(&sensors->intr_notify_lock, flags);
  316. status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
  317. SOC_DTS_OFFSET_PTMC, &ptmc_out);
  318. ptmc_out |= SOC_DTS_PTMC_APIC_DEASSERT_BIT;
  319. status = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
  320. SOC_DTS_OFFSET_PTMC, ptmc_out);
  321. status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
  322. SOC_DTS_OFFSET_PTTSS, &sticky_out);
  323. pr_debug("status %d PTTSS %x\n", status, sticky_out);
  324. if (sticky_out & SOC_DTS_TRIP_MASK) {
  325. int i;
  326. /* reset sticky bit */
  327. status = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE,
  328. SOC_DTS_OFFSET_PTTSS, sticky_out);
  329. spin_unlock_irqrestore(&sensors->intr_notify_lock, flags);
  330. for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
  331. pr_debug("TZD update for zone %d\n", i);
  332. thermal_zone_device_update(sensors->soc_dts[i].tzone,
  333. THERMAL_EVENT_UNSPECIFIED);
  334. }
  335. } else
  336. spin_unlock_irqrestore(&sensors->intr_notify_lock, flags);
  337. }
  338. EXPORT_SYMBOL_GPL(intel_soc_dts_iosf_interrupt_handler);
  339. struct intel_soc_dts_sensors *intel_soc_dts_iosf_init(
  340. enum intel_soc_dts_interrupt_type intr_type, int trip_count,
  341. int read_only_trip_count)
  342. {
  343. struct intel_soc_dts_sensors *sensors;
  344. bool notification;
  345. u32 tj_max;
  346. int ret;
  347. int i;
  348. if (!iosf_mbi_available())
  349. return ERR_PTR(-ENODEV);
  350. if (!trip_count || read_only_trip_count > trip_count)
  351. return ERR_PTR(-EINVAL);
  352. if (get_tj_max(&tj_max))
  353. return ERR_PTR(-EINVAL);
  354. sensors = kzalloc(sizeof(*sensors), GFP_KERNEL);
  355. if (!sensors)
  356. return ERR_PTR(-ENOMEM);
  357. spin_lock_init(&sensors->intr_notify_lock);
  358. mutex_init(&sensors->dts_update_lock);
  359. sensors->intr_type = intr_type;
  360. sensors->tj_max = tj_max;
  361. if (intr_type == INTEL_SOC_DTS_INTERRUPT_NONE)
  362. notification = false;
  363. else
  364. notification = true;
  365. for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
  366. sensors->soc_dts[i].sensors = sensors;
  367. ret = add_dts_thermal_zone(i, &sensors->soc_dts[i],
  368. notification, trip_count,
  369. read_only_trip_count);
  370. if (ret)
  371. goto err_free;
  372. }
  373. for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
  374. ret = update_trip_temp(&sensors->soc_dts[i], 0, 0,
  375. THERMAL_TRIP_PASSIVE);
  376. if (ret)
  377. goto err_remove_zone;
  378. ret = update_trip_temp(&sensors->soc_dts[i], 1, 0,
  379. THERMAL_TRIP_PASSIVE);
  380. if (ret)
  381. goto err_remove_zone;
  382. }
  383. return sensors;
  384. err_remove_zone:
  385. for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i)
  386. remove_dts_thermal_zone(&sensors->soc_dts[i]);
  387. err_free:
  388. kfree(sensors);
  389. return ERR_PTR(ret);
  390. }
  391. EXPORT_SYMBOL_GPL(intel_soc_dts_iosf_init);
  392. void intel_soc_dts_iosf_exit(struct intel_soc_dts_sensors *sensors)
  393. {
  394. int i;
  395. for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
  396. update_trip_temp(&sensors->soc_dts[i], 0, 0, 0);
  397. update_trip_temp(&sensors->soc_dts[i], 1, 0, 0);
  398. remove_dts_thermal_zone(&sensors->soc_dts[i]);
  399. }
  400. kfree(sensors);
  401. }
  402. EXPORT_SYMBOL_GPL(intel_soc_dts_iosf_exit);
  403. MODULE_LICENSE("GPL v2");