core.c 61 KB

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  1. /*
  2. * Copyright (c) 2005-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/firmware.h>
  19. #include <linux/of.h>
  20. #include <asm/byteorder.h>
  21. #include "core.h"
  22. #include "mac.h"
  23. #include "htc.h"
  24. #include "hif.h"
  25. #include "wmi.h"
  26. #include "bmi.h"
  27. #include "debug.h"
  28. #include "htt.h"
  29. #include "testmode.h"
  30. #include "wmi-ops.h"
  31. unsigned int ath10k_debug_mask;
  32. static unsigned int ath10k_cryptmode_param;
  33. static bool uart_print;
  34. static bool skip_otp;
  35. static bool rawmode;
  36. module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
  37. module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
  38. module_param(uart_print, bool, 0644);
  39. module_param(skip_otp, bool, 0644);
  40. module_param(rawmode, bool, 0644);
  41. MODULE_PARM_DESC(debug_mask, "Debugging mask");
  42. MODULE_PARM_DESC(uart_print, "Uart target debugging");
  43. MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
  44. MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
  45. MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath");
  46. static const struct ath10k_hw_params ath10k_hw_params_list[] = {
  47. {
  48. .id = QCA988X_HW_2_0_VERSION,
  49. .dev_id = QCA988X_2_0_DEVICE_ID,
  50. .name = "qca988x hw2.0",
  51. .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
  52. .uart_pin = 7,
  53. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
  54. .otp_exe_param = 0,
  55. .channel_counters_freq_hz = 88000,
  56. .max_probe_resp_desc_thres = 0,
  57. .cal_data_len = 2116,
  58. .fw = {
  59. .dir = QCA988X_HW_2_0_FW_DIR,
  60. .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
  61. .board_size = QCA988X_BOARD_DATA_SZ,
  62. .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
  63. },
  64. .hw_ops = &qca988x_ops,
  65. .decap_align_bytes = 4,
  66. },
  67. {
  68. .id = QCA9887_HW_1_0_VERSION,
  69. .dev_id = QCA9887_1_0_DEVICE_ID,
  70. .name = "qca9887 hw1.0",
  71. .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
  72. .uart_pin = 7,
  73. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
  74. .otp_exe_param = 0,
  75. .channel_counters_freq_hz = 88000,
  76. .max_probe_resp_desc_thres = 0,
  77. .cal_data_len = 2116,
  78. .fw = {
  79. .dir = QCA9887_HW_1_0_FW_DIR,
  80. .board = QCA9887_HW_1_0_BOARD_DATA_FILE,
  81. .board_size = QCA9887_BOARD_DATA_SZ,
  82. .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ,
  83. },
  84. .hw_ops = &qca988x_ops,
  85. .decap_align_bytes = 4,
  86. },
  87. {
  88. .id = QCA6174_HW_2_1_VERSION,
  89. .dev_id = QCA6164_2_1_DEVICE_ID,
  90. .name = "qca6164 hw2.1",
  91. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  92. .uart_pin = 6,
  93. .otp_exe_param = 0,
  94. .channel_counters_freq_hz = 88000,
  95. .max_probe_resp_desc_thres = 0,
  96. .cal_data_len = 8124,
  97. .fw = {
  98. .dir = QCA6174_HW_2_1_FW_DIR,
  99. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  100. .board_size = QCA6174_BOARD_DATA_SZ,
  101. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  102. },
  103. .hw_ops = &qca988x_ops,
  104. .decap_align_bytes = 4,
  105. },
  106. {
  107. .id = QCA6174_HW_2_1_VERSION,
  108. .dev_id = QCA6174_2_1_DEVICE_ID,
  109. .name = "qca6174 hw2.1",
  110. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  111. .uart_pin = 6,
  112. .otp_exe_param = 0,
  113. .channel_counters_freq_hz = 88000,
  114. .max_probe_resp_desc_thres = 0,
  115. .cal_data_len = 8124,
  116. .fw = {
  117. .dir = QCA6174_HW_2_1_FW_DIR,
  118. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  119. .board_size = QCA6174_BOARD_DATA_SZ,
  120. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  121. },
  122. .hw_ops = &qca988x_ops,
  123. .decap_align_bytes = 4,
  124. },
  125. {
  126. .id = QCA6174_HW_3_0_VERSION,
  127. .dev_id = QCA6174_2_1_DEVICE_ID,
  128. .name = "qca6174 hw3.0",
  129. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  130. .uart_pin = 6,
  131. .otp_exe_param = 0,
  132. .channel_counters_freq_hz = 88000,
  133. .max_probe_resp_desc_thres = 0,
  134. .cal_data_len = 8124,
  135. .fw = {
  136. .dir = QCA6174_HW_3_0_FW_DIR,
  137. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  138. .board_size = QCA6174_BOARD_DATA_SZ,
  139. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  140. },
  141. .hw_ops = &qca988x_ops,
  142. .decap_align_bytes = 4,
  143. },
  144. {
  145. .id = QCA6174_HW_3_2_VERSION,
  146. .dev_id = QCA6174_2_1_DEVICE_ID,
  147. .name = "qca6174 hw3.2",
  148. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  149. .uart_pin = 6,
  150. .otp_exe_param = 0,
  151. .channel_counters_freq_hz = 88000,
  152. .max_probe_resp_desc_thres = 0,
  153. .cal_data_len = 8124,
  154. .fw = {
  155. /* uses same binaries as hw3.0 */
  156. .dir = QCA6174_HW_3_0_FW_DIR,
  157. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  158. .board_size = QCA6174_BOARD_DATA_SZ,
  159. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  160. },
  161. .hw_ops = &qca988x_ops,
  162. .decap_align_bytes = 4,
  163. },
  164. {
  165. .id = QCA99X0_HW_2_0_DEV_VERSION,
  166. .dev_id = QCA99X0_2_0_DEVICE_ID,
  167. .name = "qca99x0 hw2.0",
  168. .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
  169. .uart_pin = 7,
  170. .otp_exe_param = 0x00000700,
  171. .continuous_frag_desc = true,
  172. .cck_rate_map_rev2 = true,
  173. .channel_counters_freq_hz = 150000,
  174. .max_probe_resp_desc_thres = 24,
  175. .tx_chain_mask = 0xf,
  176. .rx_chain_mask = 0xf,
  177. .max_spatial_stream = 4,
  178. .cal_data_len = 12064,
  179. .fw = {
  180. .dir = QCA99X0_HW_2_0_FW_DIR,
  181. .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
  182. .board_size = QCA99X0_BOARD_DATA_SZ,
  183. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  184. },
  185. .sw_decrypt_mcast_mgmt = true,
  186. .hw_ops = &qca99x0_ops,
  187. .decap_align_bytes = 1,
  188. },
  189. {
  190. .id = QCA9984_HW_1_0_DEV_VERSION,
  191. .dev_id = QCA9984_1_0_DEVICE_ID,
  192. .name = "qca9984/qca9994 hw1.0",
  193. .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
  194. .uart_pin = 7,
  195. .otp_exe_param = 0x00000700,
  196. .continuous_frag_desc = true,
  197. .cck_rate_map_rev2 = true,
  198. .channel_counters_freq_hz = 150000,
  199. .max_probe_resp_desc_thres = 24,
  200. .tx_chain_mask = 0xf,
  201. .rx_chain_mask = 0xf,
  202. .max_spatial_stream = 4,
  203. .cal_data_len = 12064,
  204. .fw = {
  205. .dir = QCA9984_HW_1_0_FW_DIR,
  206. .board = QCA9984_HW_1_0_BOARD_DATA_FILE,
  207. .board_size = QCA99X0_BOARD_DATA_SZ,
  208. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  209. },
  210. .sw_decrypt_mcast_mgmt = true,
  211. .hw_ops = &qca99x0_ops,
  212. .decap_align_bytes = 1,
  213. },
  214. {
  215. .id = QCA9888_HW_2_0_DEV_VERSION,
  216. .dev_id = QCA9888_2_0_DEVICE_ID,
  217. .name = "qca9888 hw2.0",
  218. .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
  219. .uart_pin = 7,
  220. .otp_exe_param = 0x00000700,
  221. .continuous_frag_desc = true,
  222. .channel_counters_freq_hz = 150000,
  223. .max_probe_resp_desc_thres = 24,
  224. .tx_chain_mask = 3,
  225. .rx_chain_mask = 3,
  226. .max_spatial_stream = 2,
  227. .cal_data_len = 12064,
  228. .fw = {
  229. .dir = QCA9888_HW_2_0_FW_DIR,
  230. .board = QCA9888_HW_2_0_BOARD_DATA_FILE,
  231. .board_size = QCA99X0_BOARD_DATA_SZ,
  232. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  233. },
  234. .sw_decrypt_mcast_mgmt = true,
  235. .hw_ops = &qca99x0_ops,
  236. .decap_align_bytes = 1,
  237. },
  238. {
  239. .id = QCA9377_HW_1_0_DEV_VERSION,
  240. .dev_id = QCA9377_1_0_DEVICE_ID,
  241. .name = "qca9377 hw1.0",
  242. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  243. .uart_pin = 6,
  244. .otp_exe_param = 0,
  245. .channel_counters_freq_hz = 88000,
  246. .max_probe_resp_desc_thres = 0,
  247. .cal_data_len = 8124,
  248. .fw = {
  249. .dir = QCA9377_HW_1_0_FW_DIR,
  250. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  251. .board_size = QCA9377_BOARD_DATA_SZ,
  252. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  253. },
  254. .hw_ops = &qca988x_ops,
  255. .decap_align_bytes = 4,
  256. },
  257. {
  258. .id = QCA9377_HW_1_1_DEV_VERSION,
  259. .dev_id = QCA9377_1_0_DEVICE_ID,
  260. .name = "qca9377 hw1.1",
  261. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  262. .uart_pin = 6,
  263. .otp_exe_param = 0,
  264. .channel_counters_freq_hz = 88000,
  265. .max_probe_resp_desc_thres = 0,
  266. .cal_data_len = 8124,
  267. .fw = {
  268. .dir = QCA9377_HW_1_0_FW_DIR,
  269. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  270. .board_size = QCA9377_BOARD_DATA_SZ,
  271. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  272. },
  273. .hw_ops = &qca988x_ops,
  274. .decap_align_bytes = 4,
  275. },
  276. {
  277. .id = QCA4019_HW_1_0_DEV_VERSION,
  278. .dev_id = 0,
  279. .name = "qca4019 hw1.0",
  280. .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
  281. .uart_pin = 7,
  282. .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
  283. .otp_exe_param = 0x0010000,
  284. .continuous_frag_desc = true,
  285. .cck_rate_map_rev2 = true,
  286. .channel_counters_freq_hz = 125000,
  287. .max_probe_resp_desc_thres = 24,
  288. .tx_chain_mask = 0x3,
  289. .rx_chain_mask = 0x3,
  290. .max_spatial_stream = 2,
  291. .cal_data_len = 12064,
  292. .fw = {
  293. .dir = QCA4019_HW_1_0_FW_DIR,
  294. .board = QCA4019_HW_1_0_BOARD_DATA_FILE,
  295. .board_size = QCA4019_BOARD_DATA_SZ,
  296. .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
  297. },
  298. .sw_decrypt_mcast_mgmt = true,
  299. .hw_ops = &qca99x0_ops,
  300. .decap_align_bytes = 1,
  301. },
  302. };
  303. static const char *const ath10k_core_fw_feature_str[] = {
  304. [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
  305. [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
  306. [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
  307. [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
  308. [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
  309. [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
  310. [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
  311. [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
  312. [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
  313. [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
  314. [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
  315. [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
  316. [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
  317. [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl",
  318. [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param",
  319. [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war",
  320. };
  321. static unsigned int ath10k_core_get_fw_feature_str(char *buf,
  322. size_t buf_len,
  323. enum ath10k_fw_features feat)
  324. {
  325. /* make sure that ath10k_core_fw_feature_str[] gets updated */
  326. BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
  327. ATH10K_FW_FEATURE_COUNT);
  328. if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
  329. WARN_ON(!ath10k_core_fw_feature_str[feat])) {
  330. return scnprintf(buf, buf_len, "bit%d", feat);
  331. }
  332. return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
  333. }
  334. void ath10k_core_get_fw_features_str(struct ath10k *ar,
  335. char *buf,
  336. size_t buf_len)
  337. {
  338. unsigned int len = 0;
  339. int i;
  340. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  341. if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) {
  342. if (len > 0)
  343. len += scnprintf(buf + len, buf_len - len, ",");
  344. len += ath10k_core_get_fw_feature_str(buf + len,
  345. buf_len - len,
  346. i);
  347. }
  348. }
  349. }
  350. static void ath10k_send_suspend_complete(struct ath10k *ar)
  351. {
  352. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
  353. complete(&ar->target_suspend);
  354. }
  355. static int ath10k_init_configure_target(struct ath10k *ar)
  356. {
  357. u32 param_host;
  358. int ret;
  359. /* tell target which HTC version it is used*/
  360. ret = ath10k_bmi_write32(ar, hi_app_host_interest,
  361. HTC_PROTOCOL_VERSION);
  362. if (ret) {
  363. ath10k_err(ar, "settings HTC version failed\n");
  364. return ret;
  365. }
  366. /* set the firmware mode to STA/IBSS/AP */
  367. ret = ath10k_bmi_read32(ar, hi_option_flag, &param_host);
  368. if (ret) {
  369. ath10k_err(ar, "setting firmware mode (1/2) failed\n");
  370. return ret;
  371. }
  372. /* TODO following parameters need to be re-visited. */
  373. /* num_device */
  374. param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
  375. /* Firmware mode */
  376. /* FIXME: Why FW_MODE_AP ??.*/
  377. param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
  378. /* mac_addr_method */
  379. param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  380. /* firmware_bridge */
  381. param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  382. /* fwsubmode */
  383. param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
  384. ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
  385. if (ret) {
  386. ath10k_err(ar, "setting firmware mode (2/2) failed\n");
  387. return ret;
  388. }
  389. /* We do all byte-swapping on the host */
  390. ret = ath10k_bmi_write32(ar, hi_be, 0);
  391. if (ret) {
  392. ath10k_err(ar, "setting host CPU BE mode failed\n");
  393. return ret;
  394. }
  395. /* FW descriptor/Data swap flags */
  396. ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
  397. if (ret) {
  398. ath10k_err(ar, "setting FW data/desc swap flags failed\n");
  399. return ret;
  400. }
  401. /* Some devices have a special sanity check that verifies the PCI
  402. * Device ID is written to this host interest var. It is known to be
  403. * required to boot QCA6164.
  404. */
  405. ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
  406. ar->dev_id);
  407. if (ret) {
  408. ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
  409. return ret;
  410. }
  411. return 0;
  412. }
  413. static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
  414. const char *dir,
  415. const char *file)
  416. {
  417. char filename[100];
  418. const struct firmware *fw;
  419. int ret;
  420. if (file == NULL)
  421. return ERR_PTR(-ENOENT);
  422. if (dir == NULL)
  423. dir = ".";
  424. snprintf(filename, sizeof(filename), "%s/%s", dir, file);
  425. ret = reject_firmware(&fw, filename, ar->dev);
  426. if (ret)
  427. return ERR_PTR(ret);
  428. return fw;
  429. }
  430. static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
  431. size_t data_len)
  432. {
  433. u32 board_data_size = ar->hw_params.fw.board_size;
  434. u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
  435. u32 board_ext_data_addr;
  436. int ret;
  437. ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
  438. if (ret) {
  439. ath10k_err(ar, "could not read board ext data addr (%d)\n",
  440. ret);
  441. return ret;
  442. }
  443. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  444. "boot push board extended data addr 0x%x\n",
  445. board_ext_data_addr);
  446. if (board_ext_data_addr == 0)
  447. return 0;
  448. if (data_len != (board_data_size + board_ext_data_size)) {
  449. ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
  450. data_len, board_data_size, board_ext_data_size);
  451. return -EINVAL;
  452. }
  453. ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
  454. data + board_data_size,
  455. board_ext_data_size);
  456. if (ret) {
  457. ath10k_err(ar, "could not write board ext data (%d)\n", ret);
  458. return ret;
  459. }
  460. ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
  461. (board_ext_data_size << 16) | 1);
  462. if (ret) {
  463. ath10k_err(ar, "could not write board ext data bit (%d)\n",
  464. ret);
  465. return ret;
  466. }
  467. return 0;
  468. }
  469. static int ath10k_download_board_data(struct ath10k *ar, const void *data,
  470. size_t data_len)
  471. {
  472. u32 board_data_size = ar->hw_params.fw.board_size;
  473. u32 address;
  474. int ret;
  475. ret = ath10k_push_board_ext_data(ar, data, data_len);
  476. if (ret) {
  477. ath10k_err(ar, "could not push board ext data (%d)\n", ret);
  478. goto exit;
  479. }
  480. ret = ath10k_bmi_read32(ar, hi_board_data, &address);
  481. if (ret) {
  482. ath10k_err(ar, "could not read board data addr (%d)\n", ret);
  483. goto exit;
  484. }
  485. ret = ath10k_bmi_write_memory(ar, address, data,
  486. min_t(u32, board_data_size,
  487. data_len));
  488. if (ret) {
  489. ath10k_err(ar, "could not write board data (%d)\n", ret);
  490. goto exit;
  491. }
  492. ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
  493. if (ret) {
  494. ath10k_err(ar, "could not write board data bit (%d)\n", ret);
  495. goto exit;
  496. }
  497. exit:
  498. return ret;
  499. }
  500. static int ath10k_download_cal_file(struct ath10k *ar,
  501. const struct firmware *file)
  502. {
  503. int ret;
  504. if (!file)
  505. return -ENOENT;
  506. if (IS_ERR(file))
  507. return PTR_ERR(file);
  508. ret = ath10k_download_board_data(ar, file->data, file->size);
  509. if (ret) {
  510. ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
  511. return ret;
  512. }
  513. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
  514. return 0;
  515. }
  516. static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name)
  517. {
  518. struct device_node *node;
  519. int data_len;
  520. void *data;
  521. int ret;
  522. node = ar->dev->of_node;
  523. if (!node)
  524. /* Device Tree is optional, don't print any warnings if
  525. * there's no node for ath10k.
  526. */
  527. return -ENOENT;
  528. if (!of_get_property(node, dt_name, &data_len)) {
  529. /* The calibration data node is optional */
  530. return -ENOENT;
  531. }
  532. if (data_len != ar->hw_params.cal_data_len) {
  533. ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
  534. data_len);
  535. ret = -EMSGSIZE;
  536. goto out;
  537. }
  538. data = kmalloc(data_len, GFP_KERNEL);
  539. if (!data) {
  540. ret = -ENOMEM;
  541. goto out;
  542. }
  543. ret = of_property_read_u8_array(node, dt_name, data, data_len);
  544. if (ret) {
  545. ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
  546. ret);
  547. goto out_free;
  548. }
  549. ret = ath10k_download_board_data(ar, data, data_len);
  550. if (ret) {
  551. ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
  552. ret);
  553. goto out_free;
  554. }
  555. ret = 0;
  556. out_free:
  557. kfree(data);
  558. out:
  559. return ret;
  560. }
  561. static int ath10k_download_cal_eeprom(struct ath10k *ar)
  562. {
  563. size_t data_len;
  564. void *data = NULL;
  565. int ret;
  566. ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len);
  567. if (ret) {
  568. if (ret != -EOPNOTSUPP)
  569. ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n",
  570. ret);
  571. goto out_free;
  572. }
  573. ret = ath10k_download_board_data(ar, data, data_len);
  574. if (ret) {
  575. ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n",
  576. ret);
  577. goto out_free;
  578. }
  579. ret = 0;
  580. out_free:
  581. kfree(data);
  582. return ret;
  583. }
  584. static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
  585. {
  586. u32 result, address;
  587. u8 board_id, chip_id;
  588. int ret, bmi_board_id_param;
  589. address = ar->hw_params.patch_load_addr;
  590. if (!ar->normal_mode_fw.fw_file.otp_data ||
  591. !ar->normal_mode_fw.fw_file.otp_len) {
  592. ath10k_warn(ar,
  593. "failed to retrieve board id because of invalid otp\n");
  594. return -ENODATA;
  595. }
  596. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  597. "boot upload otp to 0x%x len %zd for board id\n",
  598. address, ar->normal_mode_fw.fw_file.otp_len);
  599. ret = ath10k_bmi_fast_download(ar, address,
  600. ar->normal_mode_fw.fw_file.otp_data,
  601. ar->normal_mode_fw.fw_file.otp_len);
  602. if (ret) {
  603. ath10k_err(ar, "could not write otp for board id check: %d\n",
  604. ret);
  605. return ret;
  606. }
  607. if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
  608. ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)
  609. bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID;
  610. else
  611. bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID;
  612. ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result);
  613. if (ret) {
  614. ath10k_err(ar, "could not execute otp for board id check: %d\n",
  615. ret);
  616. return ret;
  617. }
  618. board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
  619. chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
  620. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  621. "boot get otp board id result 0x%08x board_id %d chip_id %d\n",
  622. result, board_id, chip_id);
  623. if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 ||
  624. (board_id == 0)) {
  625. ath10k_warn(ar, "board id is not exist in otp, ignore it\n");
  626. return -EOPNOTSUPP;
  627. }
  628. ar->id.bmi_ids_valid = true;
  629. ar->id.bmi_board_id = board_id;
  630. ar->id.bmi_chip_id = chip_id;
  631. return 0;
  632. }
  633. static int ath10k_download_and_run_otp(struct ath10k *ar)
  634. {
  635. u32 result, address = ar->hw_params.patch_load_addr;
  636. u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
  637. int ret;
  638. ret = ath10k_download_board_data(ar,
  639. ar->running_fw->board_data,
  640. ar->running_fw->board_len);
  641. if (ret) {
  642. ath10k_err(ar, "failed to download board data: %d\n", ret);
  643. return ret;
  644. }
  645. /* OTP is optional */
  646. if (!ar->running_fw->fw_file.otp_data ||
  647. !ar->running_fw->fw_file.otp_len) {
  648. ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n",
  649. ar->running_fw->fw_file.otp_data,
  650. ar->running_fw->fw_file.otp_len);
  651. return 0;
  652. }
  653. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
  654. address, ar->running_fw->fw_file.otp_len);
  655. ret = ath10k_bmi_fast_download(ar, address,
  656. ar->running_fw->fw_file.otp_data,
  657. ar->running_fw->fw_file.otp_len);
  658. if (ret) {
  659. ath10k_err(ar, "could not write otp (%d)\n", ret);
  660. return ret;
  661. }
  662. /* As of now pre-cal is valid for 10_4 variants */
  663. if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
  664. ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)
  665. bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL;
  666. ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
  667. if (ret) {
  668. ath10k_err(ar, "could not execute otp (%d)\n", ret);
  669. return ret;
  670. }
  671. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
  672. if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
  673. ar->running_fw->fw_file.fw_features)) &&
  674. result != 0) {
  675. ath10k_err(ar, "otp calibration failed: %d", result);
  676. return -EINVAL;
  677. }
  678. return 0;
  679. }
  680. static int ath10k_download_fw(struct ath10k *ar)
  681. {
  682. u32 address, data_len;
  683. const void *data;
  684. int ret;
  685. address = ar->hw_params.patch_load_addr;
  686. data = ar->running_fw->fw_file.firmware_data;
  687. data_len = ar->running_fw->fw_file.firmware_len;
  688. ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file);
  689. if (ret) {
  690. ath10k_err(ar, "failed to configure fw code swap: %d\n",
  691. ret);
  692. return ret;
  693. }
  694. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  695. "boot uploading firmware image %pK len %d\n",
  696. data, data_len);
  697. ret = ath10k_bmi_fast_download(ar, address, data, data_len);
  698. if (ret) {
  699. ath10k_err(ar, "failed to download firmware: %d\n",
  700. ret);
  701. return ret;
  702. }
  703. return ret;
  704. }
  705. static void ath10k_core_free_board_files(struct ath10k *ar)
  706. {
  707. if (!IS_ERR(ar->normal_mode_fw.board))
  708. release_firmware(ar->normal_mode_fw.board);
  709. ar->normal_mode_fw.board = NULL;
  710. ar->normal_mode_fw.board_data = NULL;
  711. ar->normal_mode_fw.board_len = 0;
  712. }
  713. static void ath10k_core_free_firmware_files(struct ath10k *ar)
  714. {
  715. if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware))
  716. release_firmware(ar->normal_mode_fw.fw_file.firmware);
  717. if (!IS_ERR(ar->cal_file))
  718. release_firmware(ar->cal_file);
  719. if (!IS_ERR(ar->pre_cal_file))
  720. release_firmware(ar->pre_cal_file);
  721. ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file);
  722. ar->normal_mode_fw.fw_file.otp_data = NULL;
  723. ar->normal_mode_fw.fw_file.otp_len = 0;
  724. ar->normal_mode_fw.fw_file.firmware = NULL;
  725. ar->normal_mode_fw.fw_file.firmware_data = NULL;
  726. ar->normal_mode_fw.fw_file.firmware_len = 0;
  727. ar->cal_file = NULL;
  728. ar->pre_cal_file = NULL;
  729. }
  730. static int ath10k_fetch_cal_file(struct ath10k *ar)
  731. {
  732. char filename[100];
  733. /* pre-cal-<bus>-<id>.bin */
  734. scnprintf(filename, sizeof(filename), "/*(DEBLOBBED)*/",
  735. ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
  736. ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
  737. if (!IS_ERR(ar->pre_cal_file))
  738. goto success;
  739. /*(DEBLOBBED)*/
  740. scnprintf(filename, sizeof(filename), "/*(DEBLOBBED)*/",
  741. ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
  742. ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
  743. if (IS_ERR(ar->cal_file))
  744. /* calibration file is optional, don't print any warnings */
  745. return PTR_ERR(ar->cal_file);
  746. success:
  747. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
  748. ATH10K_FW_DIR, filename);
  749. return 0;
  750. }
  751. static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar)
  752. {
  753. if (!ar->hw_params.fw.board) {
  754. ath10k_err(ar, "failed to find board file fw entry\n");
  755. return -EINVAL;
  756. }
  757. ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
  758. ar->hw_params.fw.dir,
  759. ar->hw_params.fw.board);
  760. if (IS_ERR(ar->normal_mode_fw.board))
  761. return PTR_ERR(ar->normal_mode_fw.board);
  762. ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data;
  763. ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size;
  764. return 0;
  765. }
  766. static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
  767. const void *buf, size_t buf_len,
  768. const char *boardname)
  769. {
  770. const struct ath10k_fw_ie *hdr;
  771. bool name_match_found;
  772. int ret, board_ie_id;
  773. size_t board_ie_len;
  774. const void *board_ie_data;
  775. name_match_found = false;
  776. /* go through ATH10K_BD_IE_BOARD_ elements */
  777. while (buf_len > sizeof(struct ath10k_fw_ie)) {
  778. hdr = buf;
  779. board_ie_id = le32_to_cpu(hdr->id);
  780. board_ie_len = le32_to_cpu(hdr->len);
  781. board_ie_data = hdr->data;
  782. buf_len -= sizeof(*hdr);
  783. buf += sizeof(*hdr);
  784. if (buf_len < ALIGN(board_ie_len, 4)) {
  785. ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
  786. buf_len, ALIGN(board_ie_len, 4));
  787. ret = -EINVAL;
  788. goto out;
  789. }
  790. switch (board_ie_id) {
  791. case ATH10K_BD_IE_BOARD_NAME:
  792. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
  793. board_ie_data, board_ie_len);
  794. if (board_ie_len != strlen(boardname))
  795. break;
  796. ret = memcmp(board_ie_data, boardname, strlen(boardname));
  797. if (ret)
  798. break;
  799. name_match_found = true;
  800. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  801. "boot found match for name '%s'",
  802. boardname);
  803. break;
  804. case ATH10K_BD_IE_BOARD_DATA:
  805. if (!name_match_found)
  806. /* no match found */
  807. break;
  808. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  809. "boot found board data for '%s'",
  810. boardname);
  811. ar->normal_mode_fw.board_data = board_ie_data;
  812. ar->normal_mode_fw.board_len = board_ie_len;
  813. ret = 0;
  814. goto out;
  815. default:
  816. ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
  817. board_ie_id);
  818. break;
  819. }
  820. /* jump over the padding */
  821. board_ie_len = ALIGN(board_ie_len, 4);
  822. buf_len -= board_ie_len;
  823. buf += board_ie_len;
  824. }
  825. /* no match found */
  826. ret = -ENOENT;
  827. out:
  828. return ret;
  829. }
  830. static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
  831. const char *boardname,
  832. const char *filename)
  833. {
  834. size_t len, magic_len, ie_len;
  835. struct ath10k_fw_ie *hdr;
  836. const u8 *data;
  837. int ret, ie_id;
  838. ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
  839. ar->hw_params.fw.dir,
  840. filename);
  841. if (IS_ERR(ar->normal_mode_fw.board))
  842. return PTR_ERR(ar->normal_mode_fw.board);
  843. data = ar->normal_mode_fw.board->data;
  844. len = ar->normal_mode_fw.board->size;
  845. /* magic has extra null byte padded */
  846. magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
  847. if (len < magic_len) {
  848. ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
  849. ar->hw_params.fw.dir, filename, len);
  850. ret = -EINVAL;
  851. goto err;
  852. }
  853. if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
  854. ath10k_err(ar, "found invalid board magic\n");
  855. ret = -EINVAL;
  856. goto err;
  857. }
  858. /* magic is padded to 4 bytes */
  859. magic_len = ALIGN(magic_len, 4);
  860. if (len < magic_len) {
  861. ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
  862. ar->hw_params.fw.dir, filename, len);
  863. ret = -EINVAL;
  864. goto err;
  865. }
  866. data += magic_len;
  867. len -= magic_len;
  868. while (len > sizeof(struct ath10k_fw_ie)) {
  869. hdr = (struct ath10k_fw_ie *)data;
  870. ie_id = le32_to_cpu(hdr->id);
  871. ie_len = le32_to_cpu(hdr->len);
  872. len -= sizeof(*hdr);
  873. data = hdr->data;
  874. if (len < ALIGN(ie_len, 4)) {
  875. ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
  876. ie_id, ie_len, len);
  877. ret = -EINVAL;
  878. goto err;
  879. }
  880. switch (ie_id) {
  881. case ATH10K_BD_IE_BOARD:
  882. ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
  883. boardname);
  884. if (ret == -ENOENT)
  885. /* no match found, continue */
  886. break;
  887. else if (ret)
  888. /* there was an error, bail out */
  889. goto err;
  890. /* board data found */
  891. goto out;
  892. }
  893. /* jump over the padding */
  894. ie_len = ALIGN(ie_len, 4);
  895. len -= ie_len;
  896. data += ie_len;
  897. }
  898. out:
  899. if (!ar->normal_mode_fw.board_data || !ar->normal_mode_fw.board_len) {
  900. ath10k_err(ar,
  901. "failed to fetch board data for %s from %s/%s\n",
  902. boardname, ar->hw_params.fw.dir, filename);
  903. ret = -ENODATA;
  904. goto err;
  905. }
  906. return 0;
  907. err:
  908. ath10k_core_free_board_files(ar);
  909. return ret;
  910. }
  911. static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
  912. size_t name_len)
  913. {
  914. if (ar->id.bmi_ids_valid) {
  915. scnprintf(name, name_len,
  916. "bus=%s,bmi-chip-id=%d,bmi-board-id=%d",
  917. ath10k_bus_str(ar->hif.bus),
  918. ar->id.bmi_chip_id,
  919. ar->id.bmi_board_id);
  920. goto out;
  921. }
  922. scnprintf(name, name_len,
  923. "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x",
  924. ath10k_bus_str(ar->hif.bus),
  925. ar->id.vendor, ar->id.device,
  926. ar->id.subsystem_vendor, ar->id.subsystem_device);
  927. out:
  928. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
  929. return 0;
  930. }
  931. static int ath10k_core_fetch_board_file(struct ath10k *ar)
  932. {
  933. char boardname[100];
  934. int ret;
  935. ret = ath10k_core_create_board_name(ar, boardname, sizeof(boardname));
  936. if (ret) {
  937. ath10k_err(ar, "failed to create board name: %d", ret);
  938. return ret;
  939. }
  940. ar->bd_api = 2;
  941. ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
  942. ATH10K_BOARD_API2_FILE);
  943. if (!ret)
  944. goto success;
  945. ar->bd_api = 1;
  946. ret = ath10k_core_fetch_board_data_api_1(ar);
  947. if (ret) {
  948. ath10k_err(ar, "failed to fetch board data\n");
  949. return ret;
  950. }
  951. success:
  952. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
  953. return 0;
  954. }
  955. int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
  956. struct ath10k_fw_file *fw_file)
  957. {
  958. size_t magic_len, len, ie_len;
  959. int ie_id, i, index, bit, ret;
  960. struct ath10k_fw_ie *hdr;
  961. const u8 *data;
  962. __le32 *timestamp, *version;
  963. /* first fetch the firmware file (firmware-*.bin) */
  964. fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
  965. name);
  966. if (IS_ERR(fw_file->firmware)) {
  967. ath10k_err(ar, "could not fetch firmware file '%s/%s': %ld\n",
  968. ar->hw_params.fw.dir, name,
  969. PTR_ERR(fw_file->firmware));
  970. return PTR_ERR(fw_file->firmware);
  971. }
  972. data = fw_file->firmware->data;
  973. len = fw_file->firmware->size;
  974. /* magic also includes the null byte, check that as well */
  975. magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
  976. if (len < magic_len) {
  977. ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
  978. ar->hw_params.fw.dir, name, len);
  979. ret = -EINVAL;
  980. goto err;
  981. }
  982. if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
  983. ath10k_err(ar, "invalid firmware magic\n");
  984. ret = -EINVAL;
  985. goto err;
  986. }
  987. /* jump over the padding */
  988. magic_len = ALIGN(magic_len, 4);
  989. len -= magic_len;
  990. data += magic_len;
  991. /* loop elements */
  992. while (len > sizeof(struct ath10k_fw_ie)) {
  993. hdr = (struct ath10k_fw_ie *)data;
  994. ie_id = le32_to_cpu(hdr->id);
  995. ie_len = le32_to_cpu(hdr->len);
  996. len -= sizeof(*hdr);
  997. data += sizeof(*hdr);
  998. if (len < ie_len) {
  999. ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
  1000. ie_id, len, ie_len);
  1001. ret = -EINVAL;
  1002. goto err;
  1003. }
  1004. switch (ie_id) {
  1005. case ATH10K_FW_IE_FW_VERSION:
  1006. if (ie_len > sizeof(fw_file->fw_version) - 1)
  1007. break;
  1008. memcpy(fw_file->fw_version, data, ie_len);
  1009. fw_file->fw_version[ie_len] = '\0';
  1010. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1011. "found fw version %s\n",
  1012. fw_file->fw_version);
  1013. break;
  1014. case ATH10K_FW_IE_TIMESTAMP:
  1015. if (ie_len != sizeof(u32))
  1016. break;
  1017. timestamp = (__le32 *)data;
  1018. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
  1019. le32_to_cpup(timestamp));
  1020. break;
  1021. case ATH10K_FW_IE_FEATURES:
  1022. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1023. "found firmware features ie (%zd B)\n",
  1024. ie_len);
  1025. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  1026. index = i / 8;
  1027. bit = i % 8;
  1028. if (index == ie_len)
  1029. break;
  1030. if (data[index] & (1 << bit)) {
  1031. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1032. "Enabling feature bit: %i\n",
  1033. i);
  1034. __set_bit(i, fw_file->fw_features);
  1035. }
  1036. }
  1037. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
  1038. fw_file->fw_features,
  1039. sizeof(fw_file->fw_features));
  1040. break;
  1041. case ATH10K_FW_IE_FW_IMAGE:
  1042. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1043. "found fw image ie (%zd B)\n",
  1044. ie_len);
  1045. fw_file->firmware_data = data;
  1046. fw_file->firmware_len = ie_len;
  1047. break;
  1048. case ATH10K_FW_IE_OTP_IMAGE:
  1049. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1050. "found otp image ie (%zd B)\n",
  1051. ie_len);
  1052. fw_file->otp_data = data;
  1053. fw_file->otp_len = ie_len;
  1054. break;
  1055. case ATH10K_FW_IE_WMI_OP_VERSION:
  1056. if (ie_len != sizeof(u32))
  1057. break;
  1058. version = (__le32 *)data;
  1059. fw_file->wmi_op_version = le32_to_cpup(version);
  1060. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
  1061. fw_file->wmi_op_version);
  1062. break;
  1063. case ATH10K_FW_IE_HTT_OP_VERSION:
  1064. if (ie_len != sizeof(u32))
  1065. break;
  1066. version = (__le32 *)data;
  1067. fw_file->htt_op_version = le32_to_cpup(version);
  1068. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
  1069. fw_file->htt_op_version);
  1070. break;
  1071. case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
  1072. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1073. "found fw code swap image ie (%zd B)\n",
  1074. ie_len);
  1075. fw_file->codeswap_data = data;
  1076. fw_file->codeswap_len = ie_len;
  1077. break;
  1078. default:
  1079. ath10k_warn(ar, "Unknown FW IE: %u\n",
  1080. le32_to_cpu(hdr->id));
  1081. break;
  1082. }
  1083. /* jump over the padding */
  1084. ie_len = ALIGN(ie_len, 4);
  1085. len -= ie_len;
  1086. data += ie_len;
  1087. }
  1088. if (!fw_file->firmware_data ||
  1089. !fw_file->firmware_len) {
  1090. ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
  1091. ar->hw_params.fw.dir, name);
  1092. ret = -ENOMEDIUM;
  1093. goto err;
  1094. }
  1095. return 0;
  1096. err:
  1097. ath10k_core_free_firmware_files(ar);
  1098. return ret;
  1099. }
  1100. static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
  1101. {
  1102. int ret;
  1103. /* calibration file is optional, don't check for any errors */
  1104. ath10k_fetch_cal_file(ar);
  1105. ar->fw_api = 5;
  1106. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1107. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API5_FILE,
  1108. &ar->normal_mode_fw.fw_file);
  1109. if (ret == 0)
  1110. goto success;
  1111. ar->fw_api = 4;
  1112. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1113. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API4_FILE,
  1114. &ar->normal_mode_fw.fw_file);
  1115. if (ret == 0)
  1116. goto success;
  1117. ar->fw_api = 3;
  1118. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1119. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE,
  1120. &ar->normal_mode_fw.fw_file);
  1121. if (ret == 0)
  1122. goto success;
  1123. ar->fw_api = 2;
  1124. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1125. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE,
  1126. &ar->normal_mode_fw.fw_file);
  1127. if (ret)
  1128. return ret;
  1129. success:
  1130. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  1131. return 0;
  1132. }
  1133. static int ath10k_core_pre_cal_download(struct ath10k *ar)
  1134. {
  1135. int ret;
  1136. ret = ath10k_download_cal_file(ar, ar->pre_cal_file);
  1137. if (ret == 0) {
  1138. ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;
  1139. goto success;
  1140. }
  1141. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1142. "boot did not find a pre calibration file, try DT next: %d\n",
  1143. ret);
  1144. ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data");
  1145. if (ret) {
  1146. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1147. "unable to load pre cal data from DT: %d\n", ret);
  1148. return ret;
  1149. }
  1150. ar->cal_mode = ATH10K_PRE_CAL_MODE_DT;
  1151. success:
  1152. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
  1153. ath10k_cal_mode_str(ar->cal_mode));
  1154. return 0;
  1155. }
  1156. static int ath10k_core_pre_cal_config(struct ath10k *ar)
  1157. {
  1158. int ret;
  1159. ret = ath10k_core_pre_cal_download(ar);
  1160. if (ret) {
  1161. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1162. "failed to load pre cal data: %d\n", ret);
  1163. return ret;
  1164. }
  1165. ret = ath10k_core_get_board_id_from_otp(ar);
  1166. if (ret) {
  1167. ath10k_err(ar, "failed to get board id: %d\n", ret);
  1168. return ret;
  1169. }
  1170. ret = ath10k_download_and_run_otp(ar);
  1171. if (ret) {
  1172. ath10k_err(ar, "failed to run otp: %d\n", ret);
  1173. return ret;
  1174. }
  1175. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1176. "pre cal configuration done successfully\n");
  1177. return 0;
  1178. }
  1179. static int ath10k_download_cal_data(struct ath10k *ar)
  1180. {
  1181. int ret;
  1182. ret = ath10k_core_pre_cal_config(ar);
  1183. if (ret == 0)
  1184. return 0;
  1185. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1186. "pre cal download procedure failed, try cal file: %d\n",
  1187. ret);
  1188. ret = ath10k_download_cal_file(ar, ar->cal_file);
  1189. if (ret == 0) {
  1190. ar->cal_mode = ATH10K_CAL_MODE_FILE;
  1191. goto done;
  1192. }
  1193. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1194. "boot did not find a calibration file, try DT next: %d\n",
  1195. ret);
  1196. ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data");
  1197. if (ret == 0) {
  1198. ar->cal_mode = ATH10K_CAL_MODE_DT;
  1199. goto done;
  1200. }
  1201. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1202. "boot did not find DT entry, try target EEPROM next: %d\n",
  1203. ret);
  1204. ret = ath10k_download_cal_eeprom(ar);
  1205. if (ret == 0) {
  1206. ar->cal_mode = ATH10K_CAL_MODE_EEPROM;
  1207. goto done;
  1208. }
  1209. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1210. "boot did not find target EEPROM entry, try OTP next: %d\n",
  1211. ret);
  1212. ret = ath10k_download_and_run_otp(ar);
  1213. if (ret) {
  1214. ath10k_err(ar, "failed to run otp: %d\n", ret);
  1215. return ret;
  1216. }
  1217. ar->cal_mode = ATH10K_CAL_MODE_OTP;
  1218. done:
  1219. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
  1220. ath10k_cal_mode_str(ar->cal_mode));
  1221. return 0;
  1222. }
  1223. static int ath10k_init_uart(struct ath10k *ar)
  1224. {
  1225. int ret;
  1226. /*
  1227. * Explicitly setting UART prints to zero as target turns it on
  1228. * based on scratch registers.
  1229. */
  1230. ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
  1231. if (ret) {
  1232. ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
  1233. return ret;
  1234. }
  1235. if (!uart_print)
  1236. return 0;
  1237. ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
  1238. if (ret) {
  1239. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1240. return ret;
  1241. }
  1242. ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
  1243. if (ret) {
  1244. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1245. return ret;
  1246. }
  1247. /* Set the UART baud rate to 19200. */
  1248. ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
  1249. if (ret) {
  1250. ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
  1251. return ret;
  1252. }
  1253. ath10k_info(ar, "UART prints enabled\n");
  1254. return 0;
  1255. }
  1256. static int ath10k_init_hw_params(struct ath10k *ar)
  1257. {
  1258. const struct ath10k_hw_params *uninitialized_var(hw_params);
  1259. int i;
  1260. for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
  1261. hw_params = &ath10k_hw_params_list[i];
  1262. if (hw_params->id == ar->target_version &&
  1263. hw_params->dev_id == ar->dev_id)
  1264. break;
  1265. }
  1266. if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
  1267. ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
  1268. ar->target_version);
  1269. return -EINVAL;
  1270. }
  1271. ar->hw_params = *hw_params;
  1272. ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
  1273. ar->hw_params.name, ar->target_version);
  1274. return 0;
  1275. }
  1276. static void ath10k_core_restart(struct work_struct *work)
  1277. {
  1278. struct ath10k *ar = container_of(work, struct ath10k, restart_work);
  1279. set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1280. /* Place a barrier to make sure the compiler doesn't reorder
  1281. * CRASH_FLUSH and calling other functions.
  1282. */
  1283. barrier();
  1284. ieee80211_stop_queues(ar->hw);
  1285. ath10k_drain_tx(ar);
  1286. complete(&ar->scan.started);
  1287. complete(&ar->scan.completed);
  1288. complete(&ar->scan.on_channel);
  1289. complete(&ar->offchan_tx_completed);
  1290. complete(&ar->install_key_done);
  1291. complete(&ar->vdev_setup_done);
  1292. complete(&ar->thermal.wmi_sync);
  1293. complete(&ar->bss_survey_done);
  1294. wake_up(&ar->htt.empty_tx_wq);
  1295. wake_up(&ar->wmi.tx_credits_wq);
  1296. wake_up(&ar->peer_mapping_wq);
  1297. mutex_lock(&ar->conf_mutex);
  1298. switch (ar->state) {
  1299. case ATH10K_STATE_ON:
  1300. ar->state = ATH10K_STATE_RESTARTING;
  1301. ath10k_halt(ar);
  1302. ath10k_scan_finish(ar);
  1303. ieee80211_restart_hw(ar->hw);
  1304. break;
  1305. case ATH10K_STATE_OFF:
  1306. /* this can happen if driver is being unloaded
  1307. * or if the crash happens during FW probing */
  1308. ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
  1309. break;
  1310. case ATH10K_STATE_RESTARTING:
  1311. /* hw restart might be requested from multiple places */
  1312. break;
  1313. case ATH10K_STATE_RESTARTED:
  1314. ar->state = ATH10K_STATE_WEDGED;
  1315. /* fall through */
  1316. case ATH10K_STATE_WEDGED:
  1317. ath10k_warn(ar, "device is wedged, will not restart\n");
  1318. break;
  1319. case ATH10K_STATE_UTF:
  1320. ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
  1321. break;
  1322. }
  1323. mutex_unlock(&ar->conf_mutex);
  1324. }
  1325. static int ath10k_core_init_firmware_features(struct ath10k *ar)
  1326. {
  1327. struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
  1328. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) &&
  1329. !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
  1330. ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
  1331. return -EINVAL;
  1332. }
  1333. if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
  1334. ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
  1335. ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version);
  1336. return -EINVAL;
  1337. }
  1338. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
  1339. switch (ath10k_cryptmode_param) {
  1340. case ATH10K_CRYPT_MODE_HW:
  1341. clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1342. clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1343. break;
  1344. case ATH10K_CRYPT_MODE_SW:
  1345. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1346. fw_file->fw_features)) {
  1347. ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
  1348. return -EINVAL;
  1349. }
  1350. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1351. set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1352. break;
  1353. default:
  1354. ath10k_info(ar, "invalid cryptmode: %d\n",
  1355. ath10k_cryptmode_param);
  1356. return -EINVAL;
  1357. }
  1358. ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
  1359. ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
  1360. if (rawmode) {
  1361. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1362. fw_file->fw_features)) {
  1363. ath10k_err(ar, "rawmode = 1 requires support from firmware");
  1364. return -EINVAL;
  1365. }
  1366. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1367. }
  1368. if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
  1369. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
  1370. /* Workaround:
  1371. *
  1372. * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
  1373. * and causes enormous performance issues (malformed frames,
  1374. * etc).
  1375. *
  1376. * Disabling A-MSDU makes RAW mode stable with heavy traffic
  1377. * albeit a bit slower compared to regular operation.
  1378. */
  1379. ar->htt.max_num_amsdu = 1;
  1380. }
  1381. /* Backwards compatibility for firmwares without
  1382. * ATH10K_FW_IE_WMI_OP_VERSION.
  1383. */
  1384. if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
  1385. if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
  1386. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
  1387. fw_file->fw_features))
  1388. fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
  1389. else
  1390. fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
  1391. } else {
  1392. fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
  1393. }
  1394. }
  1395. switch (fw_file->wmi_op_version) {
  1396. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1397. ar->max_num_peers = TARGET_NUM_PEERS;
  1398. ar->max_num_stations = TARGET_NUM_STATIONS;
  1399. ar->max_num_vdevs = TARGET_NUM_VDEVS;
  1400. ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
  1401. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1402. WMI_STAT_PEER;
  1403. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1404. break;
  1405. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1406. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1407. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1408. if (ath10k_peer_stats_enabled(ar)) {
  1409. ar->max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS;
  1410. ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS;
  1411. } else {
  1412. ar->max_num_peers = TARGET_10X_NUM_PEERS;
  1413. ar->max_num_stations = TARGET_10X_NUM_STATIONS;
  1414. }
  1415. ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
  1416. ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
  1417. ar->fw_stats_req_mask = WMI_STAT_PEER;
  1418. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1419. break;
  1420. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1421. ar->max_num_peers = TARGET_TLV_NUM_PEERS;
  1422. ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
  1423. ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
  1424. ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
  1425. ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
  1426. ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
  1427. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1428. WMI_STAT_PEER;
  1429. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1430. break;
  1431. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1432. ar->max_num_peers = TARGET_10_4_NUM_PEERS;
  1433. ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
  1434. ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
  1435. ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
  1436. ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
  1437. ar->fw_stats_req_mask = WMI_10_4_STAT_PEER |
  1438. WMI_10_4_STAT_PEER_EXTD;
  1439. ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
  1440. if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
  1441. fw_file->fw_features))
  1442. ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC;
  1443. else
  1444. ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
  1445. break;
  1446. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1447. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1448. WARN_ON(1);
  1449. return -EINVAL;
  1450. }
  1451. /* Backwards compatibility for firmwares without
  1452. * ATH10K_FW_IE_HTT_OP_VERSION.
  1453. */
  1454. if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
  1455. switch (fw_file->wmi_op_version) {
  1456. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1457. fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
  1458. break;
  1459. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1460. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1461. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1462. fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
  1463. break;
  1464. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1465. fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
  1466. break;
  1467. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1468. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1469. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1470. ath10k_err(ar, "htt op version not found from fw meta data");
  1471. return -EINVAL;
  1472. }
  1473. }
  1474. return 0;
  1475. }
  1476. static int ath10k_core_reset_rx_filter(struct ath10k *ar)
  1477. {
  1478. int ret;
  1479. int vdev_id;
  1480. int vdev_type;
  1481. int vdev_subtype;
  1482. const u8 *vdev_addr;
  1483. vdev_id = 0;
  1484. vdev_type = WMI_VDEV_TYPE_STA;
  1485. vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE);
  1486. vdev_addr = ar->mac_addr;
  1487. ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype,
  1488. vdev_addr);
  1489. if (ret) {
  1490. ath10k_err(ar, "failed to create dummy vdev: %d\n", ret);
  1491. return ret;
  1492. }
  1493. ret = ath10k_wmi_vdev_delete(ar, vdev_id);
  1494. if (ret) {
  1495. ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret);
  1496. return ret;
  1497. }
  1498. /* WMI and HTT may use separate HIF pipes and are not guaranteed to be
  1499. * serialized properly implicitly.
  1500. *
  1501. * Moreover (most) WMI commands have no explicit acknowledges. It is
  1502. * possible to infer it implicitly by poking firmware with echo
  1503. * command - getting a reply means all preceding comments have been
  1504. * (mostly) processed.
  1505. *
  1506. * In case of vdev create/delete this is sufficient.
  1507. *
  1508. * Without this it's possible to end up with a race when HTT Rx ring is
  1509. * started before vdev create/delete hack is complete allowing a short
  1510. * window of opportunity to receive (and Tx ACK) a bunch of frames.
  1511. */
  1512. ret = ath10k_wmi_barrier(ar);
  1513. if (ret) {
  1514. ath10k_err(ar, "failed to ping firmware: %d\n", ret);
  1515. return ret;
  1516. }
  1517. return 0;
  1518. }
  1519. int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
  1520. const struct ath10k_fw_components *fw)
  1521. {
  1522. int status;
  1523. u32 val;
  1524. lockdep_assert_held(&ar->conf_mutex);
  1525. clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1526. ar->running_fw = fw;
  1527. ath10k_bmi_start(ar);
  1528. if (ath10k_init_configure_target(ar)) {
  1529. status = -EINVAL;
  1530. goto err;
  1531. }
  1532. status = ath10k_download_cal_data(ar);
  1533. if (status)
  1534. goto err;
  1535. /* Some of of qca988x solutions are having global reset issue
  1536. * during target initialization. Bypassing PLL setting before
  1537. * downloading firmware and letting the SoC run on REF_CLK is
  1538. * fixing the problem. Corresponding firmware change is also needed
  1539. * to set the clock source once the target is initialized.
  1540. */
  1541. if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
  1542. ar->running_fw->fw_file.fw_features)) {
  1543. status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
  1544. if (status) {
  1545. ath10k_err(ar, "could not write to skip_clock_init: %d\n",
  1546. status);
  1547. goto err;
  1548. }
  1549. }
  1550. status = ath10k_download_fw(ar);
  1551. if (status)
  1552. goto err;
  1553. status = ath10k_init_uart(ar);
  1554. if (status)
  1555. goto err;
  1556. ar->htc.htc_ops.target_send_suspend_complete =
  1557. ath10k_send_suspend_complete;
  1558. status = ath10k_htc_init(ar);
  1559. if (status) {
  1560. ath10k_err(ar, "could not init HTC (%d)\n", status);
  1561. goto err;
  1562. }
  1563. status = ath10k_bmi_done(ar);
  1564. if (status)
  1565. goto err;
  1566. status = ath10k_wmi_attach(ar);
  1567. if (status) {
  1568. ath10k_err(ar, "WMI attach failed: %d\n", status);
  1569. goto err;
  1570. }
  1571. status = ath10k_htt_init(ar);
  1572. if (status) {
  1573. ath10k_err(ar, "failed to init htt: %d\n", status);
  1574. goto err_wmi_detach;
  1575. }
  1576. status = ath10k_htt_tx_alloc(&ar->htt);
  1577. if (status) {
  1578. ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
  1579. goto err_wmi_detach;
  1580. }
  1581. /* If firmware indicates Full Rx Reorder support it must be used in a
  1582. * slightly different manner. Let HTT code know.
  1583. */
  1584. ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
  1585. ar->wmi.svc_map));
  1586. status = ath10k_htt_rx_alloc(&ar->htt);
  1587. if (status) {
  1588. ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
  1589. goto err_htt_tx_detach;
  1590. }
  1591. status = ath10k_hif_start(ar);
  1592. if (status) {
  1593. ath10k_err(ar, "could not start HIF: %d\n", status);
  1594. goto err_htt_rx_detach;
  1595. }
  1596. status = ath10k_htc_wait_target(&ar->htc);
  1597. if (status) {
  1598. ath10k_err(ar, "failed to connect to HTC: %d\n", status);
  1599. goto err_hif_stop;
  1600. }
  1601. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1602. status = ath10k_htt_connect(&ar->htt);
  1603. if (status) {
  1604. ath10k_err(ar, "failed to connect htt (%d)\n", status);
  1605. goto err_hif_stop;
  1606. }
  1607. }
  1608. status = ath10k_wmi_connect(ar);
  1609. if (status) {
  1610. ath10k_err(ar, "could not connect wmi: %d\n", status);
  1611. goto err_hif_stop;
  1612. }
  1613. status = ath10k_htc_start(&ar->htc);
  1614. if (status) {
  1615. ath10k_err(ar, "failed to start htc: %d\n", status);
  1616. goto err_hif_stop;
  1617. }
  1618. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1619. status = ath10k_wmi_wait_for_service_ready(ar);
  1620. if (status) {
  1621. ath10k_warn(ar, "wmi service ready event not received");
  1622. goto err_hif_stop;
  1623. }
  1624. }
  1625. ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
  1626. ar->hw->wiphy->fw_version);
  1627. if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) &&
  1628. mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1629. val = 0;
  1630. if (ath10k_peer_stats_enabled(ar))
  1631. val = WMI_10_4_PEER_STATS;
  1632. if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map))
  1633. val |= WMI_10_4_BSS_CHANNEL_INFO_64;
  1634. /* 10.4 firmware supports BT-Coex without reloading firmware
  1635. * via pdev param. To support Bluetooth coexistence pdev param,
  1636. * WMI_COEX_GPIO_SUPPORT of extended resource config should be
  1637. * enabled always.
  1638. */
  1639. if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) &&
  1640. test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM,
  1641. ar->running_fw->fw_file.fw_features))
  1642. val |= WMI_10_4_COEX_GPIO_SUPPORT;
  1643. status = ath10k_mac_ext_resource_config(ar, val);
  1644. if (status) {
  1645. ath10k_err(ar,
  1646. "failed to send ext resource cfg command : %d\n",
  1647. status);
  1648. goto err_hif_stop;
  1649. }
  1650. }
  1651. status = ath10k_wmi_cmd_init(ar);
  1652. if (status) {
  1653. ath10k_err(ar, "could not send WMI init command (%d)\n",
  1654. status);
  1655. goto err_hif_stop;
  1656. }
  1657. status = ath10k_wmi_wait_for_unified_ready(ar);
  1658. if (status) {
  1659. ath10k_err(ar, "wmi unified ready event not received\n");
  1660. goto err_hif_stop;
  1661. }
  1662. /* Some firmware revisions do not properly set up hardware rx filter
  1663. * registers.
  1664. *
  1665. * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK
  1666. * is filled with 0s instead of 1s allowing HW to respond with ACKs to
  1667. * any frames that matches MAC_PCU_RX_FILTER which is also
  1668. * misconfigured to accept anything.
  1669. *
  1670. * The ADDR1 is programmed using internal firmware structure field and
  1671. * can't be (easily/sanely) reached from the driver explicitly. It is
  1672. * possible to implicitly make it correct by creating a dummy vdev and
  1673. * then deleting it.
  1674. */
  1675. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1676. status = ath10k_core_reset_rx_filter(ar);
  1677. if (status) {
  1678. ath10k_err(ar,
  1679. "failed to reset rx filter: %d\n", status);
  1680. goto err_hif_stop;
  1681. }
  1682. }
  1683. status = ath10k_htt_rx_ring_refill(ar);
  1684. if (status) {
  1685. ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
  1686. goto err_hif_stop;
  1687. }
  1688. if (ar->max_num_vdevs >= 64)
  1689. ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL;
  1690. else
  1691. ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
  1692. INIT_LIST_HEAD(&ar->arvifs);
  1693. /* we don't care about HTT in UTF mode */
  1694. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1695. status = ath10k_htt_setup(&ar->htt);
  1696. if (status) {
  1697. ath10k_err(ar, "failed to setup htt: %d\n", status);
  1698. goto err_hif_stop;
  1699. }
  1700. }
  1701. status = ath10k_debug_start(ar);
  1702. if (status)
  1703. goto err_hif_stop;
  1704. return 0;
  1705. err_hif_stop:
  1706. ath10k_hif_stop(ar);
  1707. err_htt_rx_detach:
  1708. ath10k_htt_rx_free(&ar->htt);
  1709. err_htt_tx_detach:
  1710. ath10k_htt_tx_free(&ar->htt);
  1711. err_wmi_detach:
  1712. ath10k_wmi_detach(ar);
  1713. err:
  1714. return status;
  1715. }
  1716. EXPORT_SYMBOL(ath10k_core_start);
  1717. int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
  1718. {
  1719. int ret;
  1720. unsigned long time_left;
  1721. reinit_completion(&ar->target_suspend);
  1722. ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
  1723. if (ret) {
  1724. ath10k_warn(ar, "could not suspend target (%d)\n", ret);
  1725. return ret;
  1726. }
  1727. time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
  1728. if (!time_left) {
  1729. ath10k_warn(ar, "suspend timed out - target pause event never came\n");
  1730. return -ETIMEDOUT;
  1731. }
  1732. return 0;
  1733. }
  1734. void ath10k_core_stop(struct ath10k *ar)
  1735. {
  1736. lockdep_assert_held(&ar->conf_mutex);
  1737. ath10k_debug_stop(ar);
  1738. /* try to suspend target */
  1739. if (ar->state != ATH10K_STATE_RESTARTING &&
  1740. ar->state != ATH10K_STATE_UTF)
  1741. ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
  1742. ath10k_hif_stop(ar);
  1743. ath10k_htt_tx_free(&ar->htt);
  1744. ath10k_htt_rx_free(&ar->htt);
  1745. ath10k_wmi_detach(ar);
  1746. }
  1747. EXPORT_SYMBOL(ath10k_core_stop);
  1748. /* mac80211 manages fw/hw initialization through start/stop hooks. However in
  1749. * order to know what hw capabilities should be advertised to mac80211 it is
  1750. * necessary to load the firmware (and tear it down immediately since start
  1751. * hook will try to init it again) before registering */
  1752. static int ath10k_core_probe_fw(struct ath10k *ar)
  1753. {
  1754. struct bmi_target_info target_info;
  1755. int ret = 0;
  1756. ret = ath10k_hif_power_up(ar);
  1757. if (ret) {
  1758. ath10k_err(ar, "could not start pci hif (%d)\n", ret);
  1759. return ret;
  1760. }
  1761. memset(&target_info, 0, sizeof(target_info));
  1762. ret = ath10k_bmi_get_target_info(ar, &target_info);
  1763. if (ret) {
  1764. ath10k_err(ar, "could not get target info (%d)\n", ret);
  1765. goto err_power_down;
  1766. }
  1767. ar->target_version = target_info.version;
  1768. ar->hw->wiphy->hw_version = target_info.version;
  1769. ret = ath10k_init_hw_params(ar);
  1770. if (ret) {
  1771. ath10k_err(ar, "could not get hw params (%d)\n", ret);
  1772. goto err_power_down;
  1773. }
  1774. ret = ath10k_core_fetch_firmware_files(ar);
  1775. if (ret) {
  1776. ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
  1777. goto err_power_down;
  1778. }
  1779. BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) !=
  1780. sizeof(ar->normal_mode_fw.fw_file.fw_version));
  1781. memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version,
  1782. sizeof(ar->hw->wiphy->fw_version));
  1783. ath10k_debug_print_hwfw_info(ar);
  1784. ret = ath10k_core_pre_cal_download(ar);
  1785. if (ret) {
  1786. /* pre calibration data download is not necessary
  1787. * for all the chipsets. Ignore failures and continue.
  1788. */
  1789. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1790. "could not load pre cal data: %d\n", ret);
  1791. }
  1792. ret = ath10k_core_get_board_id_from_otp(ar);
  1793. if (ret && ret != -EOPNOTSUPP) {
  1794. ath10k_err(ar, "failed to get board id from otp: %d\n",
  1795. ret);
  1796. goto err_free_firmware_files;
  1797. }
  1798. ret = ath10k_core_fetch_board_file(ar);
  1799. if (ret) {
  1800. ath10k_err(ar, "failed to fetch board file: %d\n", ret);
  1801. goto err_free_firmware_files;
  1802. }
  1803. ath10k_debug_print_board_info(ar);
  1804. ret = ath10k_core_init_firmware_features(ar);
  1805. if (ret) {
  1806. ath10k_err(ar, "fatal problem with firmware features: %d\n",
  1807. ret);
  1808. goto err_free_firmware_files;
  1809. }
  1810. ret = ath10k_swap_code_seg_init(ar, &ar->normal_mode_fw.fw_file);
  1811. if (ret) {
  1812. ath10k_err(ar, "failed to initialize code swap segment: %d\n",
  1813. ret);
  1814. goto err_free_firmware_files;
  1815. }
  1816. mutex_lock(&ar->conf_mutex);
  1817. ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL,
  1818. &ar->normal_mode_fw);
  1819. if (ret) {
  1820. ath10k_err(ar, "could not init core (%d)\n", ret);
  1821. goto err_unlock;
  1822. }
  1823. ath10k_debug_print_boot_info(ar);
  1824. ath10k_core_stop(ar);
  1825. mutex_unlock(&ar->conf_mutex);
  1826. ath10k_hif_power_down(ar);
  1827. return 0;
  1828. err_unlock:
  1829. mutex_unlock(&ar->conf_mutex);
  1830. err_free_firmware_files:
  1831. ath10k_core_free_firmware_files(ar);
  1832. err_power_down:
  1833. ath10k_hif_power_down(ar);
  1834. return ret;
  1835. }
  1836. static void ath10k_core_register_work(struct work_struct *work)
  1837. {
  1838. struct ath10k *ar = container_of(work, struct ath10k, register_work);
  1839. int status;
  1840. /* peer stats are enabled by default */
  1841. set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags);
  1842. status = ath10k_core_probe_fw(ar);
  1843. if (status) {
  1844. ath10k_err(ar, "could not probe fw (%d)\n", status);
  1845. goto err;
  1846. }
  1847. status = ath10k_mac_register(ar);
  1848. if (status) {
  1849. ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
  1850. goto err_release_fw;
  1851. }
  1852. status = ath10k_debug_register(ar);
  1853. if (status) {
  1854. ath10k_err(ar, "unable to initialize debugfs\n");
  1855. goto err_unregister_mac;
  1856. }
  1857. status = ath10k_spectral_create(ar);
  1858. if (status) {
  1859. ath10k_err(ar, "failed to initialize spectral\n");
  1860. goto err_debug_destroy;
  1861. }
  1862. status = ath10k_thermal_register(ar);
  1863. if (status) {
  1864. ath10k_err(ar, "could not register thermal device: %d\n",
  1865. status);
  1866. goto err_spectral_destroy;
  1867. }
  1868. set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
  1869. return;
  1870. err_spectral_destroy:
  1871. ath10k_spectral_destroy(ar);
  1872. err_debug_destroy:
  1873. ath10k_debug_destroy(ar);
  1874. err_unregister_mac:
  1875. ath10k_mac_unregister(ar);
  1876. err_release_fw:
  1877. ath10k_core_free_firmware_files(ar);
  1878. err:
  1879. /* TODO: It's probably a good idea to release device from the driver
  1880. * but calling device_release_driver() here will cause a deadlock.
  1881. */
  1882. return;
  1883. }
  1884. int ath10k_core_register(struct ath10k *ar, u32 chip_id)
  1885. {
  1886. ar->chip_id = chip_id;
  1887. queue_work(ar->workqueue, &ar->register_work);
  1888. return 0;
  1889. }
  1890. EXPORT_SYMBOL(ath10k_core_register);
  1891. void ath10k_core_unregister(struct ath10k *ar)
  1892. {
  1893. cancel_work_sync(&ar->register_work);
  1894. if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
  1895. return;
  1896. ath10k_thermal_unregister(ar);
  1897. /* Stop spectral before unregistering from mac80211 to remove the
  1898. * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
  1899. * would be already be free'd recursively, leading to a double free.
  1900. */
  1901. ath10k_spectral_destroy(ar);
  1902. /* We must unregister from mac80211 before we stop HTC and HIF.
  1903. * Otherwise we will fail to submit commands to FW and mac80211 will be
  1904. * unhappy about callback failures. */
  1905. ath10k_mac_unregister(ar);
  1906. ath10k_testmode_destroy(ar);
  1907. ath10k_core_free_firmware_files(ar);
  1908. ath10k_core_free_board_files(ar);
  1909. ath10k_debug_unregister(ar);
  1910. }
  1911. EXPORT_SYMBOL(ath10k_core_unregister);
  1912. struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
  1913. enum ath10k_bus bus,
  1914. enum ath10k_hw_rev hw_rev,
  1915. const struct ath10k_hif_ops *hif_ops)
  1916. {
  1917. struct ath10k *ar;
  1918. int ret;
  1919. ar = ath10k_mac_create(priv_size);
  1920. if (!ar)
  1921. return NULL;
  1922. ar->ath_common.priv = ar;
  1923. ar->ath_common.hw = ar->hw;
  1924. ar->dev = dev;
  1925. ar->hw_rev = hw_rev;
  1926. ar->hif.ops = hif_ops;
  1927. ar->hif.bus = bus;
  1928. switch (hw_rev) {
  1929. case ATH10K_HW_QCA988X:
  1930. case ATH10K_HW_QCA9887:
  1931. ar->regs = &qca988x_regs;
  1932. ar->hw_values = &qca988x_values;
  1933. break;
  1934. case ATH10K_HW_QCA6174:
  1935. case ATH10K_HW_QCA9377:
  1936. ar->regs = &qca6174_regs;
  1937. ar->hw_values = &qca6174_values;
  1938. break;
  1939. case ATH10K_HW_QCA99X0:
  1940. case ATH10K_HW_QCA9984:
  1941. ar->regs = &qca99x0_regs;
  1942. ar->hw_values = &qca99x0_values;
  1943. break;
  1944. case ATH10K_HW_QCA9888:
  1945. ar->regs = &qca99x0_regs;
  1946. ar->hw_values = &qca9888_values;
  1947. break;
  1948. case ATH10K_HW_QCA4019:
  1949. ar->regs = &qca4019_regs;
  1950. ar->hw_values = &qca4019_values;
  1951. break;
  1952. default:
  1953. ath10k_err(ar, "unsupported core hardware revision %d\n",
  1954. hw_rev);
  1955. ret = -ENOTSUPP;
  1956. goto err_free_mac;
  1957. }
  1958. init_completion(&ar->scan.started);
  1959. init_completion(&ar->scan.completed);
  1960. init_completion(&ar->scan.on_channel);
  1961. init_completion(&ar->target_suspend);
  1962. init_completion(&ar->wow.wakeup_completed);
  1963. init_completion(&ar->install_key_done);
  1964. init_completion(&ar->vdev_setup_done);
  1965. init_completion(&ar->thermal.wmi_sync);
  1966. init_completion(&ar->bss_survey_done);
  1967. INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
  1968. ar->workqueue = create_singlethread_workqueue("ath10k_wq");
  1969. if (!ar->workqueue)
  1970. goto err_free_mac;
  1971. ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
  1972. if (!ar->workqueue_aux)
  1973. goto err_free_wq;
  1974. mutex_init(&ar->conf_mutex);
  1975. spin_lock_init(&ar->data_lock);
  1976. spin_lock_init(&ar->txqs_lock);
  1977. INIT_LIST_HEAD(&ar->txqs);
  1978. INIT_LIST_HEAD(&ar->peers);
  1979. init_waitqueue_head(&ar->peer_mapping_wq);
  1980. init_waitqueue_head(&ar->htt.empty_tx_wq);
  1981. init_waitqueue_head(&ar->wmi.tx_credits_wq);
  1982. init_completion(&ar->offchan_tx_completed);
  1983. INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
  1984. skb_queue_head_init(&ar->offchan_tx_queue);
  1985. INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
  1986. skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
  1987. INIT_WORK(&ar->register_work, ath10k_core_register_work);
  1988. INIT_WORK(&ar->restart_work, ath10k_core_restart);
  1989. init_dummy_netdev(&ar->napi_dev);
  1990. ret = ath10k_debug_create(ar);
  1991. if (ret)
  1992. goto err_free_aux_wq;
  1993. return ar;
  1994. err_free_aux_wq:
  1995. destroy_workqueue(ar->workqueue_aux);
  1996. err_free_wq:
  1997. destroy_workqueue(ar->workqueue);
  1998. err_free_mac:
  1999. ath10k_mac_destroy(ar);
  2000. return NULL;
  2001. }
  2002. EXPORT_SYMBOL(ath10k_core_create);
  2003. void ath10k_core_destroy(struct ath10k *ar)
  2004. {
  2005. flush_workqueue(ar->workqueue);
  2006. destroy_workqueue(ar->workqueue);
  2007. flush_workqueue(ar->workqueue_aux);
  2008. destroy_workqueue(ar->workqueue_aux);
  2009. ath10k_debug_destroy(ar);
  2010. ath10k_wmi_free_host_mem(ar);
  2011. ath10k_mac_destroy(ar);
  2012. }
  2013. EXPORT_SYMBOL(ath10k_core_destroy);
  2014. MODULE_AUTHOR("Qualcomm Atheros");
  2015. MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards.");
  2016. MODULE_LICENSE("Dual BSD/GPL");