r8152.c 104 KB

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  1. /*
  2. * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/signal.h>
  10. #include <linux/slab.h>
  11. #include <linux/module.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/mii.h>
  15. #include <linux/ethtool.h>
  16. #include <linux/usb.h>
  17. #include <linux/crc32.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/list.h>
  21. #include <linux/ip.h>
  22. #include <linux/ipv6.h>
  23. #include <net/ip6_checksum.h>
  24. #include <uapi/linux/mdio.h>
  25. #include <linux/mdio.h>
  26. #include <linux/usb/cdc.h>
  27. #include <linux/suspend.h>
  28. #include <linux/acpi.h>
  29. /* Information for net-next */
  30. #define NETNEXT_VERSION "08"
  31. /* Information for net */
  32. #define NET_VERSION "9"
  33. #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
  34. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  35. #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  36. #define MODULENAME "r8152"
  37. #define R8152_PHY_ID 32
  38. #define PLA_IDR 0xc000
  39. #define PLA_RCR 0xc010
  40. #define PLA_RMS 0xc016
  41. #define PLA_RXFIFO_CTRL0 0xc0a0
  42. #define PLA_RXFIFO_CTRL1 0xc0a4
  43. #define PLA_RXFIFO_CTRL2 0xc0a8
  44. #define PLA_DMY_REG0 0xc0b0
  45. #define PLA_FMC 0xc0b4
  46. #define PLA_CFG_WOL 0xc0b6
  47. #define PLA_TEREDO_CFG 0xc0bc
  48. #define PLA_MAR 0xcd00
  49. #define PLA_BACKUP 0xd000
  50. #define PAL_BDC_CR 0xd1a0
  51. #define PLA_TEREDO_TIMER 0xd2cc
  52. #define PLA_REALWOW_TIMER 0xd2e8
  53. #define PLA_LEDSEL 0xdd90
  54. #define PLA_LED_FEATURE 0xdd92
  55. #define PLA_PHYAR 0xde00
  56. #define PLA_BOOT_CTRL 0xe004
  57. #define PLA_GPHY_INTR_IMR 0xe022
  58. #define PLA_EEE_CR 0xe040
  59. #define PLA_EEEP_CR 0xe080
  60. #define PLA_MAC_PWR_CTRL 0xe0c0
  61. #define PLA_MAC_PWR_CTRL2 0xe0ca
  62. #define PLA_MAC_PWR_CTRL3 0xe0cc
  63. #define PLA_MAC_PWR_CTRL4 0xe0ce
  64. #define PLA_WDT6_CTRL 0xe428
  65. #define PLA_TCR0 0xe610
  66. #define PLA_TCR1 0xe612
  67. #define PLA_MTPS 0xe615
  68. #define PLA_TXFIFO_CTRL 0xe618
  69. #define PLA_RSTTALLY 0xe800
  70. #define PLA_CR 0xe813
  71. #define PLA_CRWECR 0xe81c
  72. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  73. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  74. #define PLA_CONFIG5 0xe822
  75. #define PLA_PHY_PWR 0xe84c
  76. #define PLA_OOB_CTRL 0xe84f
  77. #define PLA_CPCR 0xe854
  78. #define PLA_MISC_0 0xe858
  79. #define PLA_MISC_1 0xe85a
  80. #define PLA_OCP_GPHY_BASE 0xe86c
  81. #define PLA_TALLYCNT 0xe890
  82. #define PLA_SFF_STS_7 0xe8de
  83. #define PLA_PHYSTATUS 0xe908
  84. #define PLA_BP_BA 0xfc26
  85. #define PLA_BP_0 0xfc28
  86. #define PLA_BP_1 0xfc2a
  87. #define PLA_BP_2 0xfc2c
  88. #define PLA_BP_3 0xfc2e
  89. #define PLA_BP_4 0xfc30
  90. #define PLA_BP_5 0xfc32
  91. #define PLA_BP_6 0xfc34
  92. #define PLA_BP_7 0xfc36
  93. #define PLA_BP_EN 0xfc38
  94. #define USB_USB2PHY 0xb41e
  95. #define USB_SSPHYLINK2 0xb428
  96. #define USB_U2P3_CTRL 0xb460
  97. #define USB_CSR_DUMMY1 0xb464
  98. #define USB_CSR_DUMMY2 0xb466
  99. #define USB_DEV_STAT 0xb808
  100. #define USB_CONNECT_TIMER 0xcbf8
  101. #define USB_BURST_SIZE 0xcfc0
  102. #define USB_USB_CTRL 0xd406
  103. #define USB_PHY_CTRL 0xd408
  104. #define USB_TX_AGG 0xd40a
  105. #define USB_RX_BUF_TH 0xd40c
  106. #define USB_USB_TIMER 0xd428
  107. #define USB_RX_EARLY_TIMEOUT 0xd42c
  108. #define USB_RX_EARLY_SIZE 0xd42e
  109. #define USB_PM_CTRL_STATUS 0xd432
  110. #define USB_TX_DMA 0xd434
  111. #define USB_TOLERANCE 0xd490
  112. #define USB_LPM_CTRL 0xd41a
  113. #define USB_BMU_RESET 0xd4b0
  114. #define USB_UPS_CTRL 0xd800
  115. #define USB_MISC_0 0xd81a
  116. #define USB_POWER_CUT 0xd80a
  117. #define USB_AFE_CTRL2 0xd824
  118. #define USB_WDT11_CTRL 0xe43c
  119. #define USB_BP_BA 0xfc26
  120. #define USB_BP_0 0xfc28
  121. #define USB_BP_1 0xfc2a
  122. #define USB_BP_2 0xfc2c
  123. #define USB_BP_3 0xfc2e
  124. #define USB_BP_4 0xfc30
  125. #define USB_BP_5 0xfc32
  126. #define USB_BP_6 0xfc34
  127. #define USB_BP_7 0xfc36
  128. #define USB_BP_EN 0xfc38
  129. /* OCP Registers */
  130. #define OCP_ALDPS_CONFIG 0x2010
  131. #define OCP_EEE_CONFIG1 0x2080
  132. #define OCP_EEE_CONFIG2 0x2092
  133. #define OCP_EEE_CONFIG3 0x2094
  134. #define OCP_BASE_MII 0xa400
  135. #define OCP_EEE_AR 0xa41a
  136. #define OCP_EEE_DATA 0xa41c
  137. #define OCP_PHY_STATUS 0xa420
  138. #define OCP_POWER_CFG 0xa430
  139. #define OCP_EEE_CFG 0xa432
  140. #define OCP_SRAM_ADDR 0xa436
  141. #define OCP_SRAM_DATA 0xa438
  142. #define OCP_DOWN_SPEED 0xa442
  143. #define OCP_EEE_ABLE 0xa5c4
  144. #define OCP_EEE_ADV 0xa5d0
  145. #define OCP_EEE_LPABLE 0xa5d2
  146. #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
  147. #define OCP_ADC_CFG 0xbc06
  148. /* SRAM Register */
  149. #define SRAM_LPF_CFG 0x8012
  150. #define SRAM_10M_AMP1 0x8080
  151. #define SRAM_10M_AMP2 0x8082
  152. #define SRAM_IMPEDANCE 0x8084
  153. /* PLA_RCR */
  154. #define RCR_AAP 0x00000001
  155. #define RCR_APM 0x00000002
  156. #define RCR_AM 0x00000004
  157. #define RCR_AB 0x00000008
  158. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  159. /* PLA_RXFIFO_CTRL0 */
  160. #define RXFIFO_THR1_NORMAL 0x00080002
  161. #define RXFIFO_THR1_OOB 0x01800003
  162. /* PLA_RXFIFO_CTRL1 */
  163. #define RXFIFO_THR2_FULL 0x00000060
  164. #define RXFIFO_THR2_HIGH 0x00000038
  165. #define RXFIFO_THR2_OOB 0x0000004a
  166. #define RXFIFO_THR2_NORMAL 0x00a0
  167. /* PLA_RXFIFO_CTRL2 */
  168. #define RXFIFO_THR3_FULL 0x00000078
  169. #define RXFIFO_THR3_HIGH 0x00000048
  170. #define RXFIFO_THR3_OOB 0x0000005a
  171. #define RXFIFO_THR3_NORMAL 0x0110
  172. /* PLA_TXFIFO_CTRL */
  173. #define TXFIFO_THR_NORMAL 0x00400008
  174. #define TXFIFO_THR_NORMAL2 0x01000008
  175. /* PLA_DMY_REG0 */
  176. #define ECM_ALDPS 0x0002
  177. /* PLA_FMC */
  178. #define FMC_FCR_MCU_EN 0x0001
  179. /* PLA_EEEP_CR */
  180. #define EEEP_CR_EEEP_TX 0x0002
  181. /* PLA_WDT6_CTRL */
  182. #define WDT6_SET_MODE 0x0010
  183. /* PLA_TCR0 */
  184. #define TCR0_TX_EMPTY 0x0800
  185. #define TCR0_AUTO_FIFO 0x0080
  186. /* PLA_TCR1 */
  187. #define VERSION_MASK 0x7cf0
  188. /* PLA_MTPS */
  189. #define MTPS_JUMBO (12 * 1024 / 64)
  190. #define MTPS_DEFAULT (6 * 1024 / 64)
  191. /* PLA_RSTTALLY */
  192. #define TALLY_RESET 0x0001
  193. /* PLA_CR */
  194. #define CR_RST 0x10
  195. #define CR_RE 0x08
  196. #define CR_TE 0x04
  197. /* PLA_CRWECR */
  198. #define CRWECR_NORAML 0x00
  199. #define CRWECR_CONFIG 0xc0
  200. /* PLA_OOB_CTRL */
  201. #define NOW_IS_OOB 0x80
  202. #define TXFIFO_EMPTY 0x20
  203. #define RXFIFO_EMPTY 0x10
  204. #define LINK_LIST_READY 0x02
  205. #define DIS_MCU_CLROOB 0x01
  206. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  207. /* PLA_MISC_1 */
  208. #define RXDY_GATED_EN 0x0008
  209. /* PLA_SFF_STS_7 */
  210. #define RE_INIT_LL 0x8000
  211. #define MCU_BORW_EN 0x4000
  212. /* PLA_CPCR */
  213. #define CPCR_RX_VLAN 0x0040
  214. /* PLA_CFG_WOL */
  215. #define MAGIC_EN 0x0001
  216. /* PLA_TEREDO_CFG */
  217. #define TEREDO_SEL 0x8000
  218. #define TEREDO_WAKE_MASK 0x7f00
  219. #define TEREDO_RS_EVENT_MASK 0x00fe
  220. #define OOB_TEREDO_EN 0x0001
  221. /* PAL_BDC_CR */
  222. #define ALDPS_PROXY_MODE 0x0001
  223. /* PLA_CONFIG34 */
  224. #define LINK_ON_WAKE_EN 0x0010
  225. #define LINK_OFF_WAKE_EN 0x0008
  226. /* PLA_CONFIG5 */
  227. #define BWF_EN 0x0040
  228. #define MWF_EN 0x0020
  229. #define UWF_EN 0x0010
  230. #define LAN_WAKE_EN 0x0002
  231. /* PLA_LED_FEATURE */
  232. #define LED_MODE_MASK 0x0700
  233. /* PLA_PHY_PWR */
  234. #define TX_10M_IDLE_EN 0x0080
  235. #define PFM_PWM_SWITCH 0x0040
  236. /* PLA_MAC_PWR_CTRL */
  237. #define D3_CLK_GATED_EN 0x00004000
  238. #define MCU_CLK_RATIO 0x07010f07
  239. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  240. #define ALDPS_SPDWN_RATIO 0x0f87
  241. /* PLA_MAC_PWR_CTRL2 */
  242. #define EEE_SPDWN_RATIO 0x8007
  243. /* PLA_MAC_PWR_CTRL3 */
  244. #define PKT_AVAIL_SPDWN_EN 0x0100
  245. #define SUSPEND_SPDWN_EN 0x0004
  246. #define U1U2_SPDWN_EN 0x0002
  247. #define L1_SPDWN_EN 0x0001
  248. /* PLA_MAC_PWR_CTRL4 */
  249. #define PWRSAVE_SPDWN_EN 0x1000
  250. #define RXDV_SPDWN_EN 0x0800
  251. #define TX10MIDLE_EN 0x0100
  252. #define TP100_SPDWN_EN 0x0020
  253. #define TP500_SPDWN_EN 0x0010
  254. #define TP1000_SPDWN_EN 0x0008
  255. #define EEE_SPDWN_EN 0x0001
  256. /* PLA_GPHY_INTR_IMR */
  257. #define GPHY_STS_MSK 0x0001
  258. #define SPEED_DOWN_MSK 0x0002
  259. #define SPDWN_RXDV_MSK 0x0004
  260. #define SPDWN_LINKCHG_MSK 0x0008
  261. /* PLA_PHYAR */
  262. #define PHYAR_FLAG 0x80000000
  263. /* PLA_EEE_CR */
  264. #define EEE_RX_EN 0x0001
  265. #define EEE_TX_EN 0x0002
  266. /* PLA_BOOT_CTRL */
  267. #define AUTOLOAD_DONE 0x0002
  268. /* USB_USB2PHY */
  269. #define USB2PHY_SUSPEND 0x0001
  270. #define USB2PHY_L1 0x0002
  271. /* USB_SSPHYLINK2 */
  272. #define pwd_dn_scale_mask 0x3ffe
  273. #define pwd_dn_scale(x) ((x) << 1)
  274. /* USB_CSR_DUMMY1 */
  275. #define DYNAMIC_BURST 0x0001
  276. /* USB_CSR_DUMMY2 */
  277. #define EP4_FULL_FC 0x0001
  278. /* USB_DEV_STAT */
  279. #define STAT_SPEED_MASK 0x0006
  280. #define STAT_SPEED_HIGH 0x0000
  281. #define STAT_SPEED_FULL 0x0002
  282. /* USB_TX_AGG */
  283. #define TX_AGG_MAX_THRESHOLD 0x03
  284. /* USB_RX_BUF_TH */
  285. #define RX_THR_SUPPER 0x0c350180
  286. #define RX_THR_HIGH 0x7a120180
  287. #define RX_THR_SLOW 0xffff0180
  288. /* USB_TX_DMA */
  289. #define TEST_MODE_DISABLE 0x00000001
  290. #define TX_SIZE_ADJUST1 0x00000100
  291. /* USB_BMU_RESET */
  292. #define BMU_RESET_EP_IN 0x01
  293. #define BMU_RESET_EP_OUT 0x02
  294. /* USB_UPS_CTRL */
  295. #define POWER_CUT 0x0100
  296. /* USB_PM_CTRL_STATUS */
  297. #define RESUME_INDICATE 0x0001
  298. /* USB_USB_CTRL */
  299. #define RX_AGG_DISABLE 0x0010
  300. #define RX_ZERO_EN 0x0080
  301. /* USB_U2P3_CTRL */
  302. #define U2P3_ENABLE 0x0001
  303. /* USB_POWER_CUT */
  304. #define PWR_EN 0x0001
  305. #define PHASE2_EN 0x0008
  306. /* USB_MISC_0 */
  307. #define PCUT_STATUS 0x0001
  308. /* USB_RX_EARLY_TIMEOUT */
  309. #define COALESCE_SUPER 85000U
  310. #define COALESCE_HIGH 250000U
  311. #define COALESCE_SLOW 524280U
  312. /* USB_WDT11_CTRL */
  313. #define TIMER11_EN 0x0001
  314. /* USB_LPM_CTRL */
  315. /* bit 4 ~ 5: fifo empty boundary */
  316. #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
  317. /* bit 2 ~ 3: LMP timer */
  318. #define LPM_TIMER_MASK 0x0c
  319. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  320. #define LPM_TIMER_500US 0x0c /* 500 us */
  321. #define ROK_EXIT_LPM 0x02
  322. /* USB_AFE_CTRL2 */
  323. #define SEN_VAL_MASK 0xf800
  324. #define SEN_VAL_NORMAL 0xa000
  325. #define SEL_RXIDLE 0x0100
  326. /* OCP_ALDPS_CONFIG */
  327. #define ENPWRSAVE 0x8000
  328. #define ENPDNPS 0x0200
  329. #define LINKENA 0x0100
  330. #define DIS_SDSAVE 0x0010
  331. /* OCP_PHY_STATUS */
  332. #define PHY_STAT_MASK 0x0007
  333. #define PHY_STAT_LAN_ON 3
  334. #define PHY_STAT_PWRDN 5
  335. /* OCP_POWER_CFG */
  336. #define EEE_CLKDIV_EN 0x8000
  337. #define EN_ALDPS 0x0004
  338. #define EN_10M_PLLOFF 0x0001
  339. /* OCP_EEE_CONFIG1 */
  340. #define RG_TXLPI_MSK_HFDUP 0x8000
  341. #define RG_MATCLR_EN 0x4000
  342. #define EEE_10_CAP 0x2000
  343. #define EEE_NWAY_EN 0x1000
  344. #define TX_QUIET_EN 0x0200
  345. #define RX_QUIET_EN 0x0100
  346. #define sd_rise_time_mask 0x0070
  347. #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
  348. #define RG_RXLPI_MSK_HFDUP 0x0008
  349. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  350. /* OCP_EEE_CONFIG2 */
  351. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  352. #define RG_DACQUIET_EN 0x0400
  353. #define RG_LDVQUIET_EN 0x0200
  354. #define RG_CKRSEL 0x0020
  355. #define RG_EEEPRG_EN 0x0010
  356. /* OCP_EEE_CONFIG3 */
  357. #define fast_snr_mask 0xff80
  358. #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  359. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  360. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  361. /* OCP_EEE_AR */
  362. /* bit[15:14] function */
  363. #define FUN_ADDR 0x0000
  364. #define FUN_DATA 0x4000
  365. /* bit[4:0] device addr */
  366. /* OCP_EEE_CFG */
  367. #define CTAP_SHORT_EN 0x0040
  368. #define EEE10_EN 0x0010
  369. /* OCP_DOWN_SPEED */
  370. #define EN_10M_BGOFF 0x0080
  371. /* OCP_PHY_STATE */
  372. #define TXDIS_STATE 0x01
  373. #define ABD_STATE 0x02
  374. /* OCP_ADC_CFG */
  375. #define CKADSEL_L 0x0100
  376. #define ADC_EN 0x0080
  377. #define EN_EMI_L 0x0040
  378. /* SRAM_LPF_CFG */
  379. #define LPF_AUTO_TUNE 0x8000
  380. /* SRAM_10M_AMP1 */
  381. #define GDAC_IB_UPALL 0x0008
  382. /* SRAM_10M_AMP2 */
  383. #define AMP_DN 0x0200
  384. /* SRAM_IMPEDANCE */
  385. #define RX_DRIVING_MASK 0x6000
  386. /* MAC PASSTHRU */
  387. #define AD_MASK 0xfee0
  388. #define EFUSE 0xcfdb
  389. #define PASS_THRU_MASK 0x1
  390. enum rtl_register_content {
  391. _1000bps = 0x10,
  392. _100bps = 0x08,
  393. _10bps = 0x04,
  394. LINK_STATUS = 0x02,
  395. FULL_DUP = 0x01,
  396. };
  397. #define RTL8152_MAX_TX 4
  398. #define RTL8152_MAX_RX 10
  399. #define INTBUFSIZE 2
  400. #define CRC_SIZE 4
  401. #define TX_ALIGN 4
  402. #define RX_ALIGN 8
  403. #define INTR_LINK 0x0004
  404. #define RTL8152_REQT_READ 0xc0
  405. #define RTL8152_REQT_WRITE 0x40
  406. #define RTL8152_REQ_GET_REGS 0x05
  407. #define RTL8152_REQ_SET_REGS 0x05
  408. #define BYTE_EN_DWORD 0xff
  409. #define BYTE_EN_WORD 0x33
  410. #define BYTE_EN_BYTE 0x11
  411. #define BYTE_EN_SIX_BYTES 0x3f
  412. #define BYTE_EN_START_MASK 0x0f
  413. #define BYTE_EN_END_MASK 0xf0
  414. #define RTL8153_MAX_PACKET 9216 /* 9K */
  415. #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
  416. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  417. #define RTL8153_RMS RTL8153_MAX_PACKET
  418. #define RTL8152_TX_TIMEOUT (5 * HZ)
  419. #define RTL8152_NAPI_WEIGHT 64
  420. #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + CRC_SIZE + \
  421. sizeof(struct rx_desc) + RX_ALIGN)
  422. /* rtl8152 flags */
  423. enum rtl8152_flags {
  424. RTL8152_UNPLUG = 0,
  425. RTL8152_SET_RX_MODE,
  426. WORK_ENABLE,
  427. RTL8152_LINK_CHG,
  428. SELECTIVE_SUSPEND,
  429. PHY_RESET,
  430. SCHEDULE_NAPI,
  431. };
  432. /* Define these values to match your device */
  433. #define VENDOR_ID_REALTEK 0x0bda
  434. #define VENDOR_ID_SAMSUNG 0x04e8
  435. #define VENDOR_ID_LENOVO 0x17ef
  436. #define VENDOR_ID_LINKSYS 0x13b1
  437. #define VENDOR_ID_NVIDIA 0x0955
  438. #define MCU_TYPE_PLA 0x0100
  439. #define MCU_TYPE_USB 0x0000
  440. struct tally_counter {
  441. __le64 tx_packets;
  442. __le64 rx_packets;
  443. __le64 tx_errors;
  444. __le32 rx_errors;
  445. __le16 rx_missed;
  446. __le16 align_errors;
  447. __le32 tx_one_collision;
  448. __le32 tx_multi_collision;
  449. __le64 rx_unicast;
  450. __le64 rx_broadcast;
  451. __le32 rx_multicast;
  452. __le16 tx_aborted;
  453. __le16 tx_underrun;
  454. };
  455. struct rx_desc {
  456. __le32 opts1;
  457. #define RX_LEN_MASK 0x7fff
  458. __le32 opts2;
  459. #define RD_UDP_CS BIT(23)
  460. #define RD_TCP_CS BIT(22)
  461. #define RD_IPV6_CS BIT(20)
  462. #define RD_IPV4_CS BIT(19)
  463. __le32 opts3;
  464. #define IPF BIT(23) /* IP checksum fail */
  465. #define UDPF BIT(22) /* UDP checksum fail */
  466. #define TCPF BIT(21) /* TCP checksum fail */
  467. #define RX_VLAN_TAG BIT(16)
  468. __le32 opts4;
  469. __le32 opts5;
  470. __le32 opts6;
  471. };
  472. struct tx_desc {
  473. __le32 opts1;
  474. #define TX_FS BIT(31) /* First segment of a packet */
  475. #define TX_LS BIT(30) /* Final segment of a packet */
  476. #define GTSENDV4 BIT(28)
  477. #define GTSENDV6 BIT(27)
  478. #define GTTCPHO_SHIFT 18
  479. #define GTTCPHO_MAX 0x7fU
  480. #define TX_LEN_MAX 0x3ffffU
  481. __le32 opts2;
  482. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  483. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  484. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  485. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  486. #define MSS_SHIFT 17
  487. #define MSS_MAX 0x7ffU
  488. #define TCPHO_SHIFT 17
  489. #define TCPHO_MAX 0x7ffU
  490. #define TX_VLAN_TAG BIT(16)
  491. };
  492. struct r8152;
  493. struct rx_agg {
  494. struct list_head list;
  495. struct urb *urb;
  496. struct r8152 *context;
  497. void *buffer;
  498. void *head;
  499. };
  500. struct tx_agg {
  501. struct list_head list;
  502. struct urb *urb;
  503. struct r8152 *context;
  504. void *buffer;
  505. void *head;
  506. u32 skb_num;
  507. u32 skb_len;
  508. };
  509. struct r8152 {
  510. unsigned long flags;
  511. struct usb_device *udev;
  512. struct napi_struct napi;
  513. struct usb_interface *intf;
  514. struct net_device *netdev;
  515. struct urb *intr_urb;
  516. struct tx_agg tx_info[RTL8152_MAX_TX];
  517. struct rx_agg rx_info[RTL8152_MAX_RX];
  518. struct list_head rx_done, tx_free;
  519. struct sk_buff_head tx_queue, rx_queue;
  520. spinlock_t rx_lock, tx_lock;
  521. struct delayed_work schedule, hw_phy_work;
  522. struct mii_if_info mii;
  523. struct mutex control; /* use for hw setting */
  524. #ifdef CONFIG_PM_SLEEP
  525. struct notifier_block pm_notifier;
  526. #endif
  527. struct rtl_ops {
  528. void (*init)(struct r8152 *);
  529. int (*enable)(struct r8152 *);
  530. void (*disable)(struct r8152 *);
  531. void (*up)(struct r8152 *);
  532. void (*down)(struct r8152 *);
  533. void (*unload)(struct r8152 *);
  534. int (*eee_get)(struct r8152 *, struct ethtool_eee *);
  535. int (*eee_set)(struct r8152 *, struct ethtool_eee *);
  536. bool (*in_nway)(struct r8152 *);
  537. void (*hw_phy_cfg)(struct r8152 *);
  538. void (*autosuspend_en)(struct r8152 *tp, bool enable);
  539. } rtl_ops;
  540. int intr_interval;
  541. u32 saved_wolopts;
  542. u32 msg_enable;
  543. u32 tx_qlen;
  544. u32 coalesce;
  545. u16 ocp_base;
  546. u16 speed;
  547. u8 *intr_buff;
  548. u8 version;
  549. u8 duplex;
  550. u8 autoneg;
  551. };
  552. enum rtl_version {
  553. RTL_VER_UNKNOWN = 0,
  554. RTL_VER_01,
  555. RTL_VER_02,
  556. RTL_VER_03,
  557. RTL_VER_04,
  558. RTL_VER_05,
  559. RTL_VER_06,
  560. RTL_VER_MAX
  561. };
  562. enum tx_csum_stat {
  563. TX_CSUM_SUCCESS = 0,
  564. TX_CSUM_TSO,
  565. TX_CSUM_NONE
  566. };
  567. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  568. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  569. */
  570. static const int multicast_filter_limit = 32;
  571. static unsigned int agg_buf_sz = 16384;
  572. #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
  573. VLAN_ETH_HLEN - VLAN_HLEN)
  574. static
  575. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  576. {
  577. int ret;
  578. void *tmp;
  579. tmp = kmalloc(size, GFP_KERNEL);
  580. if (!tmp)
  581. return -ENOMEM;
  582. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  583. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  584. value, index, tmp, size, 500);
  585. memcpy(data, tmp, size);
  586. kfree(tmp);
  587. return ret;
  588. }
  589. static
  590. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  591. {
  592. int ret;
  593. void *tmp;
  594. tmp = kmemdup(data, size, GFP_KERNEL);
  595. if (!tmp)
  596. return -ENOMEM;
  597. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  598. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  599. value, index, tmp, size, 500);
  600. kfree(tmp);
  601. return ret;
  602. }
  603. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  604. void *data, u16 type)
  605. {
  606. u16 limit = 64;
  607. int ret = 0;
  608. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  609. return -ENODEV;
  610. /* both size and indix must be 4 bytes align */
  611. if ((size & 3) || !size || (index & 3) || !data)
  612. return -EPERM;
  613. if ((u32)index + (u32)size > 0xffff)
  614. return -EPERM;
  615. while (size) {
  616. if (size > limit) {
  617. ret = get_registers(tp, index, type, limit, data);
  618. if (ret < 0)
  619. break;
  620. index += limit;
  621. data += limit;
  622. size -= limit;
  623. } else {
  624. ret = get_registers(tp, index, type, size, data);
  625. if (ret < 0)
  626. break;
  627. index += size;
  628. data += size;
  629. size = 0;
  630. break;
  631. }
  632. }
  633. if (ret == -ENODEV)
  634. set_bit(RTL8152_UNPLUG, &tp->flags);
  635. return ret;
  636. }
  637. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  638. u16 size, void *data, u16 type)
  639. {
  640. int ret;
  641. u16 byteen_start, byteen_end, byen;
  642. u16 limit = 512;
  643. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  644. return -ENODEV;
  645. /* both size and indix must be 4 bytes align */
  646. if ((size & 3) || !size || (index & 3) || !data)
  647. return -EPERM;
  648. if ((u32)index + (u32)size > 0xffff)
  649. return -EPERM;
  650. byteen_start = byteen & BYTE_EN_START_MASK;
  651. byteen_end = byteen & BYTE_EN_END_MASK;
  652. byen = byteen_start | (byteen_start << 4);
  653. ret = set_registers(tp, index, type | byen, 4, data);
  654. if (ret < 0)
  655. goto error1;
  656. index += 4;
  657. data += 4;
  658. size -= 4;
  659. if (size) {
  660. size -= 4;
  661. while (size) {
  662. if (size > limit) {
  663. ret = set_registers(tp, index,
  664. type | BYTE_EN_DWORD,
  665. limit, data);
  666. if (ret < 0)
  667. goto error1;
  668. index += limit;
  669. data += limit;
  670. size -= limit;
  671. } else {
  672. ret = set_registers(tp, index,
  673. type | BYTE_EN_DWORD,
  674. size, data);
  675. if (ret < 0)
  676. goto error1;
  677. index += size;
  678. data += size;
  679. size = 0;
  680. break;
  681. }
  682. }
  683. byen = byteen_end | (byteen_end >> 4);
  684. ret = set_registers(tp, index, type | byen, 4, data);
  685. if (ret < 0)
  686. goto error1;
  687. }
  688. error1:
  689. if (ret == -ENODEV)
  690. set_bit(RTL8152_UNPLUG, &tp->flags);
  691. return ret;
  692. }
  693. static inline
  694. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  695. {
  696. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  697. }
  698. static inline
  699. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  700. {
  701. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  702. }
  703. static inline
  704. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  705. {
  706. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  707. }
  708. static inline
  709. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  710. {
  711. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  712. }
  713. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  714. {
  715. __le32 data;
  716. generic_ocp_read(tp, index, sizeof(data), &data, type);
  717. return __le32_to_cpu(data);
  718. }
  719. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  720. {
  721. __le32 tmp = __cpu_to_le32(data);
  722. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  723. }
  724. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  725. {
  726. u32 data;
  727. __le32 tmp;
  728. u8 shift = index & 2;
  729. index &= ~3;
  730. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  731. data = __le32_to_cpu(tmp);
  732. data >>= (shift * 8);
  733. data &= 0xffff;
  734. return (u16)data;
  735. }
  736. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  737. {
  738. u32 mask = 0xffff;
  739. __le32 tmp;
  740. u16 byen = BYTE_EN_WORD;
  741. u8 shift = index & 2;
  742. data &= mask;
  743. if (index & 2) {
  744. byen <<= shift;
  745. mask <<= (shift * 8);
  746. data <<= (shift * 8);
  747. index &= ~3;
  748. }
  749. tmp = __cpu_to_le32(data);
  750. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  751. }
  752. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  753. {
  754. u32 data;
  755. __le32 tmp;
  756. u8 shift = index & 3;
  757. index &= ~3;
  758. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  759. data = __le32_to_cpu(tmp);
  760. data >>= (shift * 8);
  761. data &= 0xff;
  762. return (u8)data;
  763. }
  764. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  765. {
  766. u32 mask = 0xff;
  767. __le32 tmp;
  768. u16 byen = BYTE_EN_BYTE;
  769. u8 shift = index & 3;
  770. data &= mask;
  771. if (index & 3) {
  772. byen <<= shift;
  773. mask <<= (shift * 8);
  774. data <<= (shift * 8);
  775. index &= ~3;
  776. }
  777. tmp = __cpu_to_le32(data);
  778. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  779. }
  780. static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  781. {
  782. u16 ocp_base, ocp_index;
  783. ocp_base = addr & 0xf000;
  784. if (ocp_base != tp->ocp_base) {
  785. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  786. tp->ocp_base = ocp_base;
  787. }
  788. ocp_index = (addr & 0x0fff) | 0xb000;
  789. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  790. }
  791. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  792. {
  793. u16 ocp_base, ocp_index;
  794. ocp_base = addr & 0xf000;
  795. if (ocp_base != tp->ocp_base) {
  796. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  797. tp->ocp_base = ocp_base;
  798. }
  799. ocp_index = (addr & 0x0fff) | 0xb000;
  800. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  801. }
  802. static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  803. {
  804. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  805. }
  806. static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  807. {
  808. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  809. }
  810. static void sram_write(struct r8152 *tp, u16 addr, u16 data)
  811. {
  812. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  813. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  814. }
  815. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  816. {
  817. struct r8152 *tp = netdev_priv(netdev);
  818. int ret;
  819. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  820. return -ENODEV;
  821. if (phy_id != R8152_PHY_ID)
  822. return -EINVAL;
  823. ret = r8152_mdio_read(tp, reg);
  824. return ret;
  825. }
  826. static
  827. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  828. {
  829. struct r8152 *tp = netdev_priv(netdev);
  830. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  831. return;
  832. if (phy_id != R8152_PHY_ID)
  833. return;
  834. r8152_mdio_write(tp, reg, val);
  835. }
  836. static int
  837. r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  838. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  839. {
  840. struct r8152 *tp = netdev_priv(netdev);
  841. struct sockaddr *addr = p;
  842. int ret = -EADDRNOTAVAIL;
  843. if (!is_valid_ether_addr(addr->sa_data))
  844. goto out1;
  845. ret = usb_autopm_get_interface(tp->intf);
  846. if (ret < 0)
  847. goto out1;
  848. mutex_lock(&tp->control);
  849. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  850. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  851. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  852. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  853. mutex_unlock(&tp->control);
  854. usb_autopm_put_interface(tp->intf);
  855. out1:
  856. return ret;
  857. }
  858. /* Devices containing RTL8153-AD can support a persistent
  859. * host system provided MAC address.
  860. * Examples of this are Dell TB15 and Dell WD15 docks
  861. */
  862. static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
  863. {
  864. acpi_status status;
  865. struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
  866. union acpi_object *obj;
  867. int ret = -EINVAL;
  868. u32 ocp_data;
  869. unsigned char buf[6];
  870. /* test for -AD variant of RTL8153 */
  871. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  872. if ((ocp_data & AD_MASK) != 0x1000)
  873. return -ENODEV;
  874. /* test for MAC address pass-through bit */
  875. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
  876. if ((ocp_data & PASS_THRU_MASK) != 1)
  877. return -ENODEV;
  878. /* returns _AUXMAC_#AABBCCDDEEFF# */
  879. status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
  880. obj = (union acpi_object *)buffer.pointer;
  881. if (!ACPI_SUCCESS(status))
  882. return -ENODEV;
  883. if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
  884. netif_warn(tp, probe, tp->netdev,
  885. "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
  886. obj->type, obj->string.length);
  887. goto amacout;
  888. }
  889. if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
  890. strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
  891. netif_warn(tp, probe, tp->netdev,
  892. "Invalid header when reading pass-thru MAC addr\n");
  893. goto amacout;
  894. }
  895. ret = hex2bin(buf, obj->string.pointer + 9, 6);
  896. if (!(ret == 0 && is_valid_ether_addr(buf))) {
  897. netif_warn(tp, probe, tp->netdev,
  898. "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
  899. ret, buf);
  900. ret = -EINVAL;
  901. goto amacout;
  902. }
  903. memcpy(sa->sa_data, buf, 6);
  904. ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
  905. netif_info(tp, probe, tp->netdev,
  906. "Using pass-thru MAC addr %pM\n", sa->sa_data);
  907. amacout:
  908. kfree(obj);
  909. return ret;
  910. }
  911. static int set_ethernet_addr(struct r8152 *tp)
  912. {
  913. struct net_device *dev = tp->netdev;
  914. struct sockaddr sa;
  915. int ret;
  916. if (tp->version == RTL_VER_01) {
  917. ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
  918. } else {
  919. /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
  920. * or system doesn't provide valid _SB.AMAC this will be
  921. * be expected to non-zero
  922. */
  923. ret = vendor_mac_passthru_addr_read(tp, &sa);
  924. if (ret < 0)
  925. ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
  926. }
  927. if (ret < 0) {
  928. netif_err(tp, probe, dev, "Get ether addr fail\n");
  929. } else if (!is_valid_ether_addr(sa.sa_data)) {
  930. netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
  931. sa.sa_data);
  932. eth_hw_addr_random(dev);
  933. ether_addr_copy(sa.sa_data, dev->dev_addr);
  934. ret = rtl8152_set_mac_address(dev, &sa);
  935. netif_info(tp, probe, dev, "Random ether addr %pM\n",
  936. sa.sa_data);
  937. } else {
  938. if (tp->version == RTL_VER_01)
  939. ether_addr_copy(dev->dev_addr, sa.sa_data);
  940. else
  941. ret = rtl8152_set_mac_address(dev, &sa);
  942. }
  943. return ret;
  944. }
  945. static void read_bulk_callback(struct urb *urb)
  946. {
  947. struct net_device *netdev;
  948. int status = urb->status;
  949. struct rx_agg *agg;
  950. struct r8152 *tp;
  951. agg = urb->context;
  952. if (!agg)
  953. return;
  954. tp = agg->context;
  955. if (!tp)
  956. return;
  957. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  958. return;
  959. if (!test_bit(WORK_ENABLE, &tp->flags))
  960. return;
  961. netdev = tp->netdev;
  962. /* When link down, the driver would cancel all bulks. */
  963. /* This avoid the re-submitting bulk */
  964. if (!netif_carrier_ok(netdev))
  965. return;
  966. usb_mark_last_busy(tp->udev);
  967. switch (status) {
  968. case 0:
  969. if (urb->actual_length < ETH_ZLEN)
  970. break;
  971. spin_lock(&tp->rx_lock);
  972. list_add_tail(&agg->list, &tp->rx_done);
  973. spin_unlock(&tp->rx_lock);
  974. napi_schedule(&tp->napi);
  975. return;
  976. case -ESHUTDOWN:
  977. set_bit(RTL8152_UNPLUG, &tp->flags);
  978. netif_device_detach(tp->netdev);
  979. return;
  980. case -ENOENT:
  981. return; /* the urb is in unlink state */
  982. case -ETIME:
  983. if (net_ratelimit())
  984. netdev_warn(netdev, "maybe reset is needed?\n");
  985. break;
  986. default:
  987. if (net_ratelimit())
  988. netdev_warn(netdev, "Rx status %d\n", status);
  989. break;
  990. }
  991. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  992. }
  993. static void write_bulk_callback(struct urb *urb)
  994. {
  995. struct net_device_stats *stats;
  996. struct net_device *netdev;
  997. struct tx_agg *agg;
  998. struct r8152 *tp;
  999. int status = urb->status;
  1000. agg = urb->context;
  1001. if (!agg)
  1002. return;
  1003. tp = agg->context;
  1004. if (!tp)
  1005. return;
  1006. netdev = tp->netdev;
  1007. stats = &netdev->stats;
  1008. if (status) {
  1009. if (net_ratelimit())
  1010. netdev_warn(netdev, "Tx status %d\n", status);
  1011. stats->tx_errors += agg->skb_num;
  1012. } else {
  1013. stats->tx_packets += agg->skb_num;
  1014. stats->tx_bytes += agg->skb_len;
  1015. }
  1016. spin_lock(&tp->tx_lock);
  1017. list_add_tail(&agg->list, &tp->tx_free);
  1018. spin_unlock(&tp->tx_lock);
  1019. usb_autopm_put_interface_async(tp->intf);
  1020. if (!netif_carrier_ok(netdev))
  1021. return;
  1022. if (!test_bit(WORK_ENABLE, &tp->flags))
  1023. return;
  1024. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1025. return;
  1026. if (!skb_queue_empty(&tp->tx_queue))
  1027. napi_schedule(&tp->napi);
  1028. }
  1029. static void intr_callback(struct urb *urb)
  1030. {
  1031. struct r8152 *tp;
  1032. __le16 *d;
  1033. int status = urb->status;
  1034. int res;
  1035. tp = urb->context;
  1036. if (!tp)
  1037. return;
  1038. if (!test_bit(WORK_ENABLE, &tp->flags))
  1039. return;
  1040. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1041. return;
  1042. switch (status) {
  1043. case 0: /* success */
  1044. break;
  1045. case -ECONNRESET: /* unlink */
  1046. case -ESHUTDOWN:
  1047. netif_device_detach(tp->netdev);
  1048. case -ENOENT:
  1049. case -EPROTO:
  1050. netif_info(tp, intr, tp->netdev,
  1051. "Stop submitting intr, status %d\n", status);
  1052. return;
  1053. case -EOVERFLOW:
  1054. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  1055. goto resubmit;
  1056. /* -EPIPE: should clear the halt */
  1057. default:
  1058. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  1059. goto resubmit;
  1060. }
  1061. d = urb->transfer_buffer;
  1062. if (INTR_LINK & __le16_to_cpu(d[0])) {
  1063. if (!netif_carrier_ok(tp->netdev)) {
  1064. set_bit(RTL8152_LINK_CHG, &tp->flags);
  1065. schedule_delayed_work(&tp->schedule, 0);
  1066. }
  1067. } else {
  1068. if (netif_carrier_ok(tp->netdev)) {
  1069. netif_stop_queue(tp->netdev);
  1070. set_bit(RTL8152_LINK_CHG, &tp->flags);
  1071. schedule_delayed_work(&tp->schedule, 0);
  1072. }
  1073. }
  1074. resubmit:
  1075. res = usb_submit_urb(urb, GFP_ATOMIC);
  1076. if (res == -ENODEV) {
  1077. set_bit(RTL8152_UNPLUG, &tp->flags);
  1078. netif_device_detach(tp->netdev);
  1079. } else if (res) {
  1080. netif_err(tp, intr, tp->netdev,
  1081. "can't resubmit intr, status %d\n", res);
  1082. }
  1083. }
  1084. static inline void *rx_agg_align(void *data)
  1085. {
  1086. return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
  1087. }
  1088. static inline void *tx_agg_align(void *data)
  1089. {
  1090. return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
  1091. }
  1092. static void free_all_mem(struct r8152 *tp)
  1093. {
  1094. int i;
  1095. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1096. usb_free_urb(tp->rx_info[i].urb);
  1097. tp->rx_info[i].urb = NULL;
  1098. kfree(tp->rx_info[i].buffer);
  1099. tp->rx_info[i].buffer = NULL;
  1100. tp->rx_info[i].head = NULL;
  1101. }
  1102. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1103. usb_free_urb(tp->tx_info[i].urb);
  1104. tp->tx_info[i].urb = NULL;
  1105. kfree(tp->tx_info[i].buffer);
  1106. tp->tx_info[i].buffer = NULL;
  1107. tp->tx_info[i].head = NULL;
  1108. }
  1109. usb_free_urb(tp->intr_urb);
  1110. tp->intr_urb = NULL;
  1111. kfree(tp->intr_buff);
  1112. tp->intr_buff = NULL;
  1113. }
  1114. static int alloc_all_mem(struct r8152 *tp)
  1115. {
  1116. struct net_device *netdev = tp->netdev;
  1117. struct usb_interface *intf = tp->intf;
  1118. struct usb_host_interface *alt = intf->cur_altsetting;
  1119. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  1120. struct urb *urb;
  1121. int node, i;
  1122. u8 *buf;
  1123. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1124. spin_lock_init(&tp->rx_lock);
  1125. spin_lock_init(&tp->tx_lock);
  1126. INIT_LIST_HEAD(&tp->tx_free);
  1127. INIT_LIST_HEAD(&tp->rx_done);
  1128. skb_queue_head_init(&tp->tx_queue);
  1129. skb_queue_head_init(&tp->rx_queue);
  1130. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1131. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1132. if (!buf)
  1133. goto err1;
  1134. if (buf != rx_agg_align(buf)) {
  1135. kfree(buf);
  1136. buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
  1137. node);
  1138. if (!buf)
  1139. goto err1;
  1140. }
  1141. urb = usb_alloc_urb(0, GFP_KERNEL);
  1142. if (!urb) {
  1143. kfree(buf);
  1144. goto err1;
  1145. }
  1146. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1147. tp->rx_info[i].context = tp;
  1148. tp->rx_info[i].urb = urb;
  1149. tp->rx_info[i].buffer = buf;
  1150. tp->rx_info[i].head = rx_agg_align(buf);
  1151. }
  1152. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1153. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1154. if (!buf)
  1155. goto err1;
  1156. if (buf != tx_agg_align(buf)) {
  1157. kfree(buf);
  1158. buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
  1159. node);
  1160. if (!buf)
  1161. goto err1;
  1162. }
  1163. urb = usb_alloc_urb(0, GFP_KERNEL);
  1164. if (!urb) {
  1165. kfree(buf);
  1166. goto err1;
  1167. }
  1168. INIT_LIST_HEAD(&tp->tx_info[i].list);
  1169. tp->tx_info[i].context = tp;
  1170. tp->tx_info[i].urb = urb;
  1171. tp->tx_info[i].buffer = buf;
  1172. tp->tx_info[i].head = tx_agg_align(buf);
  1173. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  1174. }
  1175. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  1176. if (!tp->intr_urb)
  1177. goto err1;
  1178. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  1179. if (!tp->intr_buff)
  1180. goto err1;
  1181. tp->intr_interval = (int)ep_intr->desc.bInterval;
  1182. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  1183. tp->intr_buff, INTBUFSIZE, intr_callback,
  1184. tp, tp->intr_interval);
  1185. return 0;
  1186. err1:
  1187. free_all_mem(tp);
  1188. return -ENOMEM;
  1189. }
  1190. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  1191. {
  1192. struct tx_agg *agg = NULL;
  1193. unsigned long flags;
  1194. if (list_empty(&tp->tx_free))
  1195. return NULL;
  1196. spin_lock_irqsave(&tp->tx_lock, flags);
  1197. if (!list_empty(&tp->tx_free)) {
  1198. struct list_head *cursor;
  1199. cursor = tp->tx_free.next;
  1200. list_del_init(cursor);
  1201. agg = list_entry(cursor, struct tx_agg, list);
  1202. }
  1203. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1204. return agg;
  1205. }
  1206. /* r8152_csum_workaround()
  1207. * The hw limites the value the transport offset. When the offset is out of the
  1208. * range, calculate the checksum by sw.
  1209. */
  1210. static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
  1211. struct sk_buff_head *list)
  1212. {
  1213. if (skb_shinfo(skb)->gso_size) {
  1214. netdev_features_t features = tp->netdev->features;
  1215. struct sk_buff_head seg_list;
  1216. struct sk_buff *segs, *nskb;
  1217. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  1218. segs = skb_gso_segment(skb, features);
  1219. if (IS_ERR(segs) || !segs)
  1220. goto drop;
  1221. __skb_queue_head_init(&seg_list);
  1222. do {
  1223. nskb = segs;
  1224. segs = segs->next;
  1225. nskb->next = NULL;
  1226. __skb_queue_tail(&seg_list, nskb);
  1227. } while (segs);
  1228. skb_queue_splice(&seg_list, list);
  1229. dev_kfree_skb(skb);
  1230. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1231. if (skb_checksum_help(skb) < 0)
  1232. goto drop;
  1233. __skb_queue_head(list, skb);
  1234. } else {
  1235. struct net_device_stats *stats;
  1236. drop:
  1237. stats = &tp->netdev->stats;
  1238. stats->tx_dropped++;
  1239. dev_kfree_skb(skb);
  1240. }
  1241. }
  1242. /* msdn_giant_send_check()
  1243. * According to the document of microsoft, the TCP Pseudo Header excludes the
  1244. * packet length for IPv6 TCP large packets.
  1245. */
  1246. static int msdn_giant_send_check(struct sk_buff *skb)
  1247. {
  1248. const struct ipv6hdr *ipv6h;
  1249. struct tcphdr *th;
  1250. int ret;
  1251. ret = skb_cow_head(skb, 0);
  1252. if (ret)
  1253. return ret;
  1254. ipv6h = ipv6_hdr(skb);
  1255. th = tcp_hdr(skb);
  1256. th->check = 0;
  1257. th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
  1258. return ret;
  1259. }
  1260. static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
  1261. {
  1262. if (skb_vlan_tag_present(skb)) {
  1263. u32 opts2;
  1264. opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
  1265. desc->opts2 |= cpu_to_le32(opts2);
  1266. }
  1267. }
  1268. static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
  1269. {
  1270. u32 opts2 = le32_to_cpu(desc->opts2);
  1271. if (opts2 & RX_VLAN_TAG)
  1272. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  1273. swab16(opts2 & 0xffff));
  1274. }
  1275. static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
  1276. struct sk_buff *skb, u32 len, u32 transport_offset)
  1277. {
  1278. u32 mss = skb_shinfo(skb)->gso_size;
  1279. u32 opts1, opts2 = 0;
  1280. int ret = TX_CSUM_SUCCESS;
  1281. WARN_ON_ONCE(len > TX_LEN_MAX);
  1282. opts1 = len | TX_FS | TX_LS;
  1283. if (mss) {
  1284. if (transport_offset > GTTCPHO_MAX) {
  1285. netif_warn(tp, tx_err, tp->netdev,
  1286. "Invalid transport offset 0x%x for TSO\n",
  1287. transport_offset);
  1288. ret = TX_CSUM_TSO;
  1289. goto unavailable;
  1290. }
  1291. switch (vlan_get_protocol(skb)) {
  1292. case htons(ETH_P_IP):
  1293. opts1 |= GTSENDV4;
  1294. break;
  1295. case htons(ETH_P_IPV6):
  1296. if (msdn_giant_send_check(skb)) {
  1297. ret = TX_CSUM_TSO;
  1298. goto unavailable;
  1299. }
  1300. opts1 |= GTSENDV6;
  1301. break;
  1302. default:
  1303. WARN_ON_ONCE(1);
  1304. break;
  1305. }
  1306. opts1 |= transport_offset << GTTCPHO_SHIFT;
  1307. opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
  1308. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1309. u8 ip_protocol;
  1310. if (transport_offset > TCPHO_MAX) {
  1311. netif_warn(tp, tx_err, tp->netdev,
  1312. "Invalid transport offset 0x%x\n",
  1313. transport_offset);
  1314. ret = TX_CSUM_NONE;
  1315. goto unavailable;
  1316. }
  1317. switch (vlan_get_protocol(skb)) {
  1318. case htons(ETH_P_IP):
  1319. opts2 |= IPV4_CS;
  1320. ip_protocol = ip_hdr(skb)->protocol;
  1321. break;
  1322. case htons(ETH_P_IPV6):
  1323. opts2 |= IPV6_CS;
  1324. ip_protocol = ipv6_hdr(skb)->nexthdr;
  1325. break;
  1326. default:
  1327. ip_protocol = IPPROTO_RAW;
  1328. break;
  1329. }
  1330. if (ip_protocol == IPPROTO_TCP)
  1331. opts2 |= TCP_CS;
  1332. else if (ip_protocol == IPPROTO_UDP)
  1333. opts2 |= UDP_CS;
  1334. else
  1335. WARN_ON_ONCE(1);
  1336. opts2 |= transport_offset << TCPHO_SHIFT;
  1337. }
  1338. desc->opts2 = cpu_to_le32(opts2);
  1339. desc->opts1 = cpu_to_le32(opts1);
  1340. unavailable:
  1341. return ret;
  1342. }
  1343. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  1344. {
  1345. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1346. int remain, ret;
  1347. u8 *tx_data;
  1348. __skb_queue_head_init(&skb_head);
  1349. spin_lock(&tx_queue->lock);
  1350. skb_queue_splice_init(tx_queue, &skb_head);
  1351. spin_unlock(&tx_queue->lock);
  1352. tx_data = agg->head;
  1353. agg->skb_num = 0;
  1354. agg->skb_len = 0;
  1355. remain = agg_buf_sz;
  1356. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  1357. struct tx_desc *tx_desc;
  1358. struct sk_buff *skb;
  1359. unsigned int len;
  1360. u32 offset;
  1361. skb = __skb_dequeue(&skb_head);
  1362. if (!skb)
  1363. break;
  1364. len = skb->len + sizeof(*tx_desc);
  1365. if (len > remain) {
  1366. __skb_queue_head(&skb_head, skb);
  1367. break;
  1368. }
  1369. tx_data = tx_agg_align(tx_data);
  1370. tx_desc = (struct tx_desc *)tx_data;
  1371. offset = (u32)skb_transport_offset(skb);
  1372. if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
  1373. r8152_csum_workaround(tp, skb, &skb_head);
  1374. continue;
  1375. }
  1376. rtl_tx_vlan_tag(tx_desc, skb);
  1377. tx_data += sizeof(*tx_desc);
  1378. len = skb->len;
  1379. if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
  1380. struct net_device_stats *stats = &tp->netdev->stats;
  1381. stats->tx_dropped++;
  1382. dev_kfree_skb_any(skb);
  1383. tx_data -= sizeof(*tx_desc);
  1384. continue;
  1385. }
  1386. tx_data += len;
  1387. agg->skb_len += len;
  1388. agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
  1389. dev_kfree_skb_any(skb);
  1390. remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  1391. }
  1392. if (!skb_queue_empty(&skb_head)) {
  1393. spin_lock(&tx_queue->lock);
  1394. skb_queue_splice(&skb_head, tx_queue);
  1395. spin_unlock(&tx_queue->lock);
  1396. }
  1397. netif_tx_lock(tp->netdev);
  1398. if (netif_queue_stopped(tp->netdev) &&
  1399. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  1400. netif_wake_queue(tp->netdev);
  1401. netif_tx_unlock(tp->netdev);
  1402. ret = usb_autopm_get_interface_async(tp->intf);
  1403. if (ret < 0)
  1404. goto out_tx_fill;
  1405. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1406. agg->head, (int)(tx_data - (u8 *)agg->head),
  1407. (usb_complete_t)write_bulk_callback, agg);
  1408. ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1409. if (ret < 0)
  1410. usb_autopm_put_interface_async(tp->intf);
  1411. out_tx_fill:
  1412. return ret;
  1413. }
  1414. static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
  1415. {
  1416. u8 checksum = CHECKSUM_NONE;
  1417. u32 opts2, opts3;
  1418. if (!(tp->netdev->features & NETIF_F_RXCSUM))
  1419. goto return_result;
  1420. opts2 = le32_to_cpu(rx_desc->opts2);
  1421. opts3 = le32_to_cpu(rx_desc->opts3);
  1422. if (opts2 & RD_IPV4_CS) {
  1423. if (opts3 & IPF)
  1424. checksum = CHECKSUM_NONE;
  1425. else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
  1426. checksum = CHECKSUM_NONE;
  1427. else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
  1428. checksum = CHECKSUM_NONE;
  1429. else
  1430. checksum = CHECKSUM_UNNECESSARY;
  1431. } else if (opts2 & RD_IPV6_CS) {
  1432. if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1433. checksum = CHECKSUM_UNNECESSARY;
  1434. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1435. checksum = CHECKSUM_UNNECESSARY;
  1436. }
  1437. return_result:
  1438. return checksum;
  1439. }
  1440. static int rx_bottom(struct r8152 *tp, int budget)
  1441. {
  1442. unsigned long flags;
  1443. struct list_head *cursor, *next, rx_queue;
  1444. int ret = 0, work_done = 0;
  1445. if (!skb_queue_empty(&tp->rx_queue)) {
  1446. while (work_done < budget) {
  1447. struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
  1448. struct net_device *netdev = tp->netdev;
  1449. struct net_device_stats *stats = &netdev->stats;
  1450. unsigned int pkt_len;
  1451. if (!skb)
  1452. break;
  1453. pkt_len = skb->len;
  1454. napi_gro_receive(&tp->napi, skb);
  1455. work_done++;
  1456. stats->rx_packets++;
  1457. stats->rx_bytes += pkt_len;
  1458. }
  1459. }
  1460. if (list_empty(&tp->rx_done))
  1461. goto out1;
  1462. INIT_LIST_HEAD(&rx_queue);
  1463. spin_lock_irqsave(&tp->rx_lock, flags);
  1464. list_splice_init(&tp->rx_done, &rx_queue);
  1465. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1466. list_for_each_safe(cursor, next, &rx_queue) {
  1467. struct rx_desc *rx_desc;
  1468. struct rx_agg *agg;
  1469. int len_used = 0;
  1470. struct urb *urb;
  1471. u8 *rx_data;
  1472. list_del_init(cursor);
  1473. agg = list_entry(cursor, struct rx_agg, list);
  1474. urb = agg->urb;
  1475. if (urb->actual_length < ETH_ZLEN)
  1476. goto submit;
  1477. rx_desc = agg->head;
  1478. rx_data = agg->head;
  1479. len_used += sizeof(struct rx_desc);
  1480. while (urb->actual_length > len_used) {
  1481. struct net_device *netdev = tp->netdev;
  1482. struct net_device_stats *stats = &netdev->stats;
  1483. unsigned int pkt_len;
  1484. struct sk_buff *skb;
  1485. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1486. if (pkt_len < ETH_ZLEN)
  1487. break;
  1488. len_used += pkt_len;
  1489. if (urb->actual_length < len_used)
  1490. break;
  1491. pkt_len -= CRC_SIZE;
  1492. rx_data += sizeof(struct rx_desc);
  1493. skb = napi_alloc_skb(&tp->napi, pkt_len);
  1494. if (!skb) {
  1495. stats->rx_dropped++;
  1496. goto find_next_rx;
  1497. }
  1498. skb->ip_summed = r8152_rx_csum(tp, rx_desc);
  1499. memcpy(skb->data, rx_data, pkt_len);
  1500. skb_put(skb, pkt_len);
  1501. skb->protocol = eth_type_trans(skb, netdev);
  1502. rtl_rx_vlan_tag(rx_desc, skb);
  1503. if (work_done < budget) {
  1504. napi_gro_receive(&tp->napi, skb);
  1505. work_done++;
  1506. stats->rx_packets++;
  1507. stats->rx_bytes += pkt_len;
  1508. } else {
  1509. __skb_queue_tail(&tp->rx_queue, skb);
  1510. }
  1511. find_next_rx:
  1512. rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
  1513. rx_desc = (struct rx_desc *)rx_data;
  1514. len_used = (int)(rx_data - (u8 *)agg->head);
  1515. len_used += sizeof(struct rx_desc);
  1516. }
  1517. submit:
  1518. if (!ret) {
  1519. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1520. } else {
  1521. urb->actual_length = 0;
  1522. list_add_tail(&agg->list, next);
  1523. }
  1524. }
  1525. if (!list_empty(&rx_queue)) {
  1526. spin_lock_irqsave(&tp->rx_lock, flags);
  1527. list_splice_tail(&rx_queue, &tp->rx_done);
  1528. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1529. }
  1530. out1:
  1531. return work_done;
  1532. }
  1533. static void tx_bottom(struct r8152 *tp)
  1534. {
  1535. int res;
  1536. do {
  1537. struct tx_agg *agg;
  1538. if (skb_queue_empty(&tp->tx_queue))
  1539. break;
  1540. agg = r8152_get_tx_agg(tp);
  1541. if (!agg)
  1542. break;
  1543. res = r8152_tx_agg_fill(tp, agg);
  1544. if (res) {
  1545. struct net_device *netdev = tp->netdev;
  1546. if (res == -ENODEV) {
  1547. set_bit(RTL8152_UNPLUG, &tp->flags);
  1548. netif_device_detach(netdev);
  1549. } else {
  1550. struct net_device_stats *stats = &netdev->stats;
  1551. unsigned long flags;
  1552. netif_warn(tp, tx_err, netdev,
  1553. "failed tx_urb %d\n", res);
  1554. stats->tx_dropped += agg->skb_num;
  1555. spin_lock_irqsave(&tp->tx_lock, flags);
  1556. list_add_tail(&agg->list, &tp->tx_free);
  1557. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1558. }
  1559. }
  1560. } while (res == 0);
  1561. }
  1562. static void bottom_half(struct r8152 *tp)
  1563. {
  1564. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1565. return;
  1566. if (!test_bit(WORK_ENABLE, &tp->flags))
  1567. return;
  1568. /* When link down, the driver would cancel all bulks. */
  1569. /* This avoid the re-submitting bulk */
  1570. if (!netif_carrier_ok(tp->netdev))
  1571. return;
  1572. clear_bit(SCHEDULE_NAPI, &tp->flags);
  1573. tx_bottom(tp);
  1574. }
  1575. static int r8152_poll(struct napi_struct *napi, int budget)
  1576. {
  1577. struct r8152 *tp = container_of(napi, struct r8152, napi);
  1578. int work_done;
  1579. work_done = rx_bottom(tp, budget);
  1580. bottom_half(tp);
  1581. if (work_done < budget) {
  1582. napi_complete(napi);
  1583. if (!list_empty(&tp->rx_done))
  1584. napi_schedule(napi);
  1585. else if (!skb_queue_empty(&tp->tx_queue) &&
  1586. !list_empty(&tp->tx_free))
  1587. napi_schedule(napi);
  1588. }
  1589. return work_done;
  1590. }
  1591. static
  1592. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1593. {
  1594. int ret;
  1595. /* The rx would be stopped, so skip submitting */
  1596. if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
  1597. !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
  1598. return 0;
  1599. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1600. agg->head, agg_buf_sz,
  1601. (usb_complete_t)read_bulk_callback, agg);
  1602. ret = usb_submit_urb(agg->urb, mem_flags);
  1603. if (ret == -ENODEV) {
  1604. set_bit(RTL8152_UNPLUG, &tp->flags);
  1605. netif_device_detach(tp->netdev);
  1606. } else if (ret) {
  1607. struct urb *urb = agg->urb;
  1608. unsigned long flags;
  1609. urb->actual_length = 0;
  1610. spin_lock_irqsave(&tp->rx_lock, flags);
  1611. list_add_tail(&agg->list, &tp->rx_done);
  1612. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1613. netif_err(tp, rx_err, tp->netdev,
  1614. "Couldn't submit rx[%p], ret = %d\n", agg, ret);
  1615. napi_schedule(&tp->napi);
  1616. }
  1617. return ret;
  1618. }
  1619. static void rtl_drop_queued_tx(struct r8152 *tp)
  1620. {
  1621. struct net_device_stats *stats = &tp->netdev->stats;
  1622. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1623. struct sk_buff *skb;
  1624. if (skb_queue_empty(tx_queue))
  1625. return;
  1626. __skb_queue_head_init(&skb_head);
  1627. spin_lock_bh(&tx_queue->lock);
  1628. skb_queue_splice_init(tx_queue, &skb_head);
  1629. spin_unlock_bh(&tx_queue->lock);
  1630. while ((skb = __skb_dequeue(&skb_head))) {
  1631. dev_kfree_skb(skb);
  1632. stats->tx_dropped++;
  1633. }
  1634. }
  1635. static void rtl8152_tx_timeout(struct net_device *netdev)
  1636. {
  1637. struct r8152 *tp = netdev_priv(netdev);
  1638. netif_warn(tp, tx_err, netdev, "Tx timeout\n");
  1639. usb_queue_reset_device(tp->intf);
  1640. }
  1641. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1642. {
  1643. struct r8152 *tp = netdev_priv(netdev);
  1644. if (netif_carrier_ok(netdev)) {
  1645. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1646. schedule_delayed_work(&tp->schedule, 0);
  1647. }
  1648. }
  1649. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1650. {
  1651. struct r8152 *tp = netdev_priv(netdev);
  1652. u32 mc_filter[2]; /* Multicast hash filter */
  1653. __le32 tmp[2];
  1654. u32 ocp_data;
  1655. netif_stop_queue(netdev);
  1656. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1657. ocp_data &= ~RCR_ACPT_ALL;
  1658. ocp_data |= RCR_AB | RCR_APM;
  1659. if (netdev->flags & IFF_PROMISC) {
  1660. /* Unconditionally log net taps. */
  1661. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1662. ocp_data |= RCR_AM | RCR_AAP;
  1663. mc_filter[1] = 0xffffffff;
  1664. mc_filter[0] = 0xffffffff;
  1665. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1666. (netdev->flags & IFF_ALLMULTI)) {
  1667. /* Too many to filter perfectly -- accept all multicasts. */
  1668. ocp_data |= RCR_AM;
  1669. mc_filter[1] = 0xffffffff;
  1670. mc_filter[0] = 0xffffffff;
  1671. } else {
  1672. struct netdev_hw_addr *ha;
  1673. mc_filter[1] = 0;
  1674. mc_filter[0] = 0;
  1675. netdev_for_each_mc_addr(ha, netdev) {
  1676. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1677. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1678. ocp_data |= RCR_AM;
  1679. }
  1680. }
  1681. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1682. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1683. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1684. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1685. netif_wake_queue(netdev);
  1686. }
  1687. static netdev_features_t
  1688. rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
  1689. netdev_features_t features)
  1690. {
  1691. u32 mss = skb_shinfo(skb)->gso_size;
  1692. int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
  1693. int offset = skb_transport_offset(skb);
  1694. if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
  1695. features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
  1696. else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
  1697. features &= ~NETIF_F_GSO_MASK;
  1698. return features;
  1699. }
  1700. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1701. struct net_device *netdev)
  1702. {
  1703. struct r8152 *tp = netdev_priv(netdev);
  1704. skb_tx_timestamp(skb);
  1705. skb_queue_tail(&tp->tx_queue, skb);
  1706. if (!list_empty(&tp->tx_free)) {
  1707. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  1708. set_bit(SCHEDULE_NAPI, &tp->flags);
  1709. schedule_delayed_work(&tp->schedule, 0);
  1710. } else {
  1711. usb_mark_last_busy(tp->udev);
  1712. napi_schedule(&tp->napi);
  1713. }
  1714. } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
  1715. netif_stop_queue(netdev);
  1716. }
  1717. return NETDEV_TX_OK;
  1718. }
  1719. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1720. {
  1721. u32 ocp_data;
  1722. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1723. ocp_data &= ~FMC_FCR_MCU_EN;
  1724. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1725. ocp_data |= FMC_FCR_MCU_EN;
  1726. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1727. }
  1728. static void rtl8152_nic_reset(struct r8152 *tp)
  1729. {
  1730. int i;
  1731. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1732. for (i = 0; i < 1000; i++) {
  1733. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1734. break;
  1735. usleep_range(100, 400);
  1736. }
  1737. }
  1738. static void set_tx_qlen(struct r8152 *tp)
  1739. {
  1740. struct net_device *netdev = tp->netdev;
  1741. tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
  1742. sizeof(struct tx_desc));
  1743. }
  1744. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1745. {
  1746. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1747. }
  1748. static void rtl_set_eee_plus(struct r8152 *tp)
  1749. {
  1750. u32 ocp_data;
  1751. u8 speed;
  1752. speed = rtl8152_get_speed(tp);
  1753. if (speed & _10bps) {
  1754. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1755. ocp_data |= EEEP_CR_EEEP_TX;
  1756. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1757. } else {
  1758. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1759. ocp_data &= ~EEEP_CR_EEEP_TX;
  1760. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1761. }
  1762. }
  1763. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  1764. {
  1765. u32 ocp_data;
  1766. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1767. if (enable)
  1768. ocp_data |= RXDY_GATED_EN;
  1769. else
  1770. ocp_data &= ~RXDY_GATED_EN;
  1771. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1772. }
  1773. static int rtl_start_rx(struct r8152 *tp)
  1774. {
  1775. int i, ret = 0;
  1776. INIT_LIST_HEAD(&tp->rx_done);
  1777. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1778. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1779. ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1780. if (ret)
  1781. break;
  1782. }
  1783. if (ret && ++i < RTL8152_MAX_RX) {
  1784. struct list_head rx_queue;
  1785. unsigned long flags;
  1786. INIT_LIST_HEAD(&rx_queue);
  1787. do {
  1788. struct rx_agg *agg = &tp->rx_info[i++];
  1789. struct urb *urb = agg->urb;
  1790. urb->actual_length = 0;
  1791. list_add_tail(&agg->list, &rx_queue);
  1792. } while (i < RTL8152_MAX_RX);
  1793. spin_lock_irqsave(&tp->rx_lock, flags);
  1794. list_splice_tail(&rx_queue, &tp->rx_done);
  1795. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1796. }
  1797. return ret;
  1798. }
  1799. static int rtl_stop_rx(struct r8152 *tp)
  1800. {
  1801. int i;
  1802. for (i = 0; i < RTL8152_MAX_RX; i++)
  1803. usb_kill_urb(tp->rx_info[i].urb);
  1804. while (!skb_queue_empty(&tp->rx_queue))
  1805. dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
  1806. return 0;
  1807. }
  1808. static int rtl_enable(struct r8152 *tp)
  1809. {
  1810. u32 ocp_data;
  1811. r8152b_reset_packet_filter(tp);
  1812. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1813. ocp_data |= CR_RE | CR_TE;
  1814. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1815. rxdy_gated_en(tp, false);
  1816. return 0;
  1817. }
  1818. static int rtl8152_enable(struct r8152 *tp)
  1819. {
  1820. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1821. return -ENODEV;
  1822. set_tx_qlen(tp);
  1823. rtl_set_eee_plus(tp);
  1824. return rtl_enable(tp);
  1825. }
  1826. static void r8153_set_rx_early_timeout(struct r8152 *tp)
  1827. {
  1828. u32 ocp_data = tp->coalesce / 8;
  1829. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
  1830. }
  1831. static void r8153_set_rx_early_size(struct r8152 *tp)
  1832. {
  1833. u32 ocp_data = (agg_buf_sz - rx_reserved_size(tp->netdev->mtu)) / 4;
  1834. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
  1835. }
  1836. static int rtl8153_enable(struct r8152 *tp)
  1837. {
  1838. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1839. return -ENODEV;
  1840. usb_disable_lpm(tp->udev);
  1841. set_tx_qlen(tp);
  1842. rtl_set_eee_plus(tp);
  1843. r8153_set_rx_early_timeout(tp);
  1844. r8153_set_rx_early_size(tp);
  1845. return rtl_enable(tp);
  1846. }
  1847. static void rtl_disable(struct r8152 *tp)
  1848. {
  1849. u32 ocp_data;
  1850. int i;
  1851. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  1852. rtl_drop_queued_tx(tp);
  1853. return;
  1854. }
  1855. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1856. ocp_data &= ~RCR_ACPT_ALL;
  1857. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1858. rtl_drop_queued_tx(tp);
  1859. for (i = 0; i < RTL8152_MAX_TX; i++)
  1860. usb_kill_urb(tp->tx_info[i].urb);
  1861. rxdy_gated_en(tp, true);
  1862. for (i = 0; i < 1000; i++) {
  1863. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1864. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1865. break;
  1866. usleep_range(1000, 2000);
  1867. }
  1868. for (i = 0; i < 1000; i++) {
  1869. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1870. break;
  1871. usleep_range(1000, 2000);
  1872. }
  1873. rtl_stop_rx(tp);
  1874. rtl8152_nic_reset(tp);
  1875. }
  1876. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  1877. {
  1878. u32 ocp_data;
  1879. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1880. if (enable)
  1881. ocp_data |= POWER_CUT;
  1882. else
  1883. ocp_data &= ~POWER_CUT;
  1884. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1885. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1886. ocp_data &= ~RESUME_INDICATE;
  1887. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1888. }
  1889. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  1890. {
  1891. u32 ocp_data;
  1892. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1893. if (enable)
  1894. ocp_data |= CPCR_RX_VLAN;
  1895. else
  1896. ocp_data &= ~CPCR_RX_VLAN;
  1897. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1898. }
  1899. static int rtl8152_set_features(struct net_device *dev,
  1900. netdev_features_t features)
  1901. {
  1902. netdev_features_t changed = features ^ dev->features;
  1903. struct r8152 *tp = netdev_priv(dev);
  1904. int ret;
  1905. ret = usb_autopm_get_interface(tp->intf);
  1906. if (ret < 0)
  1907. goto out;
  1908. mutex_lock(&tp->control);
  1909. if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
  1910. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1911. rtl_rx_vlan_en(tp, true);
  1912. else
  1913. rtl_rx_vlan_en(tp, false);
  1914. }
  1915. mutex_unlock(&tp->control);
  1916. usb_autopm_put_interface(tp->intf);
  1917. out:
  1918. return ret;
  1919. }
  1920. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1921. static u32 __rtl_get_wol(struct r8152 *tp)
  1922. {
  1923. u32 ocp_data;
  1924. u32 wolopts = 0;
  1925. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1926. if (ocp_data & LINK_ON_WAKE_EN)
  1927. wolopts |= WAKE_PHY;
  1928. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1929. if (ocp_data & UWF_EN)
  1930. wolopts |= WAKE_UCAST;
  1931. if (ocp_data & BWF_EN)
  1932. wolopts |= WAKE_BCAST;
  1933. if (ocp_data & MWF_EN)
  1934. wolopts |= WAKE_MCAST;
  1935. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1936. if (ocp_data & MAGIC_EN)
  1937. wolopts |= WAKE_MAGIC;
  1938. return wolopts;
  1939. }
  1940. static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
  1941. {
  1942. u32 ocp_data;
  1943. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1944. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1945. ocp_data &= ~LINK_ON_WAKE_EN;
  1946. if (wolopts & WAKE_PHY)
  1947. ocp_data |= LINK_ON_WAKE_EN;
  1948. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1949. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1950. ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
  1951. if (wolopts & WAKE_UCAST)
  1952. ocp_data |= UWF_EN;
  1953. if (wolopts & WAKE_BCAST)
  1954. ocp_data |= BWF_EN;
  1955. if (wolopts & WAKE_MCAST)
  1956. ocp_data |= MWF_EN;
  1957. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  1958. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1959. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1960. ocp_data &= ~MAGIC_EN;
  1961. if (wolopts & WAKE_MAGIC)
  1962. ocp_data |= MAGIC_EN;
  1963. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1964. if (wolopts & WAKE_ANY)
  1965. device_set_wakeup_enable(&tp->udev->dev, true);
  1966. else
  1967. device_set_wakeup_enable(&tp->udev->dev, false);
  1968. }
  1969. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  1970. {
  1971. u8 u1u2[8];
  1972. if (enable)
  1973. memset(u1u2, 0xff, sizeof(u1u2));
  1974. else
  1975. memset(u1u2, 0x00, sizeof(u1u2));
  1976. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  1977. }
  1978. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  1979. {
  1980. u32 ocp_data;
  1981. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  1982. if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
  1983. ocp_data |= U2P3_ENABLE;
  1984. else
  1985. ocp_data &= ~U2P3_ENABLE;
  1986. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  1987. }
  1988. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  1989. {
  1990. u32 ocp_data;
  1991. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  1992. if (enable)
  1993. ocp_data |= PWR_EN | PHASE2_EN;
  1994. else
  1995. ocp_data &= ~(PWR_EN | PHASE2_EN);
  1996. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  1997. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  1998. ocp_data &= ~PCUT_STATUS;
  1999. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  2000. }
  2001. static bool rtl_can_wakeup(struct r8152 *tp)
  2002. {
  2003. struct usb_device *udev = tp->udev;
  2004. return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
  2005. }
  2006. static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
  2007. {
  2008. if (enable) {
  2009. u32 ocp_data;
  2010. __rtl_set_wol(tp, WAKE_ANY);
  2011. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  2012. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  2013. ocp_data |= LINK_OFF_WAKE_EN;
  2014. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  2015. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2016. } else {
  2017. u32 ocp_data;
  2018. __rtl_set_wol(tp, tp->saved_wolopts);
  2019. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  2020. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  2021. ocp_data &= ~LINK_OFF_WAKE_EN;
  2022. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  2023. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2024. }
  2025. }
  2026. static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
  2027. {
  2028. rtl_runtime_suspend_enable(tp, enable);
  2029. if (enable) {
  2030. r8153_u1u2en(tp, false);
  2031. r8153_u2p3en(tp, false);
  2032. } else {
  2033. r8153_u2p3en(tp, true);
  2034. r8153_u1u2en(tp, true);
  2035. }
  2036. }
  2037. static void r8153_teredo_off(struct r8152 *tp)
  2038. {
  2039. u32 ocp_data;
  2040. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2041. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
  2042. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2043. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  2044. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  2045. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  2046. }
  2047. static void rtl_reset_bmu(struct r8152 *tp)
  2048. {
  2049. u32 ocp_data;
  2050. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
  2051. ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
  2052. ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  2053. ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
  2054. ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  2055. }
  2056. static void r8152_aldps_en(struct r8152 *tp, bool enable)
  2057. {
  2058. if (enable) {
  2059. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  2060. LINKENA | DIS_SDSAVE);
  2061. } else {
  2062. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
  2063. DIS_SDSAVE);
  2064. msleep(20);
  2065. }
  2066. }
  2067. static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
  2068. {
  2069. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
  2070. ocp_reg_write(tp, OCP_EEE_DATA, reg);
  2071. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
  2072. }
  2073. static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
  2074. {
  2075. u16 data;
  2076. r8152_mmd_indirect(tp, dev, reg);
  2077. data = ocp_reg_read(tp, OCP_EEE_DATA);
  2078. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2079. return data;
  2080. }
  2081. static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
  2082. {
  2083. r8152_mmd_indirect(tp, dev, reg);
  2084. ocp_reg_write(tp, OCP_EEE_DATA, data);
  2085. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2086. }
  2087. static void r8152_eee_en(struct r8152 *tp, bool enable)
  2088. {
  2089. u16 config1, config2, config3;
  2090. u32 ocp_data;
  2091. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2092. config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
  2093. config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
  2094. config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
  2095. if (enable) {
  2096. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2097. config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
  2098. config1 |= sd_rise_time(1);
  2099. config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
  2100. config3 |= fast_snr(42);
  2101. } else {
  2102. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2103. config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
  2104. RX_QUIET_EN);
  2105. config1 |= sd_rise_time(7);
  2106. config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
  2107. config3 |= fast_snr(511);
  2108. }
  2109. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2110. ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
  2111. ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
  2112. ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
  2113. }
  2114. static void r8152b_enable_eee(struct r8152 *tp)
  2115. {
  2116. r8152_eee_en(tp, true);
  2117. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
  2118. }
  2119. static void r8152b_enable_fc(struct r8152 *tp)
  2120. {
  2121. u16 anar;
  2122. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2123. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  2124. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2125. }
  2126. static void rtl8152_disable(struct r8152 *tp)
  2127. {
  2128. r8152_aldps_en(tp, false);
  2129. rtl_disable(tp);
  2130. r8152_aldps_en(tp, true);
  2131. }
  2132. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  2133. {
  2134. r8152b_enable_eee(tp);
  2135. r8152_aldps_en(tp, true);
  2136. r8152b_enable_fc(tp);
  2137. set_bit(PHY_RESET, &tp->flags);
  2138. }
  2139. static void r8152b_exit_oob(struct r8152 *tp)
  2140. {
  2141. u32 ocp_data;
  2142. int i;
  2143. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2144. ocp_data &= ~RCR_ACPT_ALL;
  2145. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2146. rxdy_gated_en(tp, true);
  2147. r8153_teredo_off(tp);
  2148. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2149. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  2150. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2151. ocp_data &= ~NOW_IS_OOB;
  2152. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2153. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2154. ocp_data &= ~MCU_BORW_EN;
  2155. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2156. for (i = 0; i < 1000; i++) {
  2157. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2158. if (ocp_data & LINK_LIST_READY)
  2159. break;
  2160. usleep_range(1000, 2000);
  2161. }
  2162. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2163. ocp_data |= RE_INIT_LL;
  2164. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2165. for (i = 0; i < 1000; i++) {
  2166. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2167. if (ocp_data & LINK_LIST_READY)
  2168. break;
  2169. usleep_range(1000, 2000);
  2170. }
  2171. rtl8152_nic_reset(tp);
  2172. /* rx share fifo credit full threshold */
  2173. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2174. if (tp->udev->speed == USB_SPEED_FULL ||
  2175. tp->udev->speed == USB_SPEED_LOW) {
  2176. /* rx share fifo credit near full threshold */
  2177. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2178. RXFIFO_THR2_FULL);
  2179. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2180. RXFIFO_THR3_FULL);
  2181. } else {
  2182. /* rx share fifo credit near full threshold */
  2183. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2184. RXFIFO_THR2_HIGH);
  2185. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2186. RXFIFO_THR3_HIGH);
  2187. }
  2188. /* TX share fifo free credit full threshold */
  2189. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  2190. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  2191. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  2192. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  2193. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  2194. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2195. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2196. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2197. ocp_data |= TCR0_AUTO_FIFO;
  2198. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2199. }
  2200. static void r8152b_enter_oob(struct r8152 *tp)
  2201. {
  2202. u32 ocp_data;
  2203. int i;
  2204. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2205. ocp_data &= ~NOW_IS_OOB;
  2206. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2207. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  2208. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  2209. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  2210. rtl_disable(tp);
  2211. for (i = 0; i < 1000; i++) {
  2212. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2213. if (ocp_data & LINK_LIST_READY)
  2214. break;
  2215. usleep_range(1000, 2000);
  2216. }
  2217. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2218. ocp_data |= RE_INIT_LL;
  2219. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2220. for (i = 0; i < 1000; i++) {
  2221. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2222. if (ocp_data & LINK_LIST_READY)
  2223. break;
  2224. usleep_range(1000, 2000);
  2225. }
  2226. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2227. rtl_rx_vlan_en(tp, true);
  2228. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2229. ocp_data |= ALDPS_PROXY_MODE;
  2230. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2231. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2232. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2233. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2234. rxdy_gated_en(tp, false);
  2235. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2236. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2237. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2238. }
  2239. static void r8153_aldps_en(struct r8152 *tp, bool enable)
  2240. {
  2241. u16 data;
  2242. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2243. if (enable) {
  2244. data |= EN_ALDPS;
  2245. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2246. } else {
  2247. data &= ~EN_ALDPS;
  2248. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2249. msleep(20);
  2250. }
  2251. }
  2252. static void r8153_eee_en(struct r8152 *tp, bool enable)
  2253. {
  2254. u32 ocp_data;
  2255. u16 config;
  2256. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2257. config = ocp_reg_read(tp, OCP_EEE_CFG);
  2258. if (enable) {
  2259. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2260. config |= EEE10_EN;
  2261. } else {
  2262. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2263. config &= ~EEE10_EN;
  2264. }
  2265. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2266. ocp_reg_write(tp, OCP_EEE_CFG, config);
  2267. }
  2268. static void r8153_hw_phy_cfg(struct r8152 *tp)
  2269. {
  2270. u32 ocp_data;
  2271. u16 data;
  2272. /* disable ALDPS before updating the PHY parameters */
  2273. r8153_aldps_en(tp, false);
  2274. /* disable EEE before updating the PHY parameters */
  2275. r8153_eee_en(tp, false);
  2276. ocp_reg_write(tp, OCP_EEE_ADV, 0);
  2277. if (tp->version == RTL_VER_03) {
  2278. data = ocp_reg_read(tp, OCP_EEE_CFG);
  2279. data &= ~CTAP_SHORT_EN;
  2280. ocp_reg_write(tp, OCP_EEE_CFG, data);
  2281. }
  2282. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2283. data |= EEE_CLKDIV_EN;
  2284. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2285. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  2286. data |= EN_10M_BGOFF;
  2287. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  2288. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2289. data |= EN_10M_PLLOFF;
  2290. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2291. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  2292. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2293. ocp_data |= PFM_PWM_SWITCH;
  2294. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2295. /* Enable LPF corner auto tune */
  2296. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  2297. /* Adjust 10M Amplitude */
  2298. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  2299. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  2300. r8153_eee_en(tp, true);
  2301. ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
  2302. r8153_aldps_en(tp, true);
  2303. r8152b_enable_fc(tp);
  2304. set_bit(PHY_RESET, &tp->flags);
  2305. }
  2306. static void r8153_first_init(struct r8152 *tp)
  2307. {
  2308. u32 ocp_data;
  2309. int i;
  2310. rxdy_gated_en(tp, true);
  2311. r8153_teredo_off(tp);
  2312. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2313. ocp_data &= ~RCR_ACPT_ALL;
  2314. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2315. rtl8152_nic_reset(tp);
  2316. rtl_reset_bmu(tp);
  2317. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2318. ocp_data &= ~NOW_IS_OOB;
  2319. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2320. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2321. ocp_data &= ~MCU_BORW_EN;
  2322. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2323. for (i = 0; i < 1000; i++) {
  2324. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2325. if (ocp_data & LINK_LIST_READY)
  2326. break;
  2327. usleep_range(1000, 2000);
  2328. }
  2329. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2330. ocp_data |= RE_INIT_LL;
  2331. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2332. for (i = 0; i < 1000; i++) {
  2333. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2334. if (ocp_data & LINK_LIST_READY)
  2335. break;
  2336. usleep_range(1000, 2000);
  2337. }
  2338. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2339. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2340. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  2341. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2342. ocp_data |= TCR0_AUTO_FIFO;
  2343. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2344. rtl8152_nic_reset(tp);
  2345. /* rx share fifo credit full threshold */
  2346. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2347. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  2348. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  2349. /* TX share fifo free credit full threshold */
  2350. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  2351. /* rx aggregation */
  2352. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2353. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  2354. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2355. }
  2356. static void r8153_enter_oob(struct r8152 *tp)
  2357. {
  2358. u32 ocp_data;
  2359. int i;
  2360. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2361. ocp_data &= ~NOW_IS_OOB;
  2362. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2363. rtl_disable(tp);
  2364. rtl_reset_bmu(tp);
  2365. for (i = 0; i < 1000; i++) {
  2366. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2367. if (ocp_data & LINK_LIST_READY)
  2368. break;
  2369. usleep_range(1000, 2000);
  2370. }
  2371. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2372. ocp_data |= RE_INIT_LL;
  2373. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2374. for (i = 0; i < 1000; i++) {
  2375. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2376. if (ocp_data & LINK_LIST_READY)
  2377. break;
  2378. usleep_range(1000, 2000);
  2379. }
  2380. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2381. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2382. ocp_data &= ~TEREDO_WAKE_MASK;
  2383. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2384. rtl_rx_vlan_en(tp, true);
  2385. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2386. ocp_data |= ALDPS_PROXY_MODE;
  2387. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2388. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2389. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2390. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2391. rxdy_gated_en(tp, false);
  2392. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2393. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2394. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2395. }
  2396. static void rtl8153_disable(struct r8152 *tp)
  2397. {
  2398. r8153_aldps_en(tp, false);
  2399. rtl_disable(tp);
  2400. rtl_reset_bmu(tp);
  2401. r8153_aldps_en(tp, true);
  2402. usb_enable_lpm(tp->udev);
  2403. }
  2404. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  2405. {
  2406. u16 bmcr, anar, gbcr;
  2407. int ret = 0;
  2408. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2409. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  2410. ADVERTISE_100HALF | ADVERTISE_100FULL);
  2411. if (tp->mii.supports_gmii) {
  2412. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  2413. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  2414. } else {
  2415. gbcr = 0;
  2416. }
  2417. if (autoneg == AUTONEG_DISABLE) {
  2418. if (speed == SPEED_10) {
  2419. bmcr = 0;
  2420. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2421. } else if (speed == SPEED_100) {
  2422. bmcr = BMCR_SPEED100;
  2423. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2424. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2425. bmcr = BMCR_SPEED1000;
  2426. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2427. } else {
  2428. ret = -EINVAL;
  2429. goto out;
  2430. }
  2431. if (duplex == DUPLEX_FULL)
  2432. bmcr |= BMCR_FULLDPLX;
  2433. } else {
  2434. if (speed == SPEED_10) {
  2435. if (duplex == DUPLEX_FULL)
  2436. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2437. else
  2438. anar |= ADVERTISE_10HALF;
  2439. } else if (speed == SPEED_100) {
  2440. if (duplex == DUPLEX_FULL) {
  2441. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2442. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2443. } else {
  2444. anar |= ADVERTISE_10HALF;
  2445. anar |= ADVERTISE_100HALF;
  2446. }
  2447. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2448. if (duplex == DUPLEX_FULL) {
  2449. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2450. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2451. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2452. } else {
  2453. anar |= ADVERTISE_10HALF;
  2454. anar |= ADVERTISE_100HALF;
  2455. gbcr |= ADVERTISE_1000HALF;
  2456. }
  2457. } else {
  2458. ret = -EINVAL;
  2459. goto out;
  2460. }
  2461. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  2462. }
  2463. if (test_and_clear_bit(PHY_RESET, &tp->flags))
  2464. bmcr |= BMCR_RESET;
  2465. if (tp->mii.supports_gmii)
  2466. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  2467. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2468. r8152_mdio_write(tp, MII_BMCR, bmcr);
  2469. if (bmcr & BMCR_RESET) {
  2470. int i;
  2471. for (i = 0; i < 50; i++) {
  2472. msleep(20);
  2473. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  2474. break;
  2475. }
  2476. }
  2477. out:
  2478. return ret;
  2479. }
  2480. static void rtl8152_up(struct r8152 *tp)
  2481. {
  2482. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2483. return;
  2484. r8152_aldps_en(tp, false);
  2485. r8152b_exit_oob(tp);
  2486. r8152_aldps_en(tp, true);
  2487. }
  2488. static void rtl8152_down(struct r8152 *tp)
  2489. {
  2490. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2491. rtl_drop_queued_tx(tp);
  2492. return;
  2493. }
  2494. r8152_power_cut_en(tp, false);
  2495. r8152_aldps_en(tp, false);
  2496. r8152b_enter_oob(tp);
  2497. r8152_aldps_en(tp, true);
  2498. }
  2499. static void rtl8153_up(struct r8152 *tp)
  2500. {
  2501. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2502. return;
  2503. r8153_u1u2en(tp, false);
  2504. r8153_aldps_en(tp, false);
  2505. r8153_first_init(tp);
  2506. r8153_aldps_en(tp, true);
  2507. r8153_u2p3en(tp, true);
  2508. r8153_u1u2en(tp, true);
  2509. usb_enable_lpm(tp->udev);
  2510. }
  2511. static void rtl8153_down(struct r8152 *tp)
  2512. {
  2513. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2514. rtl_drop_queued_tx(tp);
  2515. return;
  2516. }
  2517. r8153_u1u2en(tp, false);
  2518. r8153_u2p3en(tp, false);
  2519. r8153_power_cut_en(tp, false);
  2520. r8153_aldps_en(tp, false);
  2521. r8153_enter_oob(tp);
  2522. r8153_aldps_en(tp, true);
  2523. }
  2524. static bool rtl8152_in_nway(struct r8152 *tp)
  2525. {
  2526. u16 nway_state;
  2527. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
  2528. tp->ocp_base = 0x2000;
  2529. ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
  2530. nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
  2531. /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
  2532. if (nway_state & 0xc000)
  2533. return false;
  2534. else
  2535. return true;
  2536. }
  2537. static bool rtl8153_in_nway(struct r8152 *tp)
  2538. {
  2539. u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
  2540. if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
  2541. return false;
  2542. else
  2543. return true;
  2544. }
  2545. static void set_carrier(struct r8152 *tp)
  2546. {
  2547. struct net_device *netdev = tp->netdev;
  2548. u8 speed;
  2549. speed = rtl8152_get_speed(tp);
  2550. if (speed & LINK_STATUS) {
  2551. if (!netif_carrier_ok(netdev)) {
  2552. tp->rtl_ops.enable(tp);
  2553. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  2554. netif_stop_queue(netdev);
  2555. napi_disable(&tp->napi);
  2556. netif_carrier_on(netdev);
  2557. rtl_start_rx(tp);
  2558. napi_enable(&tp->napi);
  2559. netif_wake_queue(netdev);
  2560. netif_info(tp, link, netdev, "carrier on\n");
  2561. } else if (netif_queue_stopped(netdev) &&
  2562. skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
  2563. netif_wake_queue(netdev);
  2564. }
  2565. } else {
  2566. if (netif_carrier_ok(netdev)) {
  2567. netif_carrier_off(netdev);
  2568. napi_disable(&tp->napi);
  2569. tp->rtl_ops.disable(tp);
  2570. napi_enable(&tp->napi);
  2571. netif_info(tp, link, netdev, "carrier off\n");
  2572. }
  2573. }
  2574. }
  2575. static void rtl_work_func_t(struct work_struct *work)
  2576. {
  2577. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  2578. /* If the device is unplugged or !netif_running(), the workqueue
  2579. * doesn't need to wake the device, and could return directly.
  2580. */
  2581. if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
  2582. return;
  2583. if (usb_autopm_get_interface(tp->intf) < 0)
  2584. return;
  2585. if (!test_bit(WORK_ENABLE, &tp->flags))
  2586. goto out1;
  2587. if (!mutex_trylock(&tp->control)) {
  2588. schedule_delayed_work(&tp->schedule, 0);
  2589. goto out1;
  2590. }
  2591. if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
  2592. set_carrier(tp);
  2593. if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
  2594. _rtl8152_set_rx_mode(tp->netdev);
  2595. /* don't schedule napi before linking */
  2596. if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
  2597. netif_carrier_ok(tp->netdev))
  2598. napi_schedule(&tp->napi);
  2599. mutex_unlock(&tp->control);
  2600. out1:
  2601. usb_autopm_put_interface(tp->intf);
  2602. }
  2603. static void rtl_hw_phy_work_func_t(struct work_struct *work)
  2604. {
  2605. struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
  2606. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2607. return;
  2608. if (usb_autopm_get_interface(tp->intf) < 0)
  2609. return;
  2610. mutex_lock(&tp->control);
  2611. tp->rtl_ops.hw_phy_cfg(tp);
  2612. rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
  2613. mutex_unlock(&tp->control);
  2614. usb_autopm_put_interface(tp->intf);
  2615. }
  2616. #ifdef CONFIG_PM_SLEEP
  2617. static int rtl_notifier(struct notifier_block *nb, unsigned long action,
  2618. void *data)
  2619. {
  2620. struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
  2621. switch (action) {
  2622. case PM_HIBERNATION_PREPARE:
  2623. case PM_SUSPEND_PREPARE:
  2624. usb_autopm_get_interface(tp->intf);
  2625. break;
  2626. case PM_POST_HIBERNATION:
  2627. case PM_POST_SUSPEND:
  2628. usb_autopm_put_interface(tp->intf);
  2629. break;
  2630. case PM_POST_RESTORE:
  2631. case PM_RESTORE_PREPARE:
  2632. default:
  2633. break;
  2634. }
  2635. return NOTIFY_DONE;
  2636. }
  2637. #endif
  2638. static int rtl8152_open(struct net_device *netdev)
  2639. {
  2640. struct r8152 *tp = netdev_priv(netdev);
  2641. int res = 0;
  2642. res = alloc_all_mem(tp);
  2643. if (res)
  2644. goto out;
  2645. res = usb_autopm_get_interface(tp->intf);
  2646. if (res < 0)
  2647. goto out_free;
  2648. mutex_lock(&tp->control);
  2649. tp->rtl_ops.up(tp);
  2650. netif_carrier_off(netdev);
  2651. netif_start_queue(netdev);
  2652. set_bit(WORK_ENABLE, &tp->flags);
  2653. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2654. if (res) {
  2655. if (res == -ENODEV)
  2656. netif_device_detach(tp->netdev);
  2657. netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
  2658. res);
  2659. goto out_unlock;
  2660. }
  2661. napi_enable(&tp->napi);
  2662. mutex_unlock(&tp->control);
  2663. usb_autopm_put_interface(tp->intf);
  2664. #ifdef CONFIG_PM_SLEEP
  2665. tp->pm_notifier.notifier_call = rtl_notifier;
  2666. register_pm_notifier(&tp->pm_notifier);
  2667. #endif
  2668. return 0;
  2669. out_unlock:
  2670. mutex_unlock(&tp->control);
  2671. usb_autopm_put_interface(tp->intf);
  2672. out_free:
  2673. free_all_mem(tp);
  2674. out:
  2675. return res;
  2676. }
  2677. static int rtl8152_close(struct net_device *netdev)
  2678. {
  2679. struct r8152 *tp = netdev_priv(netdev);
  2680. int res = 0;
  2681. #ifdef CONFIG_PM_SLEEP
  2682. unregister_pm_notifier(&tp->pm_notifier);
  2683. #endif
  2684. if (!test_bit(RTL8152_UNPLUG, &tp->flags))
  2685. napi_disable(&tp->napi);
  2686. clear_bit(WORK_ENABLE, &tp->flags);
  2687. usb_kill_urb(tp->intr_urb);
  2688. cancel_delayed_work_sync(&tp->schedule);
  2689. netif_stop_queue(netdev);
  2690. res = usb_autopm_get_interface(tp->intf);
  2691. if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2692. rtl_drop_queued_tx(tp);
  2693. rtl_stop_rx(tp);
  2694. } else {
  2695. mutex_lock(&tp->control);
  2696. tp->rtl_ops.down(tp);
  2697. mutex_unlock(&tp->control);
  2698. usb_autopm_put_interface(tp->intf);
  2699. }
  2700. free_all_mem(tp);
  2701. return res;
  2702. }
  2703. static void rtl_tally_reset(struct r8152 *tp)
  2704. {
  2705. u32 ocp_data;
  2706. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  2707. ocp_data |= TALLY_RESET;
  2708. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  2709. }
  2710. static void r8152b_init(struct r8152 *tp)
  2711. {
  2712. u32 ocp_data;
  2713. u16 data;
  2714. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2715. return;
  2716. data = r8152_mdio_read(tp, MII_BMCR);
  2717. if (data & BMCR_PDOWN) {
  2718. data &= ~BMCR_PDOWN;
  2719. r8152_mdio_write(tp, MII_BMCR, data);
  2720. }
  2721. r8152_aldps_en(tp, false);
  2722. if (tp->version == RTL_VER_01) {
  2723. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2724. ocp_data &= ~LED_MODE_MASK;
  2725. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2726. }
  2727. r8152_power_cut_en(tp, false);
  2728. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2729. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  2730. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2731. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  2732. ocp_data &= ~MCU_CLK_RATIO_MASK;
  2733. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  2734. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  2735. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  2736. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  2737. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  2738. rtl_tally_reset(tp);
  2739. /* enable rx aggregation */
  2740. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2741. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  2742. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2743. }
  2744. static void r8153_init(struct r8152 *tp)
  2745. {
  2746. u32 ocp_data;
  2747. u16 data;
  2748. int i;
  2749. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2750. return;
  2751. r8153_u1u2en(tp, false);
  2752. for (i = 0; i < 500; i++) {
  2753. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  2754. AUTOLOAD_DONE)
  2755. break;
  2756. msleep(20);
  2757. }
  2758. for (i = 0; i < 500; i++) {
  2759. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  2760. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  2761. break;
  2762. msleep(20);
  2763. }
  2764. if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
  2765. tp->version == RTL_VER_05)
  2766. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  2767. data = r8152_mdio_read(tp, MII_BMCR);
  2768. if (data & BMCR_PDOWN) {
  2769. data &= ~BMCR_PDOWN;
  2770. r8152_mdio_write(tp, MII_BMCR, data);
  2771. }
  2772. for (i = 0; i < 500; i++) {
  2773. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  2774. if (ocp_data == PHY_STAT_LAN_ON)
  2775. break;
  2776. msleep(20);
  2777. }
  2778. usb_disable_lpm(tp->udev);
  2779. r8153_u2p3en(tp, false);
  2780. if (tp->version == RTL_VER_04) {
  2781. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
  2782. ocp_data &= ~pwd_dn_scale_mask;
  2783. ocp_data |= pwd_dn_scale(96);
  2784. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
  2785. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  2786. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  2787. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  2788. } else if (tp->version == RTL_VER_05) {
  2789. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
  2790. ocp_data &= ~ECM_ALDPS;
  2791. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
  2792. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2793. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2794. ocp_data &= ~DYNAMIC_BURST;
  2795. else
  2796. ocp_data |= DYNAMIC_BURST;
  2797. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2798. } else if (tp->version == RTL_VER_06) {
  2799. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2800. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2801. ocp_data &= ~DYNAMIC_BURST;
  2802. else
  2803. ocp_data |= DYNAMIC_BURST;
  2804. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2805. }
  2806. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
  2807. ocp_data |= EP4_FULL_FC;
  2808. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
  2809. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  2810. ocp_data &= ~TIMER11_EN;
  2811. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  2812. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2813. ocp_data &= ~LED_MODE_MASK;
  2814. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2815. ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
  2816. if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
  2817. ocp_data |= LPM_TIMER_500MS;
  2818. else
  2819. ocp_data |= LPM_TIMER_500US;
  2820. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  2821. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  2822. ocp_data &= ~SEN_VAL_MASK;
  2823. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  2824. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  2825. ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
  2826. r8153_power_cut_en(tp, false);
  2827. r8153_u1u2en(tp, true);
  2828. /* MAC clock speed down */
  2829. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
  2830. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
  2831. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
  2832. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
  2833. rtl_tally_reset(tp);
  2834. r8153_u2p3en(tp, true);
  2835. }
  2836. static int rtl8152_pre_reset(struct usb_interface *intf)
  2837. {
  2838. struct r8152 *tp = usb_get_intfdata(intf);
  2839. struct net_device *netdev;
  2840. if (!tp)
  2841. return 0;
  2842. netdev = tp->netdev;
  2843. if (!netif_running(netdev))
  2844. return 0;
  2845. netif_stop_queue(netdev);
  2846. napi_disable(&tp->napi);
  2847. clear_bit(WORK_ENABLE, &tp->flags);
  2848. usb_kill_urb(tp->intr_urb);
  2849. cancel_delayed_work_sync(&tp->schedule);
  2850. if (netif_carrier_ok(netdev)) {
  2851. mutex_lock(&tp->control);
  2852. tp->rtl_ops.disable(tp);
  2853. mutex_unlock(&tp->control);
  2854. }
  2855. return 0;
  2856. }
  2857. static int rtl8152_post_reset(struct usb_interface *intf)
  2858. {
  2859. struct r8152 *tp = usb_get_intfdata(intf);
  2860. struct net_device *netdev;
  2861. if (!tp)
  2862. return 0;
  2863. netdev = tp->netdev;
  2864. if (!netif_running(netdev))
  2865. return 0;
  2866. set_bit(WORK_ENABLE, &tp->flags);
  2867. if (netif_carrier_ok(netdev)) {
  2868. mutex_lock(&tp->control);
  2869. tp->rtl_ops.enable(tp);
  2870. rtl_start_rx(tp);
  2871. rtl8152_set_rx_mode(netdev);
  2872. mutex_unlock(&tp->control);
  2873. }
  2874. napi_enable(&tp->napi);
  2875. netif_wake_queue(netdev);
  2876. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2877. if (!list_empty(&tp->rx_done))
  2878. napi_schedule(&tp->napi);
  2879. return 0;
  2880. }
  2881. static bool delay_autosuspend(struct r8152 *tp)
  2882. {
  2883. bool sw_linking = !!netif_carrier_ok(tp->netdev);
  2884. bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
  2885. /* This means a linking change occurs and the driver doesn't detect it,
  2886. * yet. If the driver has disabled tx/rx and hw is linking on, the
  2887. * device wouldn't wake up by receiving any packet.
  2888. */
  2889. if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
  2890. return true;
  2891. /* If the linking down is occurred by nway, the device may miss the
  2892. * linking change event. And it wouldn't wake when linking on.
  2893. */
  2894. if (!sw_linking && tp->rtl_ops.in_nway(tp))
  2895. return true;
  2896. else if (!skb_queue_empty(&tp->tx_queue))
  2897. return true;
  2898. else
  2899. return false;
  2900. }
  2901. static int rtl8152_rumtime_suspend(struct r8152 *tp)
  2902. {
  2903. struct net_device *netdev = tp->netdev;
  2904. int ret = 0;
  2905. set_bit(SELECTIVE_SUSPEND, &tp->flags);
  2906. smp_mb__after_atomic();
  2907. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2908. u32 rcr = 0;
  2909. if (delay_autosuspend(tp)) {
  2910. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2911. smp_mb__after_atomic();
  2912. ret = -EBUSY;
  2913. goto out1;
  2914. }
  2915. if (netif_carrier_ok(netdev)) {
  2916. u32 ocp_data;
  2917. rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2918. ocp_data = rcr & ~RCR_ACPT_ALL;
  2919. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2920. rxdy_gated_en(tp, true);
  2921. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
  2922. PLA_OOB_CTRL);
  2923. if (!(ocp_data & RXFIFO_EMPTY)) {
  2924. rxdy_gated_en(tp, false);
  2925. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
  2926. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2927. smp_mb__after_atomic();
  2928. ret = -EBUSY;
  2929. goto out1;
  2930. }
  2931. }
  2932. clear_bit(WORK_ENABLE, &tp->flags);
  2933. usb_kill_urb(tp->intr_urb);
  2934. tp->rtl_ops.autosuspend_en(tp, true);
  2935. if (netif_carrier_ok(netdev)) {
  2936. napi_disable(&tp->napi);
  2937. rtl_stop_rx(tp);
  2938. rxdy_gated_en(tp, false);
  2939. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
  2940. napi_enable(&tp->napi);
  2941. }
  2942. }
  2943. out1:
  2944. return ret;
  2945. }
  2946. static int rtl8152_system_suspend(struct r8152 *tp)
  2947. {
  2948. struct net_device *netdev = tp->netdev;
  2949. int ret = 0;
  2950. netif_device_detach(netdev);
  2951. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2952. clear_bit(WORK_ENABLE, &tp->flags);
  2953. usb_kill_urb(tp->intr_urb);
  2954. napi_disable(&tp->napi);
  2955. cancel_delayed_work_sync(&tp->schedule);
  2956. tp->rtl_ops.down(tp);
  2957. napi_enable(&tp->napi);
  2958. }
  2959. return ret;
  2960. }
  2961. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  2962. {
  2963. struct r8152 *tp = usb_get_intfdata(intf);
  2964. int ret;
  2965. mutex_lock(&tp->control);
  2966. if (PMSG_IS_AUTO(message))
  2967. ret = rtl8152_rumtime_suspend(tp);
  2968. else
  2969. ret = rtl8152_system_suspend(tp);
  2970. mutex_unlock(&tp->control);
  2971. return ret;
  2972. }
  2973. static int rtl8152_resume(struct usb_interface *intf)
  2974. {
  2975. struct r8152 *tp = usb_get_intfdata(intf);
  2976. mutex_lock(&tp->control);
  2977. if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2978. tp->rtl_ops.init(tp);
  2979. queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
  2980. netif_device_attach(tp->netdev);
  2981. }
  2982. if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) {
  2983. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2984. tp->rtl_ops.autosuspend_en(tp, false);
  2985. napi_disable(&tp->napi);
  2986. set_bit(WORK_ENABLE, &tp->flags);
  2987. if (netif_carrier_ok(tp->netdev)) {
  2988. if (rtl8152_get_speed(tp) & LINK_STATUS) {
  2989. rtl_start_rx(tp);
  2990. } else {
  2991. netif_carrier_off(tp->netdev);
  2992. tp->rtl_ops.disable(tp);
  2993. netif_info(tp, link, tp->netdev,
  2994. "linking down\n");
  2995. }
  2996. }
  2997. napi_enable(&tp->napi);
  2998. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2999. smp_mb__after_atomic();
  3000. if (!list_empty(&tp->rx_done))
  3001. napi_schedule(&tp->napi);
  3002. } else {
  3003. tp->rtl_ops.up(tp);
  3004. netif_carrier_off(tp->netdev);
  3005. set_bit(WORK_ENABLE, &tp->flags);
  3006. }
  3007. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  3008. } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  3009. if (tp->netdev->flags & IFF_UP)
  3010. tp->rtl_ops.autosuspend_en(tp, false);
  3011. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  3012. }
  3013. mutex_unlock(&tp->control);
  3014. return 0;
  3015. }
  3016. static int rtl8152_reset_resume(struct usb_interface *intf)
  3017. {
  3018. struct r8152 *tp = usb_get_intfdata(intf);
  3019. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  3020. return rtl8152_resume(intf);
  3021. }
  3022. static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  3023. {
  3024. struct r8152 *tp = netdev_priv(dev);
  3025. if (usb_autopm_get_interface(tp->intf) < 0)
  3026. return;
  3027. if (!rtl_can_wakeup(tp)) {
  3028. wol->supported = 0;
  3029. wol->wolopts = 0;
  3030. } else {
  3031. mutex_lock(&tp->control);
  3032. wol->supported = WAKE_ANY;
  3033. wol->wolopts = __rtl_get_wol(tp);
  3034. mutex_unlock(&tp->control);
  3035. }
  3036. usb_autopm_put_interface(tp->intf);
  3037. }
  3038. static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  3039. {
  3040. struct r8152 *tp = netdev_priv(dev);
  3041. int ret;
  3042. if (!rtl_can_wakeup(tp))
  3043. return -EOPNOTSUPP;
  3044. ret = usb_autopm_get_interface(tp->intf);
  3045. if (ret < 0)
  3046. goto out_set_wol;
  3047. mutex_lock(&tp->control);
  3048. __rtl_set_wol(tp, wol->wolopts);
  3049. tp->saved_wolopts = wol->wolopts & WAKE_ANY;
  3050. mutex_unlock(&tp->control);
  3051. usb_autopm_put_interface(tp->intf);
  3052. out_set_wol:
  3053. return ret;
  3054. }
  3055. static u32 rtl8152_get_msglevel(struct net_device *dev)
  3056. {
  3057. struct r8152 *tp = netdev_priv(dev);
  3058. return tp->msg_enable;
  3059. }
  3060. static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
  3061. {
  3062. struct r8152 *tp = netdev_priv(dev);
  3063. tp->msg_enable = value;
  3064. }
  3065. static void rtl8152_get_drvinfo(struct net_device *netdev,
  3066. struct ethtool_drvinfo *info)
  3067. {
  3068. struct r8152 *tp = netdev_priv(netdev);
  3069. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  3070. strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
  3071. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  3072. }
  3073. static
  3074. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  3075. {
  3076. struct r8152 *tp = netdev_priv(netdev);
  3077. int ret;
  3078. if (!tp->mii.mdio_read)
  3079. return -EOPNOTSUPP;
  3080. ret = usb_autopm_get_interface(tp->intf);
  3081. if (ret < 0)
  3082. goto out;
  3083. mutex_lock(&tp->control);
  3084. ret = mii_ethtool_gset(&tp->mii, cmd);
  3085. mutex_unlock(&tp->control);
  3086. usb_autopm_put_interface(tp->intf);
  3087. out:
  3088. return ret;
  3089. }
  3090. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  3091. {
  3092. struct r8152 *tp = netdev_priv(dev);
  3093. int ret;
  3094. ret = usb_autopm_get_interface(tp->intf);
  3095. if (ret < 0)
  3096. goto out;
  3097. mutex_lock(&tp->control);
  3098. ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  3099. if (!ret) {
  3100. tp->autoneg = cmd->autoneg;
  3101. tp->speed = cmd->speed;
  3102. tp->duplex = cmd->duplex;
  3103. }
  3104. mutex_unlock(&tp->control);
  3105. usb_autopm_put_interface(tp->intf);
  3106. out:
  3107. return ret;
  3108. }
  3109. static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
  3110. "tx_packets",
  3111. "rx_packets",
  3112. "tx_errors",
  3113. "rx_errors",
  3114. "rx_missed",
  3115. "align_errors",
  3116. "tx_single_collisions",
  3117. "tx_multi_collisions",
  3118. "rx_unicast",
  3119. "rx_broadcast",
  3120. "rx_multicast",
  3121. "tx_aborted",
  3122. "tx_underrun",
  3123. };
  3124. static int rtl8152_get_sset_count(struct net_device *dev, int sset)
  3125. {
  3126. switch (sset) {
  3127. case ETH_SS_STATS:
  3128. return ARRAY_SIZE(rtl8152_gstrings);
  3129. default:
  3130. return -EOPNOTSUPP;
  3131. }
  3132. }
  3133. static void rtl8152_get_ethtool_stats(struct net_device *dev,
  3134. struct ethtool_stats *stats, u64 *data)
  3135. {
  3136. struct r8152 *tp = netdev_priv(dev);
  3137. struct tally_counter tally;
  3138. if (usb_autopm_get_interface(tp->intf) < 0)
  3139. return;
  3140. generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
  3141. usb_autopm_put_interface(tp->intf);
  3142. data[0] = le64_to_cpu(tally.tx_packets);
  3143. data[1] = le64_to_cpu(tally.rx_packets);
  3144. data[2] = le64_to_cpu(tally.tx_errors);
  3145. data[3] = le32_to_cpu(tally.rx_errors);
  3146. data[4] = le16_to_cpu(tally.rx_missed);
  3147. data[5] = le16_to_cpu(tally.align_errors);
  3148. data[6] = le32_to_cpu(tally.tx_one_collision);
  3149. data[7] = le32_to_cpu(tally.tx_multi_collision);
  3150. data[8] = le64_to_cpu(tally.rx_unicast);
  3151. data[9] = le64_to_cpu(tally.rx_broadcast);
  3152. data[10] = le32_to_cpu(tally.rx_multicast);
  3153. data[11] = le16_to_cpu(tally.tx_aborted);
  3154. data[12] = le16_to_cpu(tally.tx_underrun);
  3155. }
  3156. static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3157. {
  3158. switch (stringset) {
  3159. case ETH_SS_STATS:
  3160. memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
  3161. break;
  3162. }
  3163. }
  3164. static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3165. {
  3166. u32 ocp_data, lp, adv, supported = 0;
  3167. u16 val;
  3168. val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
  3169. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  3170. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
  3171. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  3172. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
  3173. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  3174. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  3175. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  3176. eee->eee_enabled = !!ocp_data;
  3177. eee->eee_active = !!(supported & adv & lp);
  3178. eee->supported = supported;
  3179. eee->advertised = adv;
  3180. eee->lp_advertised = lp;
  3181. return 0;
  3182. }
  3183. static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3184. {
  3185. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  3186. r8152_eee_en(tp, eee->eee_enabled);
  3187. if (!eee->eee_enabled)
  3188. val = 0;
  3189. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  3190. return 0;
  3191. }
  3192. static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3193. {
  3194. u32 ocp_data, lp, adv, supported = 0;
  3195. u16 val;
  3196. val = ocp_reg_read(tp, OCP_EEE_ABLE);
  3197. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  3198. val = ocp_reg_read(tp, OCP_EEE_ADV);
  3199. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  3200. val = ocp_reg_read(tp, OCP_EEE_LPABLE);
  3201. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  3202. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  3203. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  3204. eee->eee_enabled = !!ocp_data;
  3205. eee->eee_active = !!(supported & adv & lp);
  3206. eee->supported = supported;
  3207. eee->advertised = adv;
  3208. eee->lp_advertised = lp;
  3209. return 0;
  3210. }
  3211. static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3212. {
  3213. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  3214. r8153_eee_en(tp, eee->eee_enabled);
  3215. if (!eee->eee_enabled)
  3216. val = 0;
  3217. ocp_reg_write(tp, OCP_EEE_ADV, val);
  3218. return 0;
  3219. }
  3220. static int
  3221. rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
  3222. {
  3223. struct r8152 *tp = netdev_priv(net);
  3224. int ret;
  3225. ret = usb_autopm_get_interface(tp->intf);
  3226. if (ret < 0)
  3227. goto out;
  3228. mutex_lock(&tp->control);
  3229. ret = tp->rtl_ops.eee_get(tp, edata);
  3230. mutex_unlock(&tp->control);
  3231. usb_autopm_put_interface(tp->intf);
  3232. out:
  3233. return ret;
  3234. }
  3235. static int
  3236. rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
  3237. {
  3238. struct r8152 *tp = netdev_priv(net);
  3239. int ret;
  3240. ret = usb_autopm_get_interface(tp->intf);
  3241. if (ret < 0)
  3242. goto out;
  3243. mutex_lock(&tp->control);
  3244. ret = tp->rtl_ops.eee_set(tp, edata);
  3245. if (!ret)
  3246. ret = mii_nway_restart(&tp->mii);
  3247. mutex_unlock(&tp->control);
  3248. usb_autopm_put_interface(tp->intf);
  3249. out:
  3250. return ret;
  3251. }
  3252. static int rtl8152_nway_reset(struct net_device *dev)
  3253. {
  3254. struct r8152 *tp = netdev_priv(dev);
  3255. int ret;
  3256. ret = usb_autopm_get_interface(tp->intf);
  3257. if (ret < 0)
  3258. goto out;
  3259. mutex_lock(&tp->control);
  3260. ret = mii_nway_restart(&tp->mii);
  3261. mutex_unlock(&tp->control);
  3262. usb_autopm_put_interface(tp->intf);
  3263. out:
  3264. return ret;
  3265. }
  3266. static int rtl8152_get_coalesce(struct net_device *netdev,
  3267. struct ethtool_coalesce *coalesce)
  3268. {
  3269. struct r8152 *tp = netdev_priv(netdev);
  3270. switch (tp->version) {
  3271. case RTL_VER_01:
  3272. case RTL_VER_02:
  3273. return -EOPNOTSUPP;
  3274. default:
  3275. break;
  3276. }
  3277. coalesce->rx_coalesce_usecs = tp->coalesce;
  3278. return 0;
  3279. }
  3280. static int rtl8152_set_coalesce(struct net_device *netdev,
  3281. struct ethtool_coalesce *coalesce)
  3282. {
  3283. struct r8152 *tp = netdev_priv(netdev);
  3284. int ret;
  3285. switch (tp->version) {
  3286. case RTL_VER_01:
  3287. case RTL_VER_02:
  3288. return -EOPNOTSUPP;
  3289. default:
  3290. break;
  3291. }
  3292. if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
  3293. return -EINVAL;
  3294. ret = usb_autopm_get_interface(tp->intf);
  3295. if (ret < 0)
  3296. return ret;
  3297. mutex_lock(&tp->control);
  3298. if (tp->coalesce != coalesce->rx_coalesce_usecs) {
  3299. tp->coalesce = coalesce->rx_coalesce_usecs;
  3300. if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
  3301. r8153_set_rx_early_timeout(tp);
  3302. }
  3303. mutex_unlock(&tp->control);
  3304. usb_autopm_put_interface(tp->intf);
  3305. return ret;
  3306. }
  3307. static const struct ethtool_ops ops = {
  3308. .get_drvinfo = rtl8152_get_drvinfo,
  3309. .get_settings = rtl8152_get_settings,
  3310. .set_settings = rtl8152_set_settings,
  3311. .get_link = ethtool_op_get_link,
  3312. .nway_reset = rtl8152_nway_reset,
  3313. .get_msglevel = rtl8152_get_msglevel,
  3314. .set_msglevel = rtl8152_set_msglevel,
  3315. .get_wol = rtl8152_get_wol,
  3316. .set_wol = rtl8152_set_wol,
  3317. .get_strings = rtl8152_get_strings,
  3318. .get_sset_count = rtl8152_get_sset_count,
  3319. .get_ethtool_stats = rtl8152_get_ethtool_stats,
  3320. .get_coalesce = rtl8152_get_coalesce,
  3321. .set_coalesce = rtl8152_set_coalesce,
  3322. .get_eee = rtl_ethtool_get_eee,
  3323. .set_eee = rtl_ethtool_set_eee,
  3324. };
  3325. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  3326. {
  3327. struct r8152 *tp = netdev_priv(netdev);
  3328. struct mii_ioctl_data *data = if_mii(rq);
  3329. int res;
  3330. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3331. return -ENODEV;
  3332. res = usb_autopm_get_interface(tp->intf);
  3333. if (res < 0)
  3334. goto out;
  3335. switch (cmd) {
  3336. case SIOCGMIIPHY:
  3337. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  3338. break;
  3339. case SIOCGMIIREG:
  3340. mutex_lock(&tp->control);
  3341. data->val_out = r8152_mdio_read(tp, data->reg_num);
  3342. mutex_unlock(&tp->control);
  3343. break;
  3344. case SIOCSMIIREG:
  3345. if (!capable(CAP_NET_ADMIN)) {
  3346. res = -EPERM;
  3347. break;
  3348. }
  3349. mutex_lock(&tp->control);
  3350. r8152_mdio_write(tp, data->reg_num, data->val_in);
  3351. mutex_unlock(&tp->control);
  3352. break;
  3353. default:
  3354. res = -EOPNOTSUPP;
  3355. }
  3356. usb_autopm_put_interface(tp->intf);
  3357. out:
  3358. return res;
  3359. }
  3360. static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
  3361. {
  3362. struct r8152 *tp = netdev_priv(dev);
  3363. int ret;
  3364. switch (tp->version) {
  3365. case RTL_VER_01:
  3366. case RTL_VER_02:
  3367. return eth_change_mtu(dev, new_mtu);
  3368. default:
  3369. break;
  3370. }
  3371. if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
  3372. return -EINVAL;
  3373. ret = usb_autopm_get_interface(tp->intf);
  3374. if (ret < 0)
  3375. return ret;
  3376. mutex_lock(&tp->control);
  3377. dev->mtu = new_mtu;
  3378. if (netif_running(dev) && netif_carrier_ok(dev))
  3379. r8153_set_rx_early_size(tp);
  3380. mutex_unlock(&tp->control);
  3381. usb_autopm_put_interface(tp->intf);
  3382. return ret;
  3383. }
  3384. static const struct net_device_ops rtl8152_netdev_ops = {
  3385. .ndo_open = rtl8152_open,
  3386. .ndo_stop = rtl8152_close,
  3387. .ndo_do_ioctl = rtl8152_ioctl,
  3388. .ndo_start_xmit = rtl8152_start_xmit,
  3389. .ndo_tx_timeout = rtl8152_tx_timeout,
  3390. .ndo_set_features = rtl8152_set_features,
  3391. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  3392. .ndo_set_mac_address = rtl8152_set_mac_address,
  3393. .ndo_change_mtu = rtl8152_change_mtu,
  3394. .ndo_validate_addr = eth_validate_addr,
  3395. .ndo_features_check = rtl8152_features_check,
  3396. };
  3397. static void r8152b_get_version(struct r8152 *tp)
  3398. {
  3399. u32 ocp_data;
  3400. u16 version;
  3401. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  3402. version = (u16)(ocp_data & VERSION_MASK);
  3403. switch (version) {
  3404. case 0x4c00:
  3405. tp->version = RTL_VER_01;
  3406. break;
  3407. case 0x4c10:
  3408. tp->version = RTL_VER_02;
  3409. break;
  3410. case 0x5c00:
  3411. tp->version = RTL_VER_03;
  3412. tp->mii.supports_gmii = 1;
  3413. break;
  3414. case 0x5c10:
  3415. tp->version = RTL_VER_04;
  3416. tp->mii.supports_gmii = 1;
  3417. break;
  3418. case 0x5c20:
  3419. tp->version = RTL_VER_05;
  3420. tp->mii.supports_gmii = 1;
  3421. break;
  3422. case 0x5c30:
  3423. tp->version = RTL_VER_06;
  3424. tp->mii.supports_gmii = 1;
  3425. break;
  3426. default:
  3427. netif_info(tp, probe, tp->netdev,
  3428. "Unknown version 0x%04x\n", version);
  3429. break;
  3430. }
  3431. }
  3432. static void rtl8152_unload(struct r8152 *tp)
  3433. {
  3434. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3435. return;
  3436. if (tp->version != RTL_VER_01)
  3437. r8152_power_cut_en(tp, true);
  3438. }
  3439. static void rtl8153_unload(struct r8152 *tp)
  3440. {
  3441. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3442. return;
  3443. r8153_power_cut_en(tp, false);
  3444. }
  3445. static int rtl_ops_init(struct r8152 *tp)
  3446. {
  3447. struct rtl_ops *ops = &tp->rtl_ops;
  3448. int ret = 0;
  3449. switch (tp->version) {
  3450. case RTL_VER_01:
  3451. case RTL_VER_02:
  3452. ops->init = r8152b_init;
  3453. ops->enable = rtl8152_enable;
  3454. ops->disable = rtl8152_disable;
  3455. ops->up = rtl8152_up;
  3456. ops->down = rtl8152_down;
  3457. ops->unload = rtl8152_unload;
  3458. ops->eee_get = r8152_get_eee;
  3459. ops->eee_set = r8152_set_eee;
  3460. ops->in_nway = rtl8152_in_nway;
  3461. ops->hw_phy_cfg = r8152b_hw_phy_cfg;
  3462. ops->autosuspend_en = rtl_runtime_suspend_enable;
  3463. break;
  3464. case RTL_VER_03:
  3465. case RTL_VER_04:
  3466. case RTL_VER_05:
  3467. case RTL_VER_06:
  3468. ops->init = r8153_init;
  3469. ops->enable = rtl8153_enable;
  3470. ops->disable = rtl8153_disable;
  3471. ops->up = rtl8153_up;
  3472. ops->down = rtl8153_down;
  3473. ops->unload = rtl8153_unload;
  3474. ops->eee_get = r8153_get_eee;
  3475. ops->eee_set = r8153_set_eee;
  3476. ops->in_nway = rtl8153_in_nway;
  3477. ops->hw_phy_cfg = r8153_hw_phy_cfg;
  3478. ops->autosuspend_en = rtl8153_runtime_enable;
  3479. break;
  3480. default:
  3481. ret = -ENODEV;
  3482. netif_err(tp, probe, tp->netdev, "Unknown Device\n");
  3483. break;
  3484. }
  3485. return ret;
  3486. }
  3487. static int rtl8152_probe(struct usb_interface *intf,
  3488. const struct usb_device_id *id)
  3489. {
  3490. struct usb_device *udev = interface_to_usbdev(intf);
  3491. struct r8152 *tp;
  3492. struct net_device *netdev;
  3493. int ret;
  3494. if (udev->actconfig->desc.bConfigurationValue != 1) {
  3495. usb_driver_set_configuration(udev, 1);
  3496. return -ENODEV;
  3497. }
  3498. usb_reset_device(udev);
  3499. netdev = alloc_etherdev(sizeof(struct r8152));
  3500. if (!netdev) {
  3501. dev_err(&intf->dev, "Out of memory\n");
  3502. return -ENOMEM;
  3503. }
  3504. SET_NETDEV_DEV(netdev, &intf->dev);
  3505. tp = netdev_priv(netdev);
  3506. tp->msg_enable = 0x7FFF;
  3507. tp->udev = udev;
  3508. tp->netdev = netdev;
  3509. tp->intf = intf;
  3510. r8152b_get_version(tp);
  3511. ret = rtl_ops_init(tp);
  3512. if (ret)
  3513. goto out;
  3514. mutex_init(&tp->control);
  3515. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  3516. INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
  3517. netdev->netdev_ops = &rtl8152_netdev_ops;
  3518. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  3519. netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3520. NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
  3521. NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  3522. NETIF_F_HW_VLAN_CTAG_TX;
  3523. netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3524. NETIF_F_TSO | NETIF_F_FRAGLIST |
  3525. NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
  3526. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
  3527. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  3528. NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
  3529. NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  3530. if (tp->version == RTL_VER_01) {
  3531. netdev->features &= ~NETIF_F_RXCSUM;
  3532. netdev->hw_features &= ~NETIF_F_RXCSUM;
  3533. }
  3534. netdev->ethtool_ops = &ops;
  3535. netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
  3536. tp->mii.dev = netdev;
  3537. tp->mii.mdio_read = read_mii_word;
  3538. tp->mii.mdio_write = write_mii_word;
  3539. tp->mii.phy_id_mask = 0x3f;
  3540. tp->mii.reg_num_mask = 0x1f;
  3541. tp->mii.phy_id = R8152_PHY_ID;
  3542. switch (udev->speed) {
  3543. case USB_SPEED_SUPER:
  3544. case USB_SPEED_SUPER_PLUS:
  3545. tp->coalesce = COALESCE_SUPER;
  3546. break;
  3547. case USB_SPEED_HIGH:
  3548. tp->coalesce = COALESCE_HIGH;
  3549. break;
  3550. default:
  3551. tp->coalesce = COALESCE_SLOW;
  3552. break;
  3553. }
  3554. tp->autoneg = AUTONEG_ENABLE;
  3555. tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
  3556. tp->duplex = DUPLEX_FULL;
  3557. intf->needs_remote_wakeup = 1;
  3558. tp->rtl_ops.init(tp);
  3559. queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
  3560. set_ethernet_addr(tp);
  3561. usb_set_intfdata(intf, tp);
  3562. netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
  3563. ret = register_netdev(netdev);
  3564. if (ret != 0) {
  3565. netif_err(tp, probe, netdev, "couldn't register the device\n");
  3566. goto out1;
  3567. }
  3568. if (!rtl_can_wakeup(tp))
  3569. __rtl_set_wol(tp, 0);
  3570. tp->saved_wolopts = __rtl_get_wol(tp);
  3571. if (tp->saved_wolopts)
  3572. device_set_wakeup_enable(&udev->dev, true);
  3573. else
  3574. device_set_wakeup_enable(&udev->dev, false);
  3575. netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
  3576. return 0;
  3577. out1:
  3578. netif_napi_del(&tp->napi);
  3579. usb_set_intfdata(intf, NULL);
  3580. out:
  3581. free_netdev(netdev);
  3582. return ret;
  3583. }
  3584. static void rtl8152_disconnect(struct usb_interface *intf)
  3585. {
  3586. struct r8152 *tp = usb_get_intfdata(intf);
  3587. usb_set_intfdata(intf, NULL);
  3588. if (tp) {
  3589. struct usb_device *udev = tp->udev;
  3590. if (udev->state == USB_STATE_NOTATTACHED)
  3591. set_bit(RTL8152_UNPLUG, &tp->flags);
  3592. netif_napi_del(&tp->napi);
  3593. unregister_netdev(tp->netdev);
  3594. cancel_delayed_work_sync(&tp->hw_phy_work);
  3595. tp->rtl_ops.unload(tp);
  3596. free_netdev(tp->netdev);
  3597. }
  3598. }
  3599. #define REALTEK_USB_DEVICE(vend, prod) \
  3600. .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
  3601. USB_DEVICE_ID_MATCH_INT_CLASS, \
  3602. .idVendor = (vend), \
  3603. .idProduct = (prod), \
  3604. .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
  3605. }, \
  3606. { \
  3607. .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
  3608. USB_DEVICE_ID_MATCH_DEVICE, \
  3609. .idVendor = (vend), \
  3610. .idProduct = (prod), \
  3611. .bInterfaceClass = USB_CLASS_COMM, \
  3612. .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
  3613. .bInterfaceProtocol = USB_CDC_PROTO_NONE
  3614. /* table of devices that work with this driver */
  3615. static struct usb_device_id rtl8152_table[] = {
  3616. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
  3617. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
  3618. {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
  3619. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
  3620. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
  3621. {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
  3622. {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
  3623. {}
  3624. };
  3625. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  3626. static struct usb_driver rtl8152_driver = {
  3627. .name = MODULENAME,
  3628. .id_table = rtl8152_table,
  3629. .probe = rtl8152_probe,
  3630. .disconnect = rtl8152_disconnect,
  3631. .suspend = rtl8152_suspend,
  3632. .resume = rtl8152_resume,
  3633. .reset_resume = rtl8152_reset_resume,
  3634. .pre_reset = rtl8152_pre_reset,
  3635. .post_reset = rtl8152_post_reset,
  3636. .supports_autosuspend = 1,
  3637. .disable_hub_initiated_lpm = 1,
  3638. };
  3639. module_usb_driver(rtl8152_driver);
  3640. MODULE_AUTHOR(DRIVER_AUTHOR);
  3641. MODULE_DESCRIPTION(DRIVER_DESC);
  3642. MODULE_LICENSE("GPL");
  3643. MODULE_VERSION(DRIVER_VERSION);