rrunner.c 41 KB

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  1. /*
  2. * rrunner.c: Linux driver for the Essential RoadRunner HIPPI board.
  3. *
  4. * Copyright (C) 1998-2002 by Jes Sorensen, <jes@wildopensource.com>.
  5. *
  6. * Thanks to Essential Communication for providing us with hardware
  7. * and very comprehensive documentation without which I would not have
  8. * been able to write this driver. A special thank you to John Gibbon
  9. * for sorting out the legal issues, with the NDA, allowing the code to
  10. * be released under the GPL.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * Thanks to Jayaram Bhat from ODS/Essential for fixing some of the
  18. * stupid bugs in my code.
  19. *
  20. * Softnet support and various other patches from Val Henson of
  21. * ODS/Essential.
  22. *
  23. * PCI DMA mapping code partly based on work by Francois Romieu.
  24. */
  25. #define DEBUG 1
  26. #define RX_DMA_SKBUFF 1
  27. #define PKT_COPY_THRESHOLD 512
  28. #include <linux/module.h>
  29. #include <linux/types.h>
  30. #include <linux/errno.h>
  31. #include <linux/ioport.h>
  32. #include <linux/pci.h>
  33. #include <linux/kernel.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/hippidevice.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/delay.h>
  38. #include <linux/mm.h>
  39. #include <linux/slab.h>
  40. #include <net/sock.h>
  41. #include <asm/cache.h>
  42. #include <asm/byteorder.h>
  43. #include <asm/io.h>
  44. #include <asm/irq.h>
  45. #include <asm/uaccess.h>
  46. #define rr_if_busy(dev) netif_queue_stopped(dev)
  47. #define rr_if_running(dev) netif_running(dev)
  48. #include "rrunner.h"
  49. #define RUN_AT(x) (jiffies + (x))
  50. MODULE_AUTHOR("Jes Sorensen <jes@wildopensource.com>");
  51. MODULE_DESCRIPTION("Essential RoadRunner HIPPI driver");
  52. MODULE_LICENSE("GPL");
  53. static char version[] = "rrunner.c: v0.50 11/11/2002 Jes Sorensen (jes@wildopensource.com)\n";
  54. static const struct net_device_ops rr_netdev_ops = {
  55. .ndo_open = rr_open,
  56. .ndo_stop = rr_close,
  57. .ndo_do_ioctl = rr_ioctl,
  58. .ndo_start_xmit = rr_start_xmit,
  59. .ndo_change_mtu = hippi_change_mtu,
  60. .ndo_set_mac_address = hippi_mac_addr,
  61. };
  62. /*
  63. * Implementation notes:
  64. *
  65. * The DMA engine only allows for DMA within physical 64KB chunks of
  66. * memory. The current approach of the driver (and stack) is to use
  67. * linear blocks of memory for the skbuffs. However, as the data block
  68. * is always the first part of the skb and skbs are 2^n aligned so we
  69. * are guarantted to get the whole block within one 64KB align 64KB
  70. * chunk.
  71. *
  72. * On the long term, relying on being able to allocate 64KB linear
  73. * chunks of memory is not feasible and the skb handling code and the
  74. * stack will need to know about I/O vectors or something similar.
  75. */
  76. static int rr_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  77. {
  78. struct net_device *dev;
  79. static int version_disp;
  80. u8 pci_latency;
  81. struct rr_private *rrpriv;
  82. void *tmpptr;
  83. dma_addr_t ring_dma;
  84. int ret = -ENOMEM;
  85. dev = alloc_hippi_dev(sizeof(struct rr_private));
  86. if (!dev)
  87. goto out3;
  88. ret = pci_enable_device(pdev);
  89. if (ret) {
  90. ret = -ENODEV;
  91. goto out2;
  92. }
  93. rrpriv = netdev_priv(dev);
  94. SET_NETDEV_DEV(dev, &pdev->dev);
  95. ret = pci_request_regions(pdev, "rrunner");
  96. if (ret < 0)
  97. goto out;
  98. pci_set_drvdata(pdev, dev);
  99. rrpriv->pci_dev = pdev;
  100. spin_lock_init(&rrpriv->lock);
  101. dev->netdev_ops = &rr_netdev_ops;
  102. /* display version info if adapter is found */
  103. if (!version_disp) {
  104. /* set display flag to TRUE so that */
  105. /* we only display this string ONCE */
  106. version_disp = 1;
  107. printk(version);
  108. }
  109. pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
  110. if (pci_latency <= 0x58){
  111. pci_latency = 0x58;
  112. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, pci_latency);
  113. }
  114. pci_set_master(pdev);
  115. printk(KERN_INFO "%s: Essential RoadRunner serial HIPPI "
  116. "at 0x%llx, irq %i, PCI latency %i\n", dev->name,
  117. (unsigned long long)pci_resource_start(pdev, 0),
  118. pdev->irq, pci_latency);
  119. /*
  120. * Remap the MMIO regs into kernel space.
  121. */
  122. rrpriv->regs = pci_iomap(pdev, 0, 0x1000);
  123. if (!rrpriv->regs) {
  124. printk(KERN_ERR "%s: Unable to map I/O register, "
  125. "RoadRunner will be disabled.\n", dev->name);
  126. ret = -EIO;
  127. goto out;
  128. }
  129. tmpptr = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
  130. rrpriv->tx_ring = tmpptr;
  131. rrpriv->tx_ring_dma = ring_dma;
  132. if (!tmpptr) {
  133. ret = -ENOMEM;
  134. goto out;
  135. }
  136. tmpptr = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
  137. rrpriv->rx_ring = tmpptr;
  138. rrpriv->rx_ring_dma = ring_dma;
  139. if (!tmpptr) {
  140. ret = -ENOMEM;
  141. goto out;
  142. }
  143. tmpptr = pci_alloc_consistent(pdev, EVT_RING_SIZE, &ring_dma);
  144. rrpriv->evt_ring = tmpptr;
  145. rrpriv->evt_ring_dma = ring_dma;
  146. if (!tmpptr) {
  147. ret = -ENOMEM;
  148. goto out;
  149. }
  150. /*
  151. * Don't access any register before this point!
  152. */
  153. #ifdef __BIG_ENDIAN
  154. writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP,
  155. &rrpriv->regs->HostCtrl);
  156. #endif
  157. /*
  158. * Need to add a case for little-endian 64-bit hosts here.
  159. */
  160. rr_init(dev);
  161. ret = register_netdev(dev);
  162. if (ret)
  163. goto out;
  164. return 0;
  165. out:
  166. if (rrpriv->evt_ring)
  167. pci_free_consistent(pdev, EVT_RING_SIZE, rrpriv->evt_ring,
  168. rrpriv->evt_ring_dma);
  169. if (rrpriv->rx_ring)
  170. pci_free_consistent(pdev, RX_TOTAL_SIZE, rrpriv->rx_ring,
  171. rrpriv->rx_ring_dma);
  172. if (rrpriv->tx_ring)
  173. pci_free_consistent(pdev, TX_TOTAL_SIZE, rrpriv->tx_ring,
  174. rrpriv->tx_ring_dma);
  175. if (rrpriv->regs)
  176. pci_iounmap(pdev, rrpriv->regs);
  177. if (pdev)
  178. pci_release_regions(pdev);
  179. out2:
  180. free_netdev(dev);
  181. out3:
  182. return ret;
  183. }
  184. static void rr_remove_one(struct pci_dev *pdev)
  185. {
  186. struct net_device *dev = pci_get_drvdata(pdev);
  187. struct rr_private *rr = netdev_priv(dev);
  188. if (!(readl(&rr->regs->HostCtrl) & NIC_HALTED)) {
  189. printk(KERN_ERR "%s: trying to unload running NIC\n",
  190. dev->name);
  191. writel(HALT_NIC, &rr->regs->HostCtrl);
  192. }
  193. unregister_netdev(dev);
  194. pci_free_consistent(pdev, EVT_RING_SIZE, rr->evt_ring,
  195. rr->evt_ring_dma);
  196. pci_free_consistent(pdev, RX_TOTAL_SIZE, rr->rx_ring,
  197. rr->rx_ring_dma);
  198. pci_free_consistent(pdev, TX_TOTAL_SIZE, rr->tx_ring,
  199. rr->tx_ring_dma);
  200. pci_iounmap(pdev, rr->regs);
  201. pci_release_regions(pdev);
  202. pci_disable_device(pdev);
  203. free_netdev(dev);
  204. }
  205. /*
  206. * Commands are considered to be slow, thus there is no reason to
  207. * inline this.
  208. */
  209. static void rr_issue_cmd(struct rr_private *rrpriv, struct cmd *cmd)
  210. {
  211. struct rr_regs __iomem *regs;
  212. u32 idx;
  213. regs = rrpriv->regs;
  214. /*
  215. * This is temporary - it will go away in the final version.
  216. * We probably also want to make this function inline.
  217. */
  218. if (readl(&regs->HostCtrl) & NIC_HALTED){
  219. printk("issuing command for halted NIC, code 0x%x, "
  220. "HostCtrl %08x\n", cmd->code, readl(&regs->HostCtrl));
  221. if (readl(&regs->Mode) & FATAL_ERR)
  222. printk("error codes Fail1 %02x, Fail2 %02x\n",
  223. readl(&regs->Fail1), readl(&regs->Fail2));
  224. }
  225. idx = rrpriv->info->cmd_ctrl.pi;
  226. writel(*(u32*)(cmd), &regs->CmdRing[idx]);
  227. wmb();
  228. idx = (idx - 1) % CMD_RING_ENTRIES;
  229. rrpriv->info->cmd_ctrl.pi = idx;
  230. wmb();
  231. if (readl(&regs->Mode) & FATAL_ERR)
  232. printk("error code %02x\n", readl(&regs->Fail1));
  233. }
  234. /*
  235. * Reset the board in a sensible manner. The NIC is already halted
  236. * when we get here and a spin-lock is held.
  237. */
  238. static int rr_reset(struct net_device *dev)
  239. {
  240. struct rr_private *rrpriv;
  241. struct rr_regs __iomem *regs;
  242. u32 start_pc;
  243. int i;
  244. rrpriv = netdev_priv(dev);
  245. regs = rrpriv->regs;
  246. rr_load_firmware(dev);
  247. writel(0x01000000, &regs->TX_state);
  248. writel(0xff800000, &regs->RX_state);
  249. writel(0, &regs->AssistState);
  250. writel(CLEAR_INTA, &regs->LocalCtrl);
  251. writel(0x01, &regs->BrkPt);
  252. writel(0, &regs->Timer);
  253. writel(0, &regs->TimerRef);
  254. writel(RESET_DMA, &regs->DmaReadState);
  255. writel(RESET_DMA, &regs->DmaWriteState);
  256. writel(0, &regs->DmaWriteHostHi);
  257. writel(0, &regs->DmaWriteHostLo);
  258. writel(0, &regs->DmaReadHostHi);
  259. writel(0, &regs->DmaReadHostLo);
  260. writel(0, &regs->DmaReadLen);
  261. writel(0, &regs->DmaWriteLen);
  262. writel(0, &regs->DmaWriteLcl);
  263. writel(0, &regs->DmaWriteIPchecksum);
  264. writel(0, &regs->DmaReadLcl);
  265. writel(0, &regs->DmaReadIPchecksum);
  266. writel(0, &regs->PciState);
  267. #if (BITS_PER_LONG == 64) && defined __LITTLE_ENDIAN
  268. writel(SWAP_DATA | PTR64BIT | PTR_WD_SWAP, &regs->Mode);
  269. #elif (BITS_PER_LONG == 64)
  270. writel(SWAP_DATA | PTR64BIT | PTR_WD_NOSWAP, &regs->Mode);
  271. #else
  272. writel(SWAP_DATA | PTR32BIT | PTR_WD_NOSWAP, &regs->Mode);
  273. #endif
  274. #if 0
  275. /*
  276. * Don't worry, this is just black magic.
  277. */
  278. writel(0xdf000, &regs->RxBase);
  279. writel(0xdf000, &regs->RxPrd);
  280. writel(0xdf000, &regs->RxCon);
  281. writel(0xce000, &regs->TxBase);
  282. writel(0xce000, &regs->TxPrd);
  283. writel(0xce000, &regs->TxCon);
  284. writel(0, &regs->RxIndPro);
  285. writel(0, &regs->RxIndCon);
  286. writel(0, &regs->RxIndRef);
  287. writel(0, &regs->TxIndPro);
  288. writel(0, &regs->TxIndCon);
  289. writel(0, &regs->TxIndRef);
  290. writel(0xcc000, &regs->pad10[0]);
  291. writel(0, &regs->DrCmndPro);
  292. writel(0, &regs->DrCmndCon);
  293. writel(0, &regs->DwCmndPro);
  294. writel(0, &regs->DwCmndCon);
  295. writel(0, &regs->DwCmndRef);
  296. writel(0, &regs->DrDataPro);
  297. writel(0, &regs->DrDataCon);
  298. writel(0, &regs->DrDataRef);
  299. writel(0, &regs->DwDataPro);
  300. writel(0, &regs->DwDataCon);
  301. writel(0, &regs->DwDataRef);
  302. #endif
  303. writel(0xffffffff, &regs->MbEvent);
  304. writel(0, &regs->Event);
  305. writel(0, &regs->TxPi);
  306. writel(0, &regs->IpRxPi);
  307. writel(0, &regs->EvtCon);
  308. writel(0, &regs->EvtPrd);
  309. rrpriv->info->evt_ctrl.pi = 0;
  310. for (i = 0; i < CMD_RING_ENTRIES; i++)
  311. writel(0, &regs->CmdRing[i]);
  312. /*
  313. * Why 32 ? is this not cache line size dependent?
  314. */
  315. writel(RBURST_64|WBURST_64, &regs->PciState);
  316. wmb();
  317. start_pc = rr_read_eeprom_word(rrpriv,
  318. offsetof(struct eeprom, rncd_info.FwStart));
  319. #if (DEBUG > 1)
  320. printk("%s: Executing firmware at address 0x%06x\n",
  321. dev->name, start_pc);
  322. #endif
  323. writel(start_pc + 0x800, &regs->Pc);
  324. wmb();
  325. udelay(5);
  326. writel(start_pc, &regs->Pc);
  327. wmb();
  328. return 0;
  329. }
  330. /*
  331. * Read a string from the EEPROM.
  332. */
  333. static unsigned int rr_read_eeprom(struct rr_private *rrpriv,
  334. unsigned long offset,
  335. unsigned char *buf,
  336. unsigned long length)
  337. {
  338. struct rr_regs __iomem *regs = rrpriv->regs;
  339. u32 misc, io, host, i;
  340. io = readl(&regs->ExtIo);
  341. writel(0, &regs->ExtIo);
  342. misc = readl(&regs->LocalCtrl);
  343. writel(0, &regs->LocalCtrl);
  344. host = readl(&regs->HostCtrl);
  345. writel(host | HALT_NIC, &regs->HostCtrl);
  346. mb();
  347. for (i = 0; i < length; i++){
  348. writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);
  349. mb();
  350. buf[i] = (readl(&regs->WinData) >> 24) & 0xff;
  351. mb();
  352. }
  353. writel(host, &regs->HostCtrl);
  354. writel(misc, &regs->LocalCtrl);
  355. writel(io, &regs->ExtIo);
  356. mb();
  357. return i;
  358. }
  359. /*
  360. * Shortcut to read one word (4 bytes) out of the EEPROM and convert
  361. * it to our CPU byte-order.
  362. */
  363. static u32 rr_read_eeprom_word(struct rr_private *rrpriv,
  364. size_t offset)
  365. {
  366. __be32 word;
  367. if ((rr_read_eeprom(rrpriv, offset,
  368. (unsigned char *)&word, 4) == 4))
  369. return be32_to_cpu(word);
  370. return 0;
  371. }
  372. /*
  373. * Write a string to the EEPROM.
  374. *
  375. * This is only called when the firmware is not running.
  376. */
  377. static unsigned int write_eeprom(struct rr_private *rrpriv,
  378. unsigned long offset,
  379. unsigned char *buf,
  380. unsigned long length)
  381. {
  382. struct rr_regs __iomem *regs = rrpriv->regs;
  383. u32 misc, io, data, i, j, ready, error = 0;
  384. io = readl(&regs->ExtIo);
  385. writel(0, &regs->ExtIo);
  386. misc = readl(&regs->LocalCtrl);
  387. writel(ENABLE_EEPROM_WRITE, &regs->LocalCtrl);
  388. mb();
  389. for (i = 0; i < length; i++){
  390. writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);
  391. mb();
  392. data = buf[i] << 24;
  393. /*
  394. * Only try to write the data if it is not the same
  395. * value already.
  396. */
  397. if ((readl(&regs->WinData) & 0xff000000) != data){
  398. writel(data, &regs->WinData);
  399. ready = 0;
  400. j = 0;
  401. mb();
  402. while(!ready){
  403. udelay(20);
  404. if ((readl(&regs->WinData) & 0xff000000) ==
  405. data)
  406. ready = 1;
  407. mb();
  408. if (j++ > 5000){
  409. printk("data mismatch: %08x, "
  410. "WinData %08x\n", data,
  411. readl(&regs->WinData));
  412. ready = 1;
  413. error = 1;
  414. }
  415. }
  416. }
  417. }
  418. writel(misc, &regs->LocalCtrl);
  419. writel(io, &regs->ExtIo);
  420. mb();
  421. return error;
  422. }
  423. static int rr_init(struct net_device *dev)
  424. {
  425. struct rr_private *rrpriv;
  426. struct rr_regs __iomem *regs;
  427. u32 sram_size, rev;
  428. rrpriv = netdev_priv(dev);
  429. regs = rrpriv->regs;
  430. rev = readl(&regs->FwRev);
  431. rrpriv->fw_rev = rev;
  432. if (rev > 0x00020024)
  433. printk(" Firmware revision: %i.%i.%i\n", (rev >> 16),
  434. ((rev >> 8) & 0xff), (rev & 0xff));
  435. else if (rev >= 0x00020000) {
  436. printk(" Firmware revision: %i.%i.%i (2.0.37 or "
  437. "later is recommended)\n", (rev >> 16),
  438. ((rev >> 8) & 0xff), (rev & 0xff));
  439. }else{
  440. printk(" Firmware revision too old: %i.%i.%i, please "
  441. "upgrade to 2.0.37 or later.\n",
  442. (rev >> 16), ((rev >> 8) & 0xff), (rev & 0xff));
  443. }
  444. #if (DEBUG > 2)
  445. printk(" Maximum receive rings %i\n", readl(&regs->MaxRxRng));
  446. #endif
  447. /*
  448. * Read the hardware address from the eeprom. The HW address
  449. * is not really necessary for HIPPI but awfully convenient.
  450. * The pointer arithmetic to put it in dev_addr is ugly, but
  451. * Donald Becker does it this way for the GigE version of this
  452. * card and it's shorter and more portable than any
  453. * other method I've seen. -VAL
  454. */
  455. *(__be16 *)(dev->dev_addr) =
  456. htons(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA)));
  457. *(__be32 *)(dev->dev_addr+2) =
  458. htonl(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA[4])));
  459. printk(" MAC: %pM\n", dev->dev_addr);
  460. sram_size = rr_read_eeprom_word(rrpriv, 8);
  461. printk(" SRAM size 0x%06x\n", sram_size);
  462. return 0;
  463. }
  464. static int rr_init1(struct net_device *dev)
  465. {
  466. struct rr_private *rrpriv;
  467. struct rr_regs __iomem *regs;
  468. unsigned long myjif, flags;
  469. struct cmd cmd;
  470. u32 hostctrl;
  471. int ecode = 0;
  472. short i;
  473. rrpriv = netdev_priv(dev);
  474. regs = rrpriv->regs;
  475. spin_lock_irqsave(&rrpriv->lock, flags);
  476. hostctrl = readl(&regs->HostCtrl);
  477. writel(hostctrl | HALT_NIC | RR_CLEAR_INT, &regs->HostCtrl);
  478. wmb();
  479. if (hostctrl & PARITY_ERR){
  480. printk("%s: Parity error halting NIC - this is serious!\n",
  481. dev->name);
  482. spin_unlock_irqrestore(&rrpriv->lock, flags);
  483. ecode = -EFAULT;
  484. goto error;
  485. }
  486. set_rxaddr(regs, rrpriv->rx_ctrl_dma);
  487. set_infoaddr(regs, rrpriv->info_dma);
  488. rrpriv->info->evt_ctrl.entry_size = sizeof(struct event);
  489. rrpriv->info->evt_ctrl.entries = EVT_RING_ENTRIES;
  490. rrpriv->info->evt_ctrl.mode = 0;
  491. rrpriv->info->evt_ctrl.pi = 0;
  492. set_rraddr(&rrpriv->info->evt_ctrl.rngptr, rrpriv->evt_ring_dma);
  493. rrpriv->info->cmd_ctrl.entry_size = sizeof(struct cmd);
  494. rrpriv->info->cmd_ctrl.entries = CMD_RING_ENTRIES;
  495. rrpriv->info->cmd_ctrl.mode = 0;
  496. rrpriv->info->cmd_ctrl.pi = 15;
  497. for (i = 0; i < CMD_RING_ENTRIES; i++) {
  498. writel(0, &regs->CmdRing[i]);
  499. }
  500. for (i = 0; i < TX_RING_ENTRIES; i++) {
  501. rrpriv->tx_ring[i].size = 0;
  502. set_rraddr(&rrpriv->tx_ring[i].addr, 0);
  503. rrpriv->tx_skbuff[i] = NULL;
  504. }
  505. rrpriv->info->tx_ctrl.entry_size = sizeof(struct tx_desc);
  506. rrpriv->info->tx_ctrl.entries = TX_RING_ENTRIES;
  507. rrpriv->info->tx_ctrl.mode = 0;
  508. rrpriv->info->tx_ctrl.pi = 0;
  509. set_rraddr(&rrpriv->info->tx_ctrl.rngptr, rrpriv->tx_ring_dma);
  510. /*
  511. * Set dirty_tx before we start receiving interrupts, otherwise
  512. * the interrupt handler might think it is supposed to process
  513. * tx ints before we are up and running, which may cause a null
  514. * pointer access in the int handler.
  515. */
  516. rrpriv->tx_full = 0;
  517. rrpriv->cur_rx = 0;
  518. rrpriv->dirty_rx = rrpriv->dirty_tx = 0;
  519. rr_reset(dev);
  520. /* Tuning values */
  521. writel(0x5000, &regs->ConRetry);
  522. writel(0x100, &regs->ConRetryTmr);
  523. writel(0x500000, &regs->ConTmout);
  524. writel(0x60, &regs->IntrTmr);
  525. writel(0x500000, &regs->TxDataMvTimeout);
  526. writel(0x200000, &regs->RxDataMvTimeout);
  527. writel(0x80, &regs->WriteDmaThresh);
  528. writel(0x80, &regs->ReadDmaThresh);
  529. rrpriv->fw_running = 0;
  530. wmb();
  531. hostctrl &= ~(HALT_NIC | INVALID_INST_B | PARITY_ERR);
  532. writel(hostctrl, &regs->HostCtrl);
  533. wmb();
  534. spin_unlock_irqrestore(&rrpriv->lock, flags);
  535. for (i = 0; i < RX_RING_ENTRIES; i++) {
  536. struct sk_buff *skb;
  537. dma_addr_t addr;
  538. rrpriv->rx_ring[i].mode = 0;
  539. skb = alloc_skb(dev->mtu + HIPPI_HLEN, GFP_ATOMIC);
  540. if (!skb) {
  541. printk(KERN_WARNING "%s: Unable to allocate memory "
  542. "for receive ring - halting NIC\n", dev->name);
  543. ecode = -ENOMEM;
  544. goto error;
  545. }
  546. rrpriv->rx_skbuff[i] = skb;
  547. addr = pci_map_single(rrpriv->pci_dev, skb->data,
  548. dev->mtu + HIPPI_HLEN, PCI_DMA_FROMDEVICE);
  549. /*
  550. * Sanity test to see if we conflict with the DMA
  551. * limitations of the Roadrunner.
  552. */
  553. if ((((unsigned long)skb->data) & 0xfff) > ~65320)
  554. printk("skb alloc error\n");
  555. set_rraddr(&rrpriv->rx_ring[i].addr, addr);
  556. rrpriv->rx_ring[i].size = dev->mtu + HIPPI_HLEN;
  557. }
  558. rrpriv->rx_ctrl[4].entry_size = sizeof(struct rx_desc);
  559. rrpriv->rx_ctrl[4].entries = RX_RING_ENTRIES;
  560. rrpriv->rx_ctrl[4].mode = 8;
  561. rrpriv->rx_ctrl[4].pi = 0;
  562. wmb();
  563. set_rraddr(&rrpriv->rx_ctrl[4].rngptr, rrpriv->rx_ring_dma);
  564. udelay(1000);
  565. /*
  566. * Now start the FirmWare.
  567. */
  568. cmd.code = C_START_FW;
  569. cmd.ring = 0;
  570. cmd.index = 0;
  571. rr_issue_cmd(rrpriv, &cmd);
  572. /*
  573. * Give the FirmWare time to chew on the `get running' command.
  574. */
  575. myjif = jiffies + 5 * HZ;
  576. while (time_before(jiffies, myjif) && !rrpriv->fw_running)
  577. cpu_relax();
  578. netif_start_queue(dev);
  579. return ecode;
  580. error:
  581. /*
  582. * We might have gotten here because we are out of memory,
  583. * make sure we release everything we allocated before failing
  584. */
  585. for (i = 0; i < RX_RING_ENTRIES; i++) {
  586. struct sk_buff *skb = rrpriv->rx_skbuff[i];
  587. if (skb) {
  588. pci_unmap_single(rrpriv->pci_dev,
  589. rrpriv->rx_ring[i].addr.addrlo,
  590. dev->mtu + HIPPI_HLEN,
  591. PCI_DMA_FROMDEVICE);
  592. rrpriv->rx_ring[i].size = 0;
  593. set_rraddr(&rrpriv->rx_ring[i].addr, 0);
  594. dev_kfree_skb(skb);
  595. rrpriv->rx_skbuff[i] = NULL;
  596. }
  597. }
  598. return ecode;
  599. }
  600. /*
  601. * All events are considered to be slow (RX/TX ints do not generate
  602. * events) and are handled here, outside the main interrupt handler,
  603. * to reduce the size of the handler.
  604. */
  605. static u32 rr_handle_event(struct net_device *dev, u32 prodidx, u32 eidx)
  606. {
  607. struct rr_private *rrpriv;
  608. struct rr_regs __iomem *regs;
  609. u32 tmp;
  610. rrpriv = netdev_priv(dev);
  611. regs = rrpriv->regs;
  612. while (prodidx != eidx){
  613. switch (rrpriv->evt_ring[eidx].code){
  614. case E_NIC_UP:
  615. tmp = readl(&regs->FwRev);
  616. printk(KERN_INFO "%s: Firmware revision %i.%i.%i "
  617. "up and running\n", dev->name,
  618. (tmp >> 16), ((tmp >> 8) & 0xff), (tmp & 0xff));
  619. rrpriv->fw_running = 1;
  620. writel(RX_RING_ENTRIES - 1, &regs->IpRxPi);
  621. wmb();
  622. break;
  623. case E_LINK_ON:
  624. printk(KERN_INFO "%s: Optical link ON\n", dev->name);
  625. break;
  626. case E_LINK_OFF:
  627. printk(KERN_INFO "%s: Optical link OFF\n", dev->name);
  628. break;
  629. case E_RX_IDLE:
  630. printk(KERN_WARNING "%s: RX data not moving\n",
  631. dev->name);
  632. goto drop;
  633. case E_WATCHDOG:
  634. printk(KERN_INFO "%s: The watchdog is here to see "
  635. "us\n", dev->name);
  636. break;
  637. case E_INTERN_ERR:
  638. printk(KERN_ERR "%s: HIPPI Internal NIC error\n",
  639. dev->name);
  640. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  641. &regs->HostCtrl);
  642. wmb();
  643. break;
  644. case E_HOST_ERR:
  645. printk(KERN_ERR "%s: Host software error\n",
  646. dev->name);
  647. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  648. &regs->HostCtrl);
  649. wmb();
  650. break;
  651. /*
  652. * TX events.
  653. */
  654. case E_CON_REJ:
  655. printk(KERN_WARNING "%s: Connection rejected\n",
  656. dev->name);
  657. dev->stats.tx_aborted_errors++;
  658. break;
  659. case E_CON_TMOUT:
  660. printk(KERN_WARNING "%s: Connection timeout\n",
  661. dev->name);
  662. break;
  663. case E_DISC_ERR:
  664. printk(KERN_WARNING "%s: HIPPI disconnect error\n",
  665. dev->name);
  666. dev->stats.tx_aborted_errors++;
  667. break;
  668. case E_INT_PRTY:
  669. printk(KERN_ERR "%s: HIPPI Internal Parity error\n",
  670. dev->name);
  671. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  672. &regs->HostCtrl);
  673. wmb();
  674. break;
  675. case E_TX_IDLE:
  676. printk(KERN_WARNING "%s: Transmitter idle\n",
  677. dev->name);
  678. break;
  679. case E_TX_LINK_DROP:
  680. printk(KERN_WARNING "%s: Link lost during transmit\n",
  681. dev->name);
  682. dev->stats.tx_aborted_errors++;
  683. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  684. &regs->HostCtrl);
  685. wmb();
  686. break;
  687. case E_TX_INV_RNG:
  688. printk(KERN_ERR "%s: Invalid send ring block\n",
  689. dev->name);
  690. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  691. &regs->HostCtrl);
  692. wmb();
  693. break;
  694. case E_TX_INV_BUF:
  695. printk(KERN_ERR "%s: Invalid send buffer address\n",
  696. dev->name);
  697. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  698. &regs->HostCtrl);
  699. wmb();
  700. break;
  701. case E_TX_INV_DSC:
  702. printk(KERN_ERR "%s: Invalid descriptor address\n",
  703. dev->name);
  704. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  705. &regs->HostCtrl);
  706. wmb();
  707. break;
  708. /*
  709. * RX events.
  710. */
  711. case E_RX_RNG_OUT:
  712. printk(KERN_INFO "%s: Receive ring full\n", dev->name);
  713. break;
  714. case E_RX_PAR_ERR:
  715. printk(KERN_WARNING "%s: Receive parity error\n",
  716. dev->name);
  717. goto drop;
  718. case E_RX_LLRC_ERR:
  719. printk(KERN_WARNING "%s: Receive LLRC error\n",
  720. dev->name);
  721. goto drop;
  722. case E_PKT_LN_ERR:
  723. printk(KERN_WARNING "%s: Receive packet length "
  724. "error\n", dev->name);
  725. goto drop;
  726. case E_DTA_CKSM_ERR:
  727. printk(KERN_WARNING "%s: Data checksum error\n",
  728. dev->name);
  729. goto drop;
  730. case E_SHT_BST:
  731. printk(KERN_WARNING "%s: Unexpected short burst "
  732. "error\n", dev->name);
  733. goto drop;
  734. case E_STATE_ERR:
  735. printk(KERN_WARNING "%s: Recv. state transition"
  736. " error\n", dev->name);
  737. goto drop;
  738. case E_UNEXP_DATA:
  739. printk(KERN_WARNING "%s: Unexpected data error\n",
  740. dev->name);
  741. goto drop;
  742. case E_LST_LNK_ERR:
  743. printk(KERN_WARNING "%s: Link lost error\n",
  744. dev->name);
  745. goto drop;
  746. case E_FRM_ERR:
  747. printk(KERN_WARNING "%s: Framming Error\n",
  748. dev->name);
  749. goto drop;
  750. case E_FLG_SYN_ERR:
  751. printk(KERN_WARNING "%s: Flag sync. lost during "
  752. "packet\n", dev->name);
  753. goto drop;
  754. case E_RX_INV_BUF:
  755. printk(KERN_ERR "%s: Invalid receive buffer "
  756. "address\n", dev->name);
  757. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  758. &regs->HostCtrl);
  759. wmb();
  760. break;
  761. case E_RX_INV_DSC:
  762. printk(KERN_ERR "%s: Invalid receive descriptor "
  763. "address\n", dev->name);
  764. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  765. &regs->HostCtrl);
  766. wmb();
  767. break;
  768. case E_RNG_BLK:
  769. printk(KERN_ERR "%s: Invalid ring block\n",
  770. dev->name);
  771. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  772. &regs->HostCtrl);
  773. wmb();
  774. break;
  775. drop:
  776. /* Label packet to be dropped.
  777. * Actual dropping occurs in rx
  778. * handling.
  779. *
  780. * The index of packet we get to drop is
  781. * the index of the packet following
  782. * the bad packet. -kbf
  783. */
  784. {
  785. u16 index = rrpriv->evt_ring[eidx].index;
  786. index = (index + (RX_RING_ENTRIES - 1)) %
  787. RX_RING_ENTRIES;
  788. rrpriv->rx_ring[index].mode |=
  789. (PACKET_BAD | PACKET_END);
  790. }
  791. break;
  792. default:
  793. printk(KERN_WARNING "%s: Unhandled event 0x%02x\n",
  794. dev->name, rrpriv->evt_ring[eidx].code);
  795. }
  796. eidx = (eidx + 1) % EVT_RING_ENTRIES;
  797. }
  798. rrpriv->info->evt_ctrl.pi = eidx;
  799. wmb();
  800. return eidx;
  801. }
  802. static void rx_int(struct net_device *dev, u32 rxlimit, u32 index)
  803. {
  804. struct rr_private *rrpriv = netdev_priv(dev);
  805. struct rr_regs __iomem *regs = rrpriv->regs;
  806. do {
  807. struct rx_desc *desc;
  808. u32 pkt_len;
  809. desc = &(rrpriv->rx_ring[index]);
  810. pkt_len = desc->size;
  811. #if (DEBUG > 2)
  812. printk("index %i, rxlimit %i\n", index, rxlimit);
  813. printk("len %x, mode %x\n", pkt_len, desc->mode);
  814. #endif
  815. if ( (rrpriv->rx_ring[index].mode & PACKET_BAD) == PACKET_BAD){
  816. dev->stats.rx_dropped++;
  817. goto defer;
  818. }
  819. if (pkt_len > 0){
  820. struct sk_buff *skb, *rx_skb;
  821. rx_skb = rrpriv->rx_skbuff[index];
  822. if (pkt_len < PKT_COPY_THRESHOLD) {
  823. skb = alloc_skb(pkt_len, GFP_ATOMIC);
  824. if (skb == NULL){
  825. printk(KERN_WARNING "%s: Unable to allocate skb (%i bytes), deferring packet\n", dev->name, pkt_len);
  826. dev->stats.rx_dropped++;
  827. goto defer;
  828. } else {
  829. pci_dma_sync_single_for_cpu(rrpriv->pci_dev,
  830. desc->addr.addrlo,
  831. pkt_len,
  832. PCI_DMA_FROMDEVICE);
  833. memcpy(skb_put(skb, pkt_len),
  834. rx_skb->data, pkt_len);
  835. pci_dma_sync_single_for_device(rrpriv->pci_dev,
  836. desc->addr.addrlo,
  837. pkt_len,
  838. PCI_DMA_FROMDEVICE);
  839. }
  840. }else{
  841. struct sk_buff *newskb;
  842. newskb = alloc_skb(dev->mtu + HIPPI_HLEN,
  843. GFP_ATOMIC);
  844. if (newskb){
  845. dma_addr_t addr;
  846. pci_unmap_single(rrpriv->pci_dev,
  847. desc->addr.addrlo, dev->mtu +
  848. HIPPI_HLEN, PCI_DMA_FROMDEVICE);
  849. skb = rx_skb;
  850. skb_put(skb, pkt_len);
  851. rrpriv->rx_skbuff[index] = newskb;
  852. addr = pci_map_single(rrpriv->pci_dev,
  853. newskb->data,
  854. dev->mtu + HIPPI_HLEN,
  855. PCI_DMA_FROMDEVICE);
  856. set_rraddr(&desc->addr, addr);
  857. } else {
  858. printk("%s: Out of memory, deferring "
  859. "packet\n", dev->name);
  860. dev->stats.rx_dropped++;
  861. goto defer;
  862. }
  863. }
  864. skb->protocol = hippi_type_trans(skb, dev);
  865. netif_rx(skb); /* send it up */
  866. dev->stats.rx_packets++;
  867. dev->stats.rx_bytes += pkt_len;
  868. }
  869. defer:
  870. desc->mode = 0;
  871. desc->size = dev->mtu + HIPPI_HLEN;
  872. if ((index & 7) == 7)
  873. writel(index, &regs->IpRxPi);
  874. index = (index + 1) % RX_RING_ENTRIES;
  875. } while(index != rxlimit);
  876. rrpriv->cur_rx = index;
  877. wmb();
  878. }
  879. static irqreturn_t rr_interrupt(int irq, void *dev_id)
  880. {
  881. struct rr_private *rrpriv;
  882. struct rr_regs __iomem *regs;
  883. struct net_device *dev = (struct net_device *)dev_id;
  884. u32 prodidx, rxindex, eidx, txcsmr, rxlimit, txcon;
  885. rrpriv = netdev_priv(dev);
  886. regs = rrpriv->regs;
  887. if (!(readl(&regs->HostCtrl) & RR_INT))
  888. return IRQ_NONE;
  889. spin_lock(&rrpriv->lock);
  890. prodidx = readl(&regs->EvtPrd);
  891. txcsmr = (prodidx >> 8) & 0xff;
  892. rxlimit = (prodidx >> 16) & 0xff;
  893. prodidx &= 0xff;
  894. #if (DEBUG > 2)
  895. printk("%s: interrupt, prodidx = %i, eidx = %i\n", dev->name,
  896. prodidx, rrpriv->info->evt_ctrl.pi);
  897. #endif
  898. /*
  899. * Order here is important. We must handle events
  900. * before doing anything else in order to catch
  901. * such things as LLRC errors, etc -kbf
  902. */
  903. eidx = rrpriv->info->evt_ctrl.pi;
  904. if (prodidx != eidx)
  905. eidx = rr_handle_event(dev, prodidx, eidx);
  906. rxindex = rrpriv->cur_rx;
  907. if (rxindex != rxlimit)
  908. rx_int(dev, rxlimit, rxindex);
  909. txcon = rrpriv->dirty_tx;
  910. if (txcsmr != txcon) {
  911. do {
  912. /* Due to occational firmware TX producer/consumer out
  913. * of sync. error need to check entry in ring -kbf
  914. */
  915. if(rrpriv->tx_skbuff[txcon]){
  916. struct tx_desc *desc;
  917. struct sk_buff *skb;
  918. desc = &(rrpriv->tx_ring[txcon]);
  919. skb = rrpriv->tx_skbuff[txcon];
  920. dev->stats.tx_packets++;
  921. dev->stats.tx_bytes += skb->len;
  922. pci_unmap_single(rrpriv->pci_dev,
  923. desc->addr.addrlo, skb->len,
  924. PCI_DMA_TODEVICE);
  925. dev_kfree_skb_irq(skb);
  926. rrpriv->tx_skbuff[txcon] = NULL;
  927. desc->size = 0;
  928. set_rraddr(&rrpriv->tx_ring[txcon].addr, 0);
  929. desc->mode = 0;
  930. }
  931. txcon = (txcon + 1) % TX_RING_ENTRIES;
  932. } while (txcsmr != txcon);
  933. wmb();
  934. rrpriv->dirty_tx = txcon;
  935. if (rrpriv->tx_full && rr_if_busy(dev) &&
  936. (((rrpriv->info->tx_ctrl.pi + 1) % TX_RING_ENTRIES)
  937. != rrpriv->dirty_tx)){
  938. rrpriv->tx_full = 0;
  939. netif_wake_queue(dev);
  940. }
  941. }
  942. eidx |= ((txcsmr << 8) | (rxlimit << 16));
  943. writel(eidx, &regs->EvtCon);
  944. wmb();
  945. spin_unlock(&rrpriv->lock);
  946. return IRQ_HANDLED;
  947. }
  948. static inline void rr_raz_tx(struct rr_private *rrpriv,
  949. struct net_device *dev)
  950. {
  951. int i;
  952. for (i = 0; i < TX_RING_ENTRIES; i++) {
  953. struct sk_buff *skb = rrpriv->tx_skbuff[i];
  954. if (skb) {
  955. struct tx_desc *desc = &(rrpriv->tx_ring[i]);
  956. pci_unmap_single(rrpriv->pci_dev, desc->addr.addrlo,
  957. skb->len, PCI_DMA_TODEVICE);
  958. desc->size = 0;
  959. set_rraddr(&desc->addr, 0);
  960. dev_kfree_skb(skb);
  961. rrpriv->tx_skbuff[i] = NULL;
  962. }
  963. }
  964. }
  965. static inline void rr_raz_rx(struct rr_private *rrpriv,
  966. struct net_device *dev)
  967. {
  968. int i;
  969. for (i = 0; i < RX_RING_ENTRIES; i++) {
  970. struct sk_buff *skb = rrpriv->rx_skbuff[i];
  971. if (skb) {
  972. struct rx_desc *desc = &(rrpriv->rx_ring[i]);
  973. pci_unmap_single(rrpriv->pci_dev, desc->addr.addrlo,
  974. dev->mtu + HIPPI_HLEN, PCI_DMA_FROMDEVICE);
  975. desc->size = 0;
  976. set_rraddr(&desc->addr, 0);
  977. dev_kfree_skb(skb);
  978. rrpriv->rx_skbuff[i] = NULL;
  979. }
  980. }
  981. }
  982. static void rr_timer(unsigned long data)
  983. {
  984. struct net_device *dev = (struct net_device *)data;
  985. struct rr_private *rrpriv = netdev_priv(dev);
  986. struct rr_regs __iomem *regs = rrpriv->regs;
  987. unsigned long flags;
  988. if (readl(&regs->HostCtrl) & NIC_HALTED){
  989. printk("%s: Restarting nic\n", dev->name);
  990. memset(rrpriv->rx_ctrl, 0, 256 * sizeof(struct ring_ctrl));
  991. memset(rrpriv->info, 0, sizeof(struct rr_info));
  992. wmb();
  993. rr_raz_tx(rrpriv, dev);
  994. rr_raz_rx(rrpriv, dev);
  995. if (rr_init1(dev)) {
  996. spin_lock_irqsave(&rrpriv->lock, flags);
  997. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  998. &regs->HostCtrl);
  999. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1000. }
  1001. }
  1002. rrpriv->timer.expires = RUN_AT(5*HZ);
  1003. add_timer(&rrpriv->timer);
  1004. }
  1005. static int rr_open(struct net_device *dev)
  1006. {
  1007. struct rr_private *rrpriv = netdev_priv(dev);
  1008. struct pci_dev *pdev = rrpriv->pci_dev;
  1009. struct rr_regs __iomem *regs;
  1010. int ecode = 0;
  1011. unsigned long flags;
  1012. dma_addr_t dma_addr;
  1013. regs = rrpriv->regs;
  1014. if (rrpriv->fw_rev < 0x00020000) {
  1015. printk(KERN_WARNING "%s: trying to configure device with "
  1016. "obsolete firmware\n", dev->name);
  1017. ecode = -EBUSY;
  1018. goto error;
  1019. }
  1020. rrpriv->rx_ctrl = pci_alloc_consistent(pdev,
  1021. 256 * sizeof(struct ring_ctrl),
  1022. &dma_addr);
  1023. if (!rrpriv->rx_ctrl) {
  1024. ecode = -ENOMEM;
  1025. goto error;
  1026. }
  1027. rrpriv->rx_ctrl_dma = dma_addr;
  1028. memset(rrpriv->rx_ctrl, 0, 256*sizeof(struct ring_ctrl));
  1029. rrpriv->info = pci_alloc_consistent(pdev, sizeof(struct rr_info),
  1030. &dma_addr);
  1031. if (!rrpriv->info) {
  1032. ecode = -ENOMEM;
  1033. goto error;
  1034. }
  1035. rrpriv->info_dma = dma_addr;
  1036. memset(rrpriv->info, 0, sizeof(struct rr_info));
  1037. wmb();
  1038. spin_lock_irqsave(&rrpriv->lock, flags);
  1039. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);
  1040. readl(&regs->HostCtrl);
  1041. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1042. if (request_irq(pdev->irq, rr_interrupt, IRQF_SHARED, dev->name, dev)) {
  1043. printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
  1044. dev->name, pdev->irq);
  1045. ecode = -EAGAIN;
  1046. goto error;
  1047. }
  1048. if ((ecode = rr_init1(dev)))
  1049. goto error;
  1050. /* Set the timer to switch to check for link beat and perhaps switch
  1051. to an alternate media type. */
  1052. init_timer(&rrpriv->timer);
  1053. rrpriv->timer.expires = RUN_AT(5*HZ); /* 5 sec. watchdog */
  1054. rrpriv->timer.data = (unsigned long)dev;
  1055. rrpriv->timer.function = rr_timer; /* timer handler */
  1056. add_timer(&rrpriv->timer);
  1057. netif_start_queue(dev);
  1058. return ecode;
  1059. error:
  1060. spin_lock_irqsave(&rrpriv->lock, flags);
  1061. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);
  1062. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1063. if (rrpriv->info) {
  1064. pci_free_consistent(pdev, sizeof(struct rr_info), rrpriv->info,
  1065. rrpriv->info_dma);
  1066. rrpriv->info = NULL;
  1067. }
  1068. if (rrpriv->rx_ctrl) {
  1069. pci_free_consistent(pdev, sizeof(struct ring_ctrl),
  1070. rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
  1071. rrpriv->rx_ctrl = NULL;
  1072. }
  1073. netif_stop_queue(dev);
  1074. return ecode;
  1075. }
  1076. static void rr_dump(struct net_device *dev)
  1077. {
  1078. struct rr_private *rrpriv;
  1079. struct rr_regs __iomem *regs;
  1080. u32 index, cons;
  1081. short i;
  1082. int len;
  1083. rrpriv = netdev_priv(dev);
  1084. regs = rrpriv->regs;
  1085. printk("%s: dumping NIC TX rings\n", dev->name);
  1086. printk("RxPrd %08x, TxPrd %02x, EvtPrd %08x, TxPi %02x, TxCtrlPi %02x\n",
  1087. readl(&regs->RxPrd), readl(&regs->TxPrd),
  1088. readl(&regs->EvtPrd), readl(&regs->TxPi),
  1089. rrpriv->info->tx_ctrl.pi);
  1090. printk("Error code 0x%x\n", readl(&regs->Fail1));
  1091. index = (((readl(&regs->EvtPrd) >> 8) & 0xff) - 1) % TX_RING_ENTRIES;
  1092. cons = rrpriv->dirty_tx;
  1093. printk("TX ring index %i, TX consumer %i\n",
  1094. index, cons);
  1095. if (rrpriv->tx_skbuff[index]){
  1096. len = min_t(int, 0x80, rrpriv->tx_skbuff[index]->len);
  1097. printk("skbuff for index %i is valid - dumping data (0x%x bytes - DMA len 0x%x)\n", index, len, rrpriv->tx_ring[index].size);
  1098. for (i = 0; i < len; i++){
  1099. if (!(i & 7))
  1100. printk("\n");
  1101. printk("%02x ", (unsigned char) rrpriv->tx_skbuff[index]->data[i]);
  1102. }
  1103. printk("\n");
  1104. }
  1105. if (rrpriv->tx_skbuff[cons]){
  1106. len = min_t(int, 0x80, rrpriv->tx_skbuff[cons]->len);
  1107. printk("skbuff for cons %i is valid - dumping data (0x%x bytes - skbuff len 0x%x)\n", cons, len, rrpriv->tx_skbuff[cons]->len);
  1108. printk("mode 0x%x, size 0x%x,\n phys %08Lx, skbuff-addr %08lx, truesize 0x%x\n",
  1109. rrpriv->tx_ring[cons].mode,
  1110. rrpriv->tx_ring[cons].size,
  1111. (unsigned long long) rrpriv->tx_ring[cons].addr.addrlo,
  1112. (unsigned long)rrpriv->tx_skbuff[cons]->data,
  1113. (unsigned int)rrpriv->tx_skbuff[cons]->truesize);
  1114. for (i = 0; i < len; i++){
  1115. if (!(i & 7))
  1116. printk("\n");
  1117. printk("%02x ", (unsigned char)rrpriv->tx_ring[cons].size);
  1118. }
  1119. printk("\n");
  1120. }
  1121. printk("dumping TX ring info:\n");
  1122. for (i = 0; i < TX_RING_ENTRIES; i++)
  1123. printk("mode 0x%x, size 0x%x, phys-addr %08Lx\n",
  1124. rrpriv->tx_ring[i].mode,
  1125. rrpriv->tx_ring[i].size,
  1126. (unsigned long long) rrpriv->tx_ring[i].addr.addrlo);
  1127. }
  1128. static int rr_close(struct net_device *dev)
  1129. {
  1130. struct rr_private *rrpriv = netdev_priv(dev);
  1131. struct rr_regs __iomem *regs = rrpriv->regs;
  1132. struct pci_dev *pdev = rrpriv->pci_dev;
  1133. unsigned long flags;
  1134. u32 tmp;
  1135. short i;
  1136. netif_stop_queue(dev);
  1137. /*
  1138. * Lock to make sure we are not cleaning up while another CPU
  1139. * is handling interrupts.
  1140. */
  1141. spin_lock_irqsave(&rrpriv->lock, flags);
  1142. tmp = readl(&regs->HostCtrl);
  1143. if (tmp & NIC_HALTED){
  1144. printk("%s: NIC already halted\n", dev->name);
  1145. rr_dump(dev);
  1146. }else{
  1147. tmp |= HALT_NIC | RR_CLEAR_INT;
  1148. writel(tmp, &regs->HostCtrl);
  1149. readl(&regs->HostCtrl);
  1150. }
  1151. rrpriv->fw_running = 0;
  1152. del_timer_sync(&rrpriv->timer);
  1153. writel(0, &regs->TxPi);
  1154. writel(0, &regs->IpRxPi);
  1155. writel(0, &regs->EvtCon);
  1156. writel(0, &regs->EvtPrd);
  1157. for (i = 0; i < CMD_RING_ENTRIES; i++)
  1158. writel(0, &regs->CmdRing[i]);
  1159. rrpriv->info->tx_ctrl.entries = 0;
  1160. rrpriv->info->cmd_ctrl.pi = 0;
  1161. rrpriv->info->evt_ctrl.pi = 0;
  1162. rrpriv->rx_ctrl[4].entries = 0;
  1163. rr_raz_tx(rrpriv, dev);
  1164. rr_raz_rx(rrpriv, dev);
  1165. pci_free_consistent(pdev, 256 * sizeof(struct ring_ctrl),
  1166. rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
  1167. rrpriv->rx_ctrl = NULL;
  1168. pci_free_consistent(pdev, sizeof(struct rr_info), rrpriv->info,
  1169. rrpriv->info_dma);
  1170. rrpriv->info = NULL;
  1171. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1172. free_irq(pdev->irq, dev);
  1173. return 0;
  1174. }
  1175. static netdev_tx_t rr_start_xmit(struct sk_buff *skb,
  1176. struct net_device *dev)
  1177. {
  1178. struct rr_private *rrpriv = netdev_priv(dev);
  1179. struct rr_regs __iomem *regs = rrpriv->regs;
  1180. struct hippi_cb *hcb = (struct hippi_cb *) skb->cb;
  1181. struct ring_ctrl *txctrl;
  1182. unsigned long flags;
  1183. u32 index, len = skb->len;
  1184. u32 *ifield;
  1185. struct sk_buff *new_skb;
  1186. if (readl(&regs->Mode) & FATAL_ERR)
  1187. printk("error codes Fail1 %02x, Fail2 %02x\n",
  1188. readl(&regs->Fail1), readl(&regs->Fail2));
  1189. /*
  1190. * We probably need to deal with tbusy here to prevent overruns.
  1191. */
  1192. if (skb_headroom(skb) < 8){
  1193. printk("incoming skb too small - reallocating\n");
  1194. if (!(new_skb = dev_alloc_skb(len + 8))) {
  1195. dev_kfree_skb(skb);
  1196. netif_wake_queue(dev);
  1197. return NETDEV_TX_OK;
  1198. }
  1199. skb_reserve(new_skb, 8);
  1200. skb_put(new_skb, len);
  1201. skb_copy_from_linear_data(skb, new_skb->data, len);
  1202. dev_kfree_skb(skb);
  1203. skb = new_skb;
  1204. }
  1205. ifield = (u32 *)skb_push(skb, 8);
  1206. ifield[0] = 0;
  1207. ifield[1] = hcb->ifield;
  1208. /*
  1209. * We don't need the lock before we are actually going to start
  1210. * fiddling with the control blocks.
  1211. */
  1212. spin_lock_irqsave(&rrpriv->lock, flags);
  1213. txctrl = &rrpriv->info->tx_ctrl;
  1214. index = txctrl->pi;
  1215. rrpriv->tx_skbuff[index] = skb;
  1216. set_rraddr(&rrpriv->tx_ring[index].addr, pci_map_single(
  1217. rrpriv->pci_dev, skb->data, len + 8, PCI_DMA_TODEVICE));
  1218. rrpriv->tx_ring[index].size = len + 8; /* include IFIELD */
  1219. rrpriv->tx_ring[index].mode = PACKET_START | PACKET_END;
  1220. txctrl->pi = (index + 1) % TX_RING_ENTRIES;
  1221. wmb();
  1222. writel(txctrl->pi, &regs->TxPi);
  1223. if (txctrl->pi == rrpriv->dirty_tx){
  1224. rrpriv->tx_full = 1;
  1225. netif_stop_queue(dev);
  1226. }
  1227. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1228. return NETDEV_TX_OK;
  1229. }
  1230. /*
  1231. * Read the firmware out of the EEPROM and put it into the SRAM
  1232. * (or from user space - later)
  1233. *
  1234. * This operation requires the NIC to be halted and is performed with
  1235. * interrupts disabled and with the spinlock hold.
  1236. */
  1237. static int rr_load_firmware(struct net_device *dev)
  1238. {
  1239. struct rr_private *rrpriv;
  1240. struct rr_regs __iomem *regs;
  1241. size_t eptr, segptr;
  1242. int i, j;
  1243. u32 localctrl, sptr, len, tmp;
  1244. u32 p2len, p2size, nr_seg, revision, io, sram_size;
  1245. rrpriv = netdev_priv(dev);
  1246. regs = rrpriv->regs;
  1247. if (dev->flags & IFF_UP)
  1248. return -EBUSY;
  1249. if (!(readl(&regs->HostCtrl) & NIC_HALTED)){
  1250. printk("%s: Trying to load firmware to a running NIC.\n",
  1251. dev->name);
  1252. return -EBUSY;
  1253. }
  1254. localctrl = readl(&regs->LocalCtrl);
  1255. writel(0, &regs->LocalCtrl);
  1256. writel(0, &regs->EvtPrd);
  1257. writel(0, &regs->RxPrd);
  1258. writel(0, &regs->TxPrd);
  1259. /*
  1260. * First wipe the entire SRAM, otherwise we might run into all
  1261. * kinds of trouble ... sigh, this took almost all afternoon
  1262. * to track down ;-(
  1263. */
  1264. io = readl(&regs->ExtIo);
  1265. writel(0, &regs->ExtIo);
  1266. sram_size = rr_read_eeprom_word(rrpriv, 8);
  1267. for (i = 200; i < sram_size / 4; i++){
  1268. writel(i * 4, &regs->WinBase);
  1269. mb();
  1270. writel(0, &regs->WinData);
  1271. mb();
  1272. }
  1273. writel(io, &regs->ExtIo);
  1274. mb();
  1275. eptr = rr_read_eeprom_word(rrpriv,
  1276. offsetof(struct eeprom, rncd_info.AddrRunCodeSegs));
  1277. eptr = ((eptr & 0x1fffff) >> 3);
  1278. p2len = rr_read_eeprom_word(rrpriv, 0x83*4);
  1279. p2len = (p2len << 2);
  1280. p2size = rr_read_eeprom_word(rrpriv, 0x84*4);
  1281. p2size = ((p2size & 0x1fffff) >> 3);
  1282. if ((eptr < p2size) || (eptr > (p2size + p2len))){
  1283. printk("%s: eptr is invalid\n", dev->name);
  1284. goto out;
  1285. }
  1286. revision = rr_read_eeprom_word(rrpriv,
  1287. offsetof(struct eeprom, manf.HeaderFmt));
  1288. if (revision != 1){
  1289. printk("%s: invalid firmware format (%i)\n",
  1290. dev->name, revision);
  1291. goto out;
  1292. }
  1293. nr_seg = rr_read_eeprom_word(rrpriv, eptr);
  1294. eptr +=4;
  1295. #if (DEBUG > 1)
  1296. printk("%s: nr_seg %i\n", dev->name, nr_seg);
  1297. #endif
  1298. for (i = 0; i < nr_seg; i++){
  1299. sptr = rr_read_eeprom_word(rrpriv, eptr);
  1300. eptr += 4;
  1301. len = rr_read_eeprom_word(rrpriv, eptr);
  1302. eptr += 4;
  1303. segptr = rr_read_eeprom_word(rrpriv, eptr);
  1304. segptr = ((segptr & 0x1fffff) >> 3);
  1305. eptr += 4;
  1306. #if (DEBUG > 1)
  1307. printk("%s: segment %i, sram address %06x, length %04x, segptr %06x\n",
  1308. dev->name, i, sptr, len, segptr);
  1309. #endif
  1310. for (j = 0; j < len; j++){
  1311. tmp = rr_read_eeprom_word(rrpriv, segptr);
  1312. writel(sptr, &regs->WinBase);
  1313. mb();
  1314. writel(tmp, &regs->WinData);
  1315. mb();
  1316. segptr += 4;
  1317. sptr += 4;
  1318. }
  1319. }
  1320. out:
  1321. writel(localctrl, &regs->LocalCtrl);
  1322. mb();
  1323. return 0;
  1324. }
  1325. static int rr_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  1326. {
  1327. struct rr_private *rrpriv;
  1328. unsigned char *image, *oldimage;
  1329. unsigned long flags;
  1330. unsigned int i;
  1331. int error = -EOPNOTSUPP;
  1332. rrpriv = netdev_priv(dev);
  1333. switch(cmd){
  1334. case SIOCRRGFW:
  1335. if (!capable(CAP_SYS_RAWIO)){
  1336. return -EPERM;
  1337. }
  1338. image = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
  1339. if (!image)
  1340. return -ENOMEM;
  1341. if (rrpriv->fw_running){
  1342. printk("%s: Firmware already running\n", dev->name);
  1343. error = -EPERM;
  1344. goto gf_out;
  1345. }
  1346. spin_lock_irqsave(&rrpriv->lock, flags);
  1347. i = rr_read_eeprom(rrpriv, 0, image, EEPROM_BYTES);
  1348. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1349. if (i != EEPROM_BYTES){
  1350. printk(KERN_ERR "%s: Error reading EEPROM\n",
  1351. dev->name);
  1352. error = -EFAULT;
  1353. goto gf_out;
  1354. }
  1355. error = copy_to_user(rq->ifr_data, image, EEPROM_BYTES);
  1356. if (error)
  1357. error = -EFAULT;
  1358. gf_out:
  1359. kfree(image);
  1360. return error;
  1361. case SIOCRRPFW:
  1362. if (!capable(CAP_SYS_RAWIO)){
  1363. return -EPERM;
  1364. }
  1365. image = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
  1366. oldimage = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
  1367. if (!image || !oldimage) {
  1368. error = -ENOMEM;
  1369. goto wf_out;
  1370. }
  1371. error = copy_from_user(image, rq->ifr_data, EEPROM_BYTES);
  1372. if (error) {
  1373. error = -EFAULT;
  1374. goto wf_out;
  1375. }
  1376. if (rrpriv->fw_running){
  1377. printk("%s: Firmware already running\n", dev->name);
  1378. error = -EPERM;
  1379. goto wf_out;
  1380. }
  1381. printk("%s: Updating EEPROM firmware\n", dev->name);
  1382. spin_lock_irqsave(&rrpriv->lock, flags);
  1383. error = write_eeprom(rrpriv, 0, image, EEPROM_BYTES);
  1384. if (error)
  1385. printk(KERN_ERR "%s: Error writing EEPROM\n",
  1386. dev->name);
  1387. i = rr_read_eeprom(rrpriv, 0, oldimage, EEPROM_BYTES);
  1388. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1389. if (i != EEPROM_BYTES)
  1390. printk(KERN_ERR "%s: Error reading back EEPROM "
  1391. "image\n", dev->name);
  1392. error = memcmp(image, oldimage, EEPROM_BYTES);
  1393. if (error){
  1394. printk(KERN_ERR "%s: Error verifying EEPROM image\n",
  1395. dev->name);
  1396. error = -EFAULT;
  1397. }
  1398. wf_out:
  1399. kfree(oldimage);
  1400. kfree(image);
  1401. return error;
  1402. case SIOCRRID:
  1403. return put_user(0x52523032, (int __user *)rq->ifr_data);
  1404. default:
  1405. return error;
  1406. }
  1407. }
  1408. static const struct pci_device_id rr_pci_tbl[] = {
  1409. { PCI_VENDOR_ID_ESSENTIAL, PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER,
  1410. PCI_ANY_ID, PCI_ANY_ID, },
  1411. { 0,}
  1412. };
  1413. MODULE_DEVICE_TABLE(pci, rr_pci_tbl);
  1414. static struct pci_driver rr_driver = {
  1415. .name = "rrunner",
  1416. .id_table = rr_pci_tbl,
  1417. .probe = rr_init_one,
  1418. .remove = rr_remove_one,
  1419. };
  1420. module_pci_driver(rr_driver);