hw-txe.c 30 KB

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  1. /*
  2. *
  3. * Intel Management Engine Interface (Intel MEI) Linux driver
  4. * Copyright (c) 2013-2014, Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. */
  16. #include <linux/pci.h>
  17. #include <linux/jiffies.h>
  18. #include <linux/ktime.h>
  19. #include <linux/delay.h>
  20. #include <linux/kthread.h>
  21. #include <linux/irqreturn.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/mei.h>
  24. #include "mei_dev.h"
  25. #include "hw-txe.h"
  26. #include "client.h"
  27. #include "hbm.h"
  28. #include "mei-trace.h"
  29. /**
  30. * mei_txe_reg_read - Reads 32bit data from the txe device
  31. *
  32. * @base_addr: registers base address
  33. * @offset: register offset
  34. *
  35. * Return: register value
  36. */
  37. static inline u32 mei_txe_reg_read(void __iomem *base_addr,
  38. unsigned long offset)
  39. {
  40. return ioread32(base_addr + offset);
  41. }
  42. /**
  43. * mei_txe_reg_write - Writes 32bit data to the txe device
  44. *
  45. * @base_addr: registers base address
  46. * @offset: register offset
  47. * @value: the value to write
  48. */
  49. static inline void mei_txe_reg_write(void __iomem *base_addr,
  50. unsigned long offset, u32 value)
  51. {
  52. iowrite32(value, base_addr + offset);
  53. }
  54. /**
  55. * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR
  56. *
  57. * @hw: the txe hardware structure
  58. * @offset: register offset
  59. *
  60. * Doesn't check for aliveness while Reads 32bit data from the SeC BAR
  61. *
  62. * Return: register value
  63. */
  64. static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw,
  65. unsigned long offset)
  66. {
  67. return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset);
  68. }
  69. /**
  70. * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR
  71. *
  72. * @hw: the txe hardware structure
  73. * @offset: register offset
  74. *
  75. * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set
  76. *
  77. * Return: register value
  78. */
  79. static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw,
  80. unsigned long offset)
  81. {
  82. WARN(!hw->aliveness, "sec read: aliveness not asserted\n");
  83. return mei_txe_sec_reg_read_silent(hw, offset);
  84. }
  85. /**
  86. * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR
  87. * doesn't check for aliveness
  88. *
  89. * @hw: the txe hardware structure
  90. * @offset: register offset
  91. * @value: value to write
  92. *
  93. * Doesn't check for aliveness while writes 32bit data from to the SeC BAR
  94. */
  95. static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw,
  96. unsigned long offset, u32 value)
  97. {
  98. mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value);
  99. }
  100. /**
  101. * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR
  102. *
  103. * @hw: the txe hardware structure
  104. * @offset: register offset
  105. * @value: value to write
  106. *
  107. * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set
  108. */
  109. static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw,
  110. unsigned long offset, u32 value)
  111. {
  112. WARN(!hw->aliveness, "sec write: aliveness not asserted\n");
  113. mei_txe_sec_reg_write_silent(hw, offset, value);
  114. }
  115. /**
  116. * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR
  117. *
  118. * @hw: the txe hardware structure
  119. * @offset: offset from which to read the data
  120. *
  121. * Return: the byte read.
  122. */
  123. static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw,
  124. unsigned long offset)
  125. {
  126. return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset);
  127. }
  128. /**
  129. * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR
  130. *
  131. * @hw: the txe hardware structure
  132. * @offset: offset from which to write the data
  133. * @value: the byte to write
  134. */
  135. static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw,
  136. unsigned long offset, u32 value)
  137. {
  138. mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value);
  139. }
  140. /**
  141. * mei_txe_aliveness_set - request for aliveness change
  142. *
  143. * @dev: the device structure
  144. * @req: requested aliveness value
  145. *
  146. * Request for aliveness change and returns true if the change is
  147. * really needed and false if aliveness is already
  148. * in the requested state
  149. *
  150. * Locking: called under "dev->device_lock" lock
  151. *
  152. * Return: true if request was send
  153. */
  154. static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req)
  155. {
  156. struct mei_txe_hw *hw = to_txe_hw(dev);
  157. bool do_req = hw->aliveness != req;
  158. dev_dbg(dev->dev, "Aliveness current=%d request=%d\n",
  159. hw->aliveness, req);
  160. if (do_req) {
  161. dev->pg_event = MEI_PG_EVENT_WAIT;
  162. mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req);
  163. }
  164. return do_req;
  165. }
  166. /**
  167. * mei_txe_aliveness_req_get - get aliveness requested register value
  168. *
  169. * @dev: the device structure
  170. *
  171. * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from
  172. * from HICR_HOST_ALIVENESS_REQ register value
  173. *
  174. * Return: SICR_HOST_ALIVENESS_REQ_REQUESTED bit value
  175. */
  176. static u32 mei_txe_aliveness_req_get(struct mei_device *dev)
  177. {
  178. struct mei_txe_hw *hw = to_txe_hw(dev);
  179. u32 reg;
  180. reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG);
  181. return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED;
  182. }
  183. /**
  184. * mei_txe_aliveness_get - get aliveness response register value
  185. *
  186. * @dev: the device structure
  187. *
  188. * Return: HICR_HOST_ALIVENESS_RESP_ACK bit from HICR_HOST_ALIVENESS_RESP
  189. * register
  190. */
  191. static u32 mei_txe_aliveness_get(struct mei_device *dev)
  192. {
  193. struct mei_txe_hw *hw = to_txe_hw(dev);
  194. u32 reg;
  195. reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG);
  196. return reg & HICR_HOST_ALIVENESS_RESP_ACK;
  197. }
  198. /**
  199. * mei_txe_aliveness_poll - waits for aliveness to settle
  200. *
  201. * @dev: the device structure
  202. * @expected: expected aliveness value
  203. *
  204. * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
  205. *
  206. * Return: 0 if the expected value was received, -ETIME otherwise
  207. */
  208. static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected)
  209. {
  210. struct mei_txe_hw *hw = to_txe_hw(dev);
  211. ktime_t stop, start;
  212. start = ktime_get();
  213. stop = ktime_add(start, ms_to_ktime(SEC_ALIVENESS_WAIT_TIMEOUT));
  214. do {
  215. hw->aliveness = mei_txe_aliveness_get(dev);
  216. if (hw->aliveness == expected) {
  217. dev->pg_event = MEI_PG_EVENT_IDLE;
  218. dev_dbg(dev->dev, "aliveness settled after %lld usecs\n",
  219. ktime_to_us(ktime_sub(ktime_get(), start)));
  220. return 0;
  221. }
  222. usleep_range(20, 50);
  223. } while (ktime_before(ktime_get(), stop));
  224. dev->pg_event = MEI_PG_EVENT_IDLE;
  225. dev_err(dev->dev, "aliveness timed out\n");
  226. return -ETIME;
  227. }
  228. /**
  229. * mei_txe_aliveness_wait - waits for aliveness to settle
  230. *
  231. * @dev: the device structure
  232. * @expected: expected aliveness value
  233. *
  234. * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
  235. *
  236. * Return: 0 on success and < 0 otherwise
  237. */
  238. static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected)
  239. {
  240. struct mei_txe_hw *hw = to_txe_hw(dev);
  241. const unsigned long timeout =
  242. msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT);
  243. long err;
  244. int ret;
  245. hw->aliveness = mei_txe_aliveness_get(dev);
  246. if (hw->aliveness == expected)
  247. return 0;
  248. mutex_unlock(&dev->device_lock);
  249. err = wait_event_timeout(hw->wait_aliveness_resp,
  250. dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
  251. mutex_lock(&dev->device_lock);
  252. hw->aliveness = mei_txe_aliveness_get(dev);
  253. ret = hw->aliveness == expected ? 0 : -ETIME;
  254. if (ret)
  255. dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n",
  256. err, hw->aliveness, dev->pg_event);
  257. else
  258. dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n",
  259. jiffies_to_msecs(timeout - err),
  260. hw->aliveness, dev->pg_event);
  261. dev->pg_event = MEI_PG_EVENT_IDLE;
  262. return ret;
  263. }
  264. /**
  265. * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete
  266. *
  267. * @dev: the device structure
  268. * @req: requested aliveness value
  269. *
  270. * Return: 0 on success and < 0 otherwise
  271. */
  272. int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req)
  273. {
  274. if (mei_txe_aliveness_set(dev, req))
  275. return mei_txe_aliveness_wait(dev, req);
  276. return 0;
  277. }
  278. /**
  279. * mei_txe_pg_in_transition - is device now in pg transition
  280. *
  281. * @dev: the device structure
  282. *
  283. * Return: true if in pg transition, false otherwise
  284. */
  285. static bool mei_txe_pg_in_transition(struct mei_device *dev)
  286. {
  287. return dev->pg_event == MEI_PG_EVENT_WAIT;
  288. }
  289. /**
  290. * mei_txe_pg_is_enabled - detect if PG is supported by HW
  291. *
  292. * @dev: the device structure
  293. *
  294. * Return: true is pg supported, false otherwise
  295. */
  296. static bool mei_txe_pg_is_enabled(struct mei_device *dev)
  297. {
  298. return true;
  299. }
  300. /**
  301. * mei_txe_pg_state - translate aliveness register value
  302. * to the mei power gating state
  303. *
  304. * @dev: the device structure
  305. *
  306. * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
  307. */
  308. static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev)
  309. {
  310. struct mei_txe_hw *hw = to_txe_hw(dev);
  311. return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON;
  312. }
  313. /**
  314. * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt
  315. *
  316. * @dev: the device structure
  317. */
  318. static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev)
  319. {
  320. struct mei_txe_hw *hw = to_txe_hw(dev);
  321. u32 hintmsk;
  322. /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */
  323. hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG);
  324. hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY;
  325. mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk);
  326. }
  327. /**
  328. * mei_txe_input_doorbell_set - sets bit 0 in
  329. * SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL.
  330. *
  331. * @hw: the txe hardware structure
  332. */
  333. static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw)
  334. {
  335. /* Clear the interrupt cause */
  336. clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause);
  337. mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1);
  338. }
  339. /**
  340. * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1
  341. *
  342. * @hw: the txe hardware structure
  343. */
  344. static void mei_txe_output_ready_set(struct mei_txe_hw *hw)
  345. {
  346. mei_txe_br_reg_write(hw,
  347. SICR_SEC_IPC_OUTPUT_STATUS_REG,
  348. SEC_IPC_OUTPUT_STATUS_RDY);
  349. }
  350. /**
  351. * mei_txe_is_input_ready - check if TXE is ready for receiving data
  352. *
  353. * @dev: the device structure
  354. *
  355. * Return: true if INPUT STATUS READY bit is set
  356. */
  357. static bool mei_txe_is_input_ready(struct mei_device *dev)
  358. {
  359. struct mei_txe_hw *hw = to_txe_hw(dev);
  360. u32 status;
  361. status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG);
  362. return !!(SEC_IPC_INPUT_STATUS_RDY & status);
  363. }
  364. /**
  365. * mei_txe_intr_clear - clear all interrupts
  366. *
  367. * @dev: the device structure
  368. */
  369. static inline void mei_txe_intr_clear(struct mei_device *dev)
  370. {
  371. struct mei_txe_hw *hw = to_txe_hw(dev);
  372. mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG,
  373. SEC_IPC_HOST_INT_STATUS_PENDING);
  374. mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK);
  375. mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK);
  376. }
  377. /**
  378. * mei_txe_intr_disable - disable all interrupts
  379. *
  380. * @dev: the device structure
  381. */
  382. static void mei_txe_intr_disable(struct mei_device *dev)
  383. {
  384. struct mei_txe_hw *hw = to_txe_hw(dev);
  385. mei_txe_br_reg_write(hw, HHIER_REG, 0);
  386. mei_txe_br_reg_write(hw, HIER_REG, 0);
  387. }
  388. /**
  389. * mei_txe_intr_enable - enable all interrupts
  390. *
  391. * @dev: the device structure
  392. */
  393. static void mei_txe_intr_enable(struct mei_device *dev)
  394. {
  395. struct mei_txe_hw *hw = to_txe_hw(dev);
  396. mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK);
  397. mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK);
  398. }
  399. /**
  400. * mei_txe_pending_interrupts - check if there are pending interrupts
  401. * only Aliveness, Input ready, and output doorbell are of relevance
  402. *
  403. * @dev: the device structure
  404. *
  405. * Checks if there are pending interrupts
  406. * only Aliveness, Readiness, Input ready, and Output doorbell are relevant
  407. *
  408. * Return: true if there are pending interrupts
  409. */
  410. static bool mei_txe_pending_interrupts(struct mei_device *dev)
  411. {
  412. struct mei_txe_hw *hw = to_txe_hw(dev);
  413. bool ret = (hw->intr_cause & (TXE_INTR_READINESS |
  414. TXE_INTR_ALIVENESS |
  415. TXE_INTR_IN_READY |
  416. TXE_INTR_OUT_DB));
  417. if (ret) {
  418. dev_dbg(dev->dev,
  419. "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n",
  420. !!(hw->intr_cause & TXE_INTR_IN_READY),
  421. !!(hw->intr_cause & TXE_INTR_READINESS),
  422. !!(hw->intr_cause & TXE_INTR_ALIVENESS),
  423. !!(hw->intr_cause & TXE_INTR_OUT_DB));
  424. }
  425. return ret;
  426. }
  427. /**
  428. * mei_txe_input_payload_write - write a dword to the host buffer
  429. * at offset idx
  430. *
  431. * @dev: the device structure
  432. * @idx: index in the host buffer
  433. * @value: value
  434. */
  435. static void mei_txe_input_payload_write(struct mei_device *dev,
  436. unsigned long idx, u32 value)
  437. {
  438. struct mei_txe_hw *hw = to_txe_hw(dev);
  439. mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG +
  440. (idx * sizeof(u32)), value);
  441. }
  442. /**
  443. * mei_txe_out_data_read - read dword from the device buffer
  444. * at offset idx
  445. *
  446. * @dev: the device structure
  447. * @idx: index in the device buffer
  448. *
  449. * Return: register value at index
  450. */
  451. static u32 mei_txe_out_data_read(const struct mei_device *dev,
  452. unsigned long idx)
  453. {
  454. struct mei_txe_hw *hw = to_txe_hw(dev);
  455. return mei_txe_br_reg_read(hw,
  456. BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32)));
  457. }
  458. /* Readiness */
  459. /**
  460. * mei_txe_readiness_set_host_rdy - set host readiness bit
  461. *
  462. * @dev: the device structure
  463. */
  464. static void mei_txe_readiness_set_host_rdy(struct mei_device *dev)
  465. {
  466. struct mei_txe_hw *hw = to_txe_hw(dev);
  467. mei_txe_br_reg_write(hw,
  468. SICR_HOST_IPC_READINESS_REQ_REG,
  469. SICR_HOST_IPC_READINESS_HOST_RDY);
  470. }
  471. /**
  472. * mei_txe_readiness_clear - clear host readiness bit
  473. *
  474. * @dev: the device structure
  475. */
  476. static void mei_txe_readiness_clear(struct mei_device *dev)
  477. {
  478. struct mei_txe_hw *hw = to_txe_hw(dev);
  479. mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG,
  480. SICR_HOST_IPC_READINESS_RDY_CLR);
  481. }
  482. /**
  483. * mei_txe_readiness_get - Reads and returns
  484. * the HICR_SEC_IPC_READINESS register value
  485. *
  486. * @dev: the device structure
  487. *
  488. * Return: the HICR_SEC_IPC_READINESS register value
  489. */
  490. static u32 mei_txe_readiness_get(struct mei_device *dev)
  491. {
  492. struct mei_txe_hw *hw = to_txe_hw(dev);
  493. return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
  494. }
  495. /**
  496. * mei_txe_readiness_is_sec_rdy - check readiness
  497. * for HICR_SEC_IPC_READINESS_SEC_RDY
  498. *
  499. * @readiness: cached readiness state
  500. *
  501. * Return: true if readiness bit is set
  502. */
  503. static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness)
  504. {
  505. return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY);
  506. }
  507. /**
  508. * mei_txe_hw_is_ready - check if the hw is ready
  509. *
  510. * @dev: the device structure
  511. *
  512. * Return: true if sec is ready
  513. */
  514. static bool mei_txe_hw_is_ready(struct mei_device *dev)
  515. {
  516. u32 readiness = mei_txe_readiness_get(dev);
  517. return mei_txe_readiness_is_sec_rdy(readiness);
  518. }
  519. /**
  520. * mei_txe_host_is_ready - check if the host is ready
  521. *
  522. * @dev: the device structure
  523. *
  524. * Return: true if host is ready
  525. */
  526. static inline bool mei_txe_host_is_ready(struct mei_device *dev)
  527. {
  528. struct mei_txe_hw *hw = to_txe_hw(dev);
  529. u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
  530. return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY);
  531. }
  532. /**
  533. * mei_txe_readiness_wait - wait till readiness settles
  534. *
  535. * @dev: the device structure
  536. *
  537. * Return: 0 on success and -ETIME on timeout
  538. */
  539. static int mei_txe_readiness_wait(struct mei_device *dev)
  540. {
  541. if (mei_txe_hw_is_ready(dev))
  542. return 0;
  543. mutex_unlock(&dev->device_lock);
  544. wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready,
  545. msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT));
  546. mutex_lock(&dev->device_lock);
  547. if (!dev->recvd_hw_ready) {
  548. dev_err(dev->dev, "wait for readiness failed\n");
  549. return -ETIME;
  550. }
  551. dev->recvd_hw_ready = false;
  552. return 0;
  553. }
  554. static const struct mei_fw_status mei_txe_fw_sts = {
  555. .count = 2,
  556. .status[0] = PCI_CFG_TXE_FW_STS0,
  557. .status[1] = PCI_CFG_TXE_FW_STS1
  558. };
  559. /**
  560. * mei_txe_fw_status - read fw status register from pci config space
  561. *
  562. * @dev: mei device
  563. * @fw_status: fw status register values
  564. *
  565. * Return: 0 on success, error otherwise
  566. */
  567. static int mei_txe_fw_status(struct mei_device *dev,
  568. struct mei_fw_status *fw_status)
  569. {
  570. const struct mei_fw_status *fw_src = &mei_txe_fw_sts;
  571. struct pci_dev *pdev = to_pci_dev(dev->dev);
  572. int ret;
  573. int i;
  574. if (!fw_status)
  575. return -EINVAL;
  576. fw_status->count = fw_src->count;
  577. for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
  578. ret = pci_read_config_dword(pdev, fw_src->status[i],
  579. &fw_status->status[i]);
  580. trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X",
  581. fw_src->status[i],
  582. fw_status->status[i]);
  583. if (ret)
  584. return ret;
  585. }
  586. return 0;
  587. }
  588. /**
  589. * mei_txe_hw_config - configure hardware at the start of the devices
  590. *
  591. * @dev: the device structure
  592. *
  593. * Configure hardware at the start of the device should be done only
  594. * once at the device probe time
  595. */
  596. static void mei_txe_hw_config(struct mei_device *dev)
  597. {
  598. struct mei_txe_hw *hw = to_txe_hw(dev);
  599. /* Doesn't change in runtime */
  600. dev->hbuf_depth = PAYLOAD_SIZE / 4;
  601. hw->aliveness = mei_txe_aliveness_get(dev);
  602. hw->readiness = mei_txe_readiness_get(dev);
  603. dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n",
  604. hw->aliveness, hw->readiness);
  605. }
  606. /**
  607. * mei_txe_write - writes a message to device.
  608. *
  609. * @dev: the device structure
  610. * @header: header of message
  611. * @buf: message buffer will be written
  612. *
  613. * Return: 0 if success, <0 - otherwise.
  614. */
  615. static int mei_txe_write(struct mei_device *dev,
  616. struct mei_msg_hdr *header, unsigned char *buf)
  617. {
  618. struct mei_txe_hw *hw = to_txe_hw(dev);
  619. unsigned long rem;
  620. unsigned long length;
  621. int slots = dev->hbuf_depth;
  622. u32 *reg_buf = (u32 *)buf;
  623. u32 dw_cnt;
  624. int i;
  625. if (WARN_ON(!header || !buf))
  626. return -EINVAL;
  627. length = header->length;
  628. dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
  629. dw_cnt = mei_data2slots(length);
  630. if (dw_cnt > slots)
  631. return -EMSGSIZE;
  632. if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n"))
  633. return -EAGAIN;
  634. /* Enable Input Ready Interrupt. */
  635. mei_txe_input_ready_interrupt_enable(dev);
  636. if (!mei_txe_is_input_ready(dev)) {
  637. char fw_sts_str[MEI_FW_STATUS_STR_SZ];
  638. mei_fw_status_str(dev, fw_sts_str, MEI_FW_STATUS_STR_SZ);
  639. dev_err(dev->dev, "Input is not ready %s\n", fw_sts_str);
  640. return -EAGAIN;
  641. }
  642. mei_txe_input_payload_write(dev, 0, *((u32 *)header));
  643. for (i = 0; i < length / 4; i++)
  644. mei_txe_input_payload_write(dev, i + 1, reg_buf[i]);
  645. rem = length & 0x3;
  646. if (rem > 0) {
  647. u32 reg = 0;
  648. memcpy(&reg, &buf[length - rem], rem);
  649. mei_txe_input_payload_write(dev, i + 1, reg);
  650. }
  651. /* after each write the whole buffer is consumed */
  652. hw->slots = 0;
  653. /* Set Input-Doorbell */
  654. mei_txe_input_doorbell_set(hw);
  655. return 0;
  656. }
  657. /**
  658. * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer
  659. *
  660. * @dev: the device structure
  661. *
  662. * Return: the PAYLOAD_SIZE - 4
  663. */
  664. static size_t mei_txe_hbuf_max_len(const struct mei_device *dev)
  665. {
  666. return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr);
  667. }
  668. /**
  669. * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer
  670. *
  671. * @dev: the device structure
  672. *
  673. * Return: always hbuf_depth
  674. */
  675. static int mei_txe_hbuf_empty_slots(struct mei_device *dev)
  676. {
  677. struct mei_txe_hw *hw = to_txe_hw(dev);
  678. return hw->slots;
  679. }
  680. /**
  681. * mei_txe_count_full_read_slots - mimics the me device circular buffer
  682. *
  683. * @dev: the device structure
  684. *
  685. * Return: always buffer size in dwords count
  686. */
  687. static int mei_txe_count_full_read_slots(struct mei_device *dev)
  688. {
  689. /* read buffers has static size */
  690. return PAYLOAD_SIZE / 4;
  691. }
  692. /**
  693. * mei_txe_read_hdr - read message header which is always in 4 first bytes
  694. *
  695. * @dev: the device structure
  696. *
  697. * Return: mei message header
  698. */
  699. static u32 mei_txe_read_hdr(const struct mei_device *dev)
  700. {
  701. return mei_txe_out_data_read(dev, 0);
  702. }
  703. /**
  704. * mei_txe_read - reads a message from the txe device.
  705. *
  706. * @dev: the device structure
  707. * @buf: message buffer will be written
  708. * @len: message size will be read
  709. *
  710. * Return: -EINVAL on error wrong argument and 0 on success
  711. */
  712. static int mei_txe_read(struct mei_device *dev,
  713. unsigned char *buf, unsigned long len)
  714. {
  715. struct mei_txe_hw *hw = to_txe_hw(dev);
  716. u32 *reg_buf, reg;
  717. u32 rem;
  718. u32 i;
  719. if (WARN_ON(!buf || !len))
  720. return -EINVAL;
  721. reg_buf = (u32 *)buf;
  722. rem = len & 0x3;
  723. dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n",
  724. len, mei_txe_out_data_read(dev, 0));
  725. for (i = 0; i < len / 4; i++) {
  726. /* skip header: index starts from 1 */
  727. reg = mei_txe_out_data_read(dev, i + 1);
  728. dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg);
  729. *reg_buf++ = reg;
  730. }
  731. if (rem) {
  732. reg = mei_txe_out_data_read(dev, i + 1);
  733. memcpy(reg_buf, &reg, rem);
  734. }
  735. mei_txe_output_ready_set(hw);
  736. return 0;
  737. }
  738. /**
  739. * mei_txe_hw_reset - resets host and fw.
  740. *
  741. * @dev: the device structure
  742. * @intr_enable: if interrupt should be enabled after reset.
  743. *
  744. * Return: 0 on success and < 0 in case of error
  745. */
  746. static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable)
  747. {
  748. struct mei_txe_hw *hw = to_txe_hw(dev);
  749. u32 aliveness_req;
  750. /*
  751. * read input doorbell to ensure consistency between Bridge and SeC
  752. * return value might be garbage return
  753. */
  754. (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG);
  755. aliveness_req = mei_txe_aliveness_req_get(dev);
  756. hw->aliveness = mei_txe_aliveness_get(dev);
  757. /* Disable interrupts in this stage we will poll */
  758. mei_txe_intr_disable(dev);
  759. /*
  760. * If Aliveness Request and Aliveness Response are not equal then
  761. * wait for them to be equal
  762. * Since we might have interrupts disabled - poll for it
  763. */
  764. if (aliveness_req != hw->aliveness)
  765. if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) {
  766. dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n");
  767. return -EIO;
  768. }
  769. /*
  770. * If Aliveness Request and Aliveness Response are set then clear them
  771. */
  772. if (aliveness_req) {
  773. mei_txe_aliveness_set(dev, 0);
  774. if (mei_txe_aliveness_poll(dev, 0) < 0) {
  775. dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
  776. return -EIO;
  777. }
  778. }
  779. /*
  780. * Set readiness RDY_CLR bit
  781. */
  782. mei_txe_readiness_clear(dev);
  783. return 0;
  784. }
  785. /**
  786. * mei_txe_hw_start - start the hardware after reset
  787. *
  788. * @dev: the device structure
  789. *
  790. * Return: 0 on success an error code otherwise
  791. */
  792. static int mei_txe_hw_start(struct mei_device *dev)
  793. {
  794. struct mei_txe_hw *hw = to_txe_hw(dev);
  795. int ret;
  796. u32 hisr;
  797. /* bring back interrupts */
  798. mei_txe_intr_enable(dev);
  799. ret = mei_txe_readiness_wait(dev);
  800. if (ret < 0) {
  801. dev_err(dev->dev, "waiting for readiness failed\n");
  802. return ret;
  803. }
  804. /*
  805. * If HISR.INT2_STS interrupt status bit is set then clear it.
  806. */
  807. hisr = mei_txe_br_reg_read(hw, HISR_REG);
  808. if (hisr & HISR_INT_2_STS)
  809. mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS);
  810. /* Clear the interrupt cause of OutputDoorbell */
  811. clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause);
  812. ret = mei_txe_aliveness_set_sync(dev, 1);
  813. if (ret < 0) {
  814. dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
  815. return ret;
  816. }
  817. pm_runtime_set_active(dev->dev);
  818. /* enable input ready interrupts:
  819. * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK
  820. */
  821. mei_txe_input_ready_interrupt_enable(dev);
  822. /* Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */
  823. mei_txe_output_ready_set(hw);
  824. /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY
  825. */
  826. mei_txe_readiness_set_host_rdy(dev);
  827. return 0;
  828. }
  829. /**
  830. * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into
  831. * single bit mask and acknowledge the interrupts
  832. *
  833. * @dev: the device structure
  834. * @do_ack: acknowledge interrupts
  835. *
  836. * Return: true if found interrupts to process.
  837. */
  838. static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack)
  839. {
  840. struct mei_txe_hw *hw = to_txe_hw(dev);
  841. u32 hisr;
  842. u32 hhisr;
  843. u32 ipc_isr;
  844. u32 aliveness;
  845. bool generated;
  846. /* read interrupt registers */
  847. hhisr = mei_txe_br_reg_read(hw, HHISR_REG);
  848. generated = (hhisr & IPC_HHIER_MSK);
  849. if (!generated)
  850. goto out;
  851. hisr = mei_txe_br_reg_read(hw, HISR_REG);
  852. aliveness = mei_txe_aliveness_get(dev);
  853. if (hhisr & IPC_HHIER_SEC && aliveness) {
  854. ipc_isr = mei_txe_sec_reg_read_silent(hw,
  855. SEC_IPC_HOST_INT_STATUS_REG);
  856. } else {
  857. ipc_isr = 0;
  858. hhisr &= ~IPC_HHIER_SEC;
  859. }
  860. generated = generated ||
  861. (hisr & HISR_INT_STS_MSK) ||
  862. (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING);
  863. if (generated && do_ack) {
  864. /* Save the interrupt causes */
  865. hw->intr_cause |= hisr & HISR_INT_STS_MSK;
  866. if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY)
  867. hw->intr_cause |= TXE_INTR_IN_READY;
  868. mei_txe_intr_disable(dev);
  869. /* Clear the interrupts in hierarchy:
  870. * IPC and Bridge, than the High Level */
  871. mei_txe_sec_reg_write_silent(hw,
  872. SEC_IPC_HOST_INT_STATUS_REG, ipc_isr);
  873. mei_txe_br_reg_write(hw, HISR_REG, hisr);
  874. mei_txe_br_reg_write(hw, HHISR_REG, hhisr);
  875. }
  876. out:
  877. return generated;
  878. }
  879. /**
  880. * mei_txe_irq_quick_handler - The ISR of the MEI device
  881. *
  882. * @irq: The irq number
  883. * @dev_id: pointer to the device structure
  884. *
  885. * Return: IRQ_WAKE_THREAD if interrupt is designed for the device
  886. * IRQ_NONE otherwise
  887. */
  888. irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id)
  889. {
  890. struct mei_device *dev = dev_id;
  891. if (mei_txe_check_and_ack_intrs(dev, true))
  892. return IRQ_WAKE_THREAD;
  893. return IRQ_NONE;
  894. }
  895. /**
  896. * mei_txe_irq_thread_handler - txe interrupt thread
  897. *
  898. * @irq: The irq number
  899. * @dev_id: pointer to the device structure
  900. *
  901. * Return: IRQ_HANDLED
  902. */
  903. irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id)
  904. {
  905. struct mei_device *dev = (struct mei_device *) dev_id;
  906. struct mei_txe_hw *hw = to_txe_hw(dev);
  907. struct mei_cl_cb complete_list;
  908. s32 slots;
  909. int rets = 0;
  910. dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n",
  911. mei_txe_br_reg_read(hw, HHISR_REG),
  912. mei_txe_br_reg_read(hw, HISR_REG),
  913. mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG));
  914. /* initialize our complete list */
  915. mutex_lock(&dev->device_lock);
  916. mei_io_list_init(&complete_list);
  917. if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))
  918. mei_txe_check_and_ack_intrs(dev, true);
  919. /* show irq events */
  920. mei_txe_pending_interrupts(dev);
  921. hw->aliveness = mei_txe_aliveness_get(dev);
  922. hw->readiness = mei_txe_readiness_get(dev);
  923. /* Readiness:
  924. * Detection of TXE driver going through reset
  925. * or TXE driver resetting the HECI interface.
  926. */
  927. if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) {
  928. dev_dbg(dev->dev, "Readiness Interrupt was received...\n");
  929. /* Check if SeC is going through reset */
  930. if (mei_txe_readiness_is_sec_rdy(hw->readiness)) {
  931. dev_dbg(dev->dev, "we need to start the dev.\n");
  932. dev->recvd_hw_ready = true;
  933. } else {
  934. dev->recvd_hw_ready = false;
  935. if (dev->dev_state != MEI_DEV_RESETTING) {
  936. dev_warn(dev->dev, "FW not ready: resetting.\n");
  937. schedule_work(&dev->reset_work);
  938. goto end;
  939. }
  940. }
  941. wake_up(&dev->wait_hw_ready);
  942. }
  943. /************************************************************/
  944. /* Check interrupt cause:
  945. * Aliveness: Detection of SeC acknowledge of host request that
  946. * it remain alive or host cancellation of that request.
  947. */
  948. if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) {
  949. /* Clear the interrupt cause */
  950. dev_dbg(dev->dev,
  951. "Aliveness Interrupt: Status: %d\n", hw->aliveness);
  952. dev->pg_event = MEI_PG_EVENT_RECEIVED;
  953. if (waitqueue_active(&hw->wait_aliveness_resp))
  954. wake_up(&hw->wait_aliveness_resp);
  955. }
  956. /* Output Doorbell:
  957. * Detection of SeC having sent output to host
  958. */
  959. slots = mei_count_full_read_slots(dev);
  960. if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) {
  961. /* Read from TXE */
  962. rets = mei_irq_read_handler(dev, &complete_list, &slots);
  963. if (rets && dev->dev_state != MEI_DEV_RESETTING) {
  964. dev_err(dev->dev,
  965. "mei_irq_read_handler ret = %d.\n", rets);
  966. schedule_work(&dev->reset_work);
  967. goto end;
  968. }
  969. }
  970. /* Input Ready: Detection if host can write to SeC */
  971. if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) {
  972. dev->hbuf_is_ready = true;
  973. hw->slots = dev->hbuf_depth;
  974. }
  975. if (hw->aliveness && dev->hbuf_is_ready) {
  976. /* get the real register value */
  977. dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
  978. rets = mei_irq_write_handler(dev, &complete_list);
  979. if (rets && rets != -EMSGSIZE)
  980. dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n",
  981. rets);
  982. dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
  983. }
  984. mei_irq_compl_handler(dev, &complete_list);
  985. end:
  986. dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
  987. mutex_unlock(&dev->device_lock);
  988. mei_enable_interrupts(dev);
  989. return IRQ_HANDLED;
  990. }
  991. static const struct mei_hw_ops mei_txe_hw_ops = {
  992. .host_is_ready = mei_txe_host_is_ready,
  993. .fw_status = mei_txe_fw_status,
  994. .pg_state = mei_txe_pg_state,
  995. .hw_is_ready = mei_txe_hw_is_ready,
  996. .hw_reset = mei_txe_hw_reset,
  997. .hw_config = mei_txe_hw_config,
  998. .hw_start = mei_txe_hw_start,
  999. .pg_in_transition = mei_txe_pg_in_transition,
  1000. .pg_is_enabled = mei_txe_pg_is_enabled,
  1001. .intr_clear = mei_txe_intr_clear,
  1002. .intr_enable = mei_txe_intr_enable,
  1003. .intr_disable = mei_txe_intr_disable,
  1004. .hbuf_free_slots = mei_txe_hbuf_empty_slots,
  1005. .hbuf_is_ready = mei_txe_is_input_ready,
  1006. .hbuf_max_len = mei_txe_hbuf_max_len,
  1007. .write = mei_txe_write,
  1008. .rdbuf_full_slots = mei_txe_count_full_read_slots,
  1009. .read_hdr = mei_txe_read_hdr,
  1010. .read = mei_txe_read,
  1011. };
  1012. /**
  1013. * mei_txe_dev_init - allocates and initializes txe hardware specific structure
  1014. *
  1015. * @pdev: pci device
  1016. *
  1017. * Return: struct mei_device * on success or NULL
  1018. */
  1019. struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
  1020. {
  1021. struct mei_device *dev;
  1022. struct mei_txe_hw *hw;
  1023. dev = kzalloc(sizeof(struct mei_device) +
  1024. sizeof(struct mei_txe_hw), GFP_KERNEL);
  1025. if (!dev)
  1026. return NULL;
  1027. mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops);
  1028. hw = to_txe_hw(dev);
  1029. init_waitqueue_head(&hw->wait_aliveness_resp);
  1030. return dev;
  1031. }
  1032. /**
  1033. * mei_txe_setup_satt2 - SATT2 configuration for DMA support.
  1034. *
  1035. * @dev: the device structure
  1036. * @addr: physical address start of the range
  1037. * @range: physical range size
  1038. *
  1039. * Return: 0 on success an error code otherwise
  1040. */
  1041. int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range)
  1042. {
  1043. struct mei_txe_hw *hw = to_txe_hw(dev);
  1044. u32 lo32 = lower_32_bits(addr);
  1045. u32 hi32 = upper_32_bits(addr);
  1046. u32 ctrl;
  1047. /* SATT is limited to 36 Bits */
  1048. if (hi32 & ~0xF)
  1049. return -EINVAL;
  1050. /* SATT has to be 16Byte aligned */
  1051. if (lo32 & 0xF)
  1052. return -EINVAL;
  1053. /* SATT range has to be 4Bytes aligned */
  1054. if (range & 0x4)
  1055. return -EINVAL;
  1056. /* SATT is limited to 32 MB range*/
  1057. if (range > SATT_RANGE_MAX)
  1058. return -EINVAL;
  1059. ctrl = SATT2_CTRL_VALID_MSK;
  1060. ctrl |= hi32 << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT;
  1061. mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range);
  1062. mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32);
  1063. mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl);
  1064. dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n",
  1065. range, lo32, ctrl);
  1066. return 0;
  1067. }