irq-bcm2835.c 7.4 KB

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  1. /*
  2. * Copyright 2010 Broadcom
  3. * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
  16. *
  17. * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
  18. * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
  19. * to look in the bank 1 status register for more information.
  20. *
  21. * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
  22. * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
  23. * status register, but bank 0 bit 8 is _not_ set.
  24. *
  25. * Quirk 2: You can't mask the register 1/2 pending interrupts
  26. *
  27. * In a proper cascaded interrupt controller, the interrupt lines with
  28. * cascaded interrupt controllers on them are just normal interrupt lines.
  29. * You can mask the interrupts and get on with things. With this controller
  30. * you can't do that.
  31. *
  32. * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
  33. *
  34. * Those interrupts that have shortcuts can only be masked/unmasked in
  35. * their respective banks' enable/disable registers. Doing so in the bank 0
  36. * enable/disable registers has no effect.
  37. *
  38. * The FIQ control register:
  39. * Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
  40. * Bit 7: Enable FIQ generation
  41. * Bits 8+: Unused
  42. *
  43. * An interrupt must be disabled before configuring it for FIQ generation
  44. * otherwise both handlers will fire at the same time!
  45. */
  46. #include <linux/io.h>
  47. #include <linux/slab.h>
  48. #include <linux/of_address.h>
  49. #include <linux/of_irq.h>
  50. #include <linux/irqchip.h>
  51. #include <linux/irqdomain.h>
  52. #include <asm/exception.h>
  53. /* Put the bank and irq (32 bits) into the hwirq */
  54. #define MAKE_HWIRQ(b, n) ((b << 5) | (n))
  55. #define HWIRQ_BANK(i) (i >> 5)
  56. #define HWIRQ_BIT(i) BIT(i & 0x1f)
  57. #define NR_IRQS_BANK0 8
  58. #define BANK0_HWIRQ_MASK 0xff
  59. /* Shortcuts can't be disabled so any unknown new ones need to be masked */
  60. #define SHORTCUT1_MASK 0x00007c00
  61. #define SHORTCUT2_MASK 0x001f8000
  62. #define SHORTCUT_SHIFT 10
  63. #define BANK1_HWIRQ BIT(8)
  64. #define BANK2_HWIRQ BIT(9)
  65. #define BANK0_VALID_MASK (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
  66. | SHORTCUT1_MASK | SHORTCUT2_MASK)
  67. #define REG_FIQ_CONTROL 0x0c
  68. #define NR_BANKS 3
  69. #define IRQS_PER_BANK 32
  70. static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
  71. static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
  72. static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
  73. static const int bank_irqs[] __initconst = { 8, 32, 32 };
  74. static const int shortcuts[] = {
  75. 7, 9, 10, 18, 19, /* Bank 1 */
  76. 21, 22, 23, 24, 25, 30 /* Bank 2 */
  77. };
  78. struct armctrl_ic {
  79. void __iomem *base;
  80. void __iomem *pending[NR_BANKS];
  81. void __iomem *enable[NR_BANKS];
  82. void __iomem *disable[NR_BANKS];
  83. struct irq_domain *domain;
  84. };
  85. static struct armctrl_ic intc __read_mostly;
  86. static void __exception_irq_entry bcm2835_handle_irq(
  87. struct pt_regs *regs);
  88. static void bcm2836_chained_handle_irq(struct irq_desc *desc);
  89. static void armctrl_mask_irq(struct irq_data *d)
  90. {
  91. writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
  92. }
  93. static void armctrl_unmask_irq(struct irq_data *d)
  94. {
  95. writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
  96. }
  97. static struct irq_chip armctrl_chip = {
  98. .name = "ARMCTRL-level",
  99. .irq_mask = armctrl_mask_irq,
  100. .irq_unmask = armctrl_unmask_irq
  101. };
  102. static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
  103. const u32 *intspec, unsigned int intsize,
  104. unsigned long *out_hwirq, unsigned int *out_type)
  105. {
  106. if (WARN_ON(intsize != 2))
  107. return -EINVAL;
  108. if (WARN_ON(intspec[0] >= NR_BANKS))
  109. return -EINVAL;
  110. if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
  111. return -EINVAL;
  112. if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
  113. return -EINVAL;
  114. *out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
  115. *out_type = IRQ_TYPE_NONE;
  116. return 0;
  117. }
  118. static const struct irq_domain_ops armctrl_ops = {
  119. .xlate = armctrl_xlate
  120. };
  121. static int __init armctrl_of_init(struct device_node *node,
  122. struct device_node *parent,
  123. bool is_2836)
  124. {
  125. void __iomem *base;
  126. int irq, b, i;
  127. base = of_iomap(node, 0);
  128. if (!base)
  129. panic("%s: unable to map IC registers\n",
  130. node->full_name);
  131. intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
  132. &armctrl_ops, NULL);
  133. if (!intc.domain)
  134. panic("%s: unable to create IRQ domain\n", node->full_name);
  135. for (b = 0; b < NR_BANKS; b++) {
  136. intc.pending[b] = base + reg_pending[b];
  137. intc.enable[b] = base + reg_enable[b];
  138. intc.disable[b] = base + reg_disable[b];
  139. for (i = 0; i < bank_irqs[b]; i++) {
  140. irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
  141. BUG_ON(irq <= 0);
  142. irq_set_chip_and_handler(irq, &armctrl_chip,
  143. handle_level_irq);
  144. irq_set_probe(irq);
  145. }
  146. }
  147. if (is_2836) {
  148. int parent_irq = irq_of_parse_and_map(node, 0);
  149. if (!parent_irq) {
  150. panic("%s: unable to get parent interrupt.\n",
  151. node->full_name);
  152. }
  153. irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
  154. } else {
  155. set_handle_irq(bcm2835_handle_irq);
  156. }
  157. return 0;
  158. }
  159. static int __init bcm2835_armctrl_of_init(struct device_node *node,
  160. struct device_node *parent)
  161. {
  162. return armctrl_of_init(node, parent, false);
  163. }
  164. static int __init bcm2836_armctrl_of_init(struct device_node *node,
  165. struct device_node *parent)
  166. {
  167. return armctrl_of_init(node, parent, true);
  168. }
  169. /*
  170. * Handle each interrupt across the entire interrupt controller. This reads the
  171. * status register before handling each interrupt, which is necessary given that
  172. * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
  173. */
  174. static u32 armctrl_translate_bank(int bank)
  175. {
  176. u32 stat = readl_relaxed(intc.pending[bank]);
  177. return MAKE_HWIRQ(bank, ffs(stat) - 1);
  178. }
  179. static u32 armctrl_translate_shortcut(int bank, u32 stat)
  180. {
  181. return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
  182. }
  183. static u32 get_next_armctrl_hwirq(void)
  184. {
  185. u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
  186. if (stat == 0)
  187. return ~0;
  188. else if (stat & BANK0_HWIRQ_MASK)
  189. return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
  190. else if (stat & SHORTCUT1_MASK)
  191. return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
  192. else if (stat & SHORTCUT2_MASK)
  193. return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
  194. else if (stat & BANK1_HWIRQ)
  195. return armctrl_translate_bank(1);
  196. else if (stat & BANK2_HWIRQ)
  197. return armctrl_translate_bank(2);
  198. else
  199. BUG();
  200. }
  201. static void __exception_irq_entry bcm2835_handle_irq(
  202. struct pt_regs *regs)
  203. {
  204. u32 hwirq;
  205. while ((hwirq = get_next_armctrl_hwirq()) != ~0)
  206. handle_domain_irq(intc.domain, hwirq, regs);
  207. }
  208. static void bcm2836_chained_handle_irq(struct irq_desc *desc)
  209. {
  210. u32 hwirq;
  211. while ((hwirq = get_next_armctrl_hwirq()) != ~0)
  212. generic_handle_irq(irq_linear_revmap(intc.domain, hwirq));
  213. }
  214. IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
  215. bcm2835_armctrl_of_init);
  216. IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
  217. bcm2836_armctrl_of_init);