i40iw_puda.h 5.7 KB

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  1. /*******************************************************************************
  2. *
  3. * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenFabrics.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. *
  33. *******************************************************************************/
  34. #ifndef I40IW_PUDA_H
  35. #define I40IW_PUDA_H
  36. #define I40IW_IEQ_MPA_FRAMING 6
  37. struct i40iw_sc_dev;
  38. struct i40iw_sc_qp;
  39. struct i40iw_sc_cq;
  40. enum puda_resource_type {
  41. I40IW_PUDA_RSRC_TYPE_ILQ = 1,
  42. I40IW_PUDA_RSRC_TYPE_IEQ
  43. };
  44. enum puda_rsrc_complete {
  45. PUDA_CQ_CREATED = 1,
  46. PUDA_QP_CREATED,
  47. PUDA_TX_COMPLETE,
  48. PUDA_RX_COMPLETE,
  49. PUDA_HASH_CRC_COMPLETE
  50. };
  51. struct i40iw_puda_completion_info {
  52. struct i40iw_qp_uk *qp;
  53. u8 q_type;
  54. u8 vlan_valid;
  55. u8 l3proto;
  56. u8 l4proto;
  57. u16 payload_len;
  58. u32 compl_error; /* No_err=0, else major and minor err code */
  59. u32 qp_id;
  60. u32 wqe_idx;
  61. };
  62. struct i40iw_puda_send_info {
  63. u64 paddr; /* Physical address */
  64. u32 len;
  65. u8 tcplen;
  66. u8 maclen;
  67. bool ipv4;
  68. bool doloopback;
  69. void *scratch;
  70. };
  71. struct i40iw_puda_buf {
  72. struct list_head list; /* MUST be first entry */
  73. struct i40iw_dma_mem mem; /* DMA memory for the buffer */
  74. struct i40iw_puda_buf *next; /* for alloclist in rsrc struct */
  75. struct i40iw_virt_mem buf_mem; /* Buffer memory for this buffer */
  76. void *scratch;
  77. u8 *iph;
  78. u8 *tcph;
  79. u8 *data;
  80. u16 datalen;
  81. u16 vlan_id;
  82. u8 tcphlen; /* tcp length in bytes */
  83. u8 maclen; /* mac length in bytes */
  84. u32 totallen; /* machlen+iphlen+tcphlen+datalen */
  85. atomic_t refcount;
  86. u8 hdrlen;
  87. bool ipv4;
  88. u32 seqnum;
  89. };
  90. struct i40iw_puda_rsrc_info {
  91. enum puda_resource_type type; /* ILQ or IEQ */
  92. u32 count;
  93. u16 pd_id;
  94. u32 cq_id;
  95. u32 qp_id;
  96. u32 sq_size;
  97. u32 rq_size;
  98. u16 buf_size;
  99. u16 mss;
  100. u32 tx_buf_cnt; /* total bufs allocated will be rq_size + tx_buf_cnt */
  101. void (*receive)(struct i40iw_sc_dev *, struct i40iw_puda_buf *);
  102. void (*xmit_complete)(struct i40iw_sc_dev *, void *);
  103. };
  104. struct i40iw_puda_rsrc {
  105. struct i40iw_sc_cq cq;
  106. struct i40iw_sc_qp qp;
  107. struct i40iw_sc_pd sc_pd;
  108. struct i40iw_sc_dev *dev;
  109. struct i40iw_dma_mem cqmem;
  110. struct i40iw_dma_mem qpmem;
  111. struct i40iw_virt_mem ilq_mem;
  112. enum puda_rsrc_complete completion;
  113. enum puda_resource_type type;
  114. u16 buf_size; /*buffer must be max datalen + tcpip hdr + mac */
  115. u16 mss;
  116. u32 cq_id;
  117. u32 qp_id;
  118. u32 sq_size;
  119. u32 rq_size;
  120. u32 cq_size;
  121. struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
  122. u64 *rq_wrid_array;
  123. u32 compl_rxwqe_idx;
  124. u32 rx_wqe_idx;
  125. u32 rxq_invalid_cnt;
  126. u32 tx_wqe_avail_cnt;
  127. bool check_crc;
  128. struct shash_desc *hash_desc;
  129. struct list_head txpend;
  130. struct list_head bufpool; /* free buffers pool list for recv and xmit */
  131. u32 alloc_buf_count;
  132. u32 avail_buf_count; /* snapshot of currently available buffers */
  133. spinlock_t bufpool_lock;
  134. struct i40iw_puda_buf *alloclist;
  135. void (*receive)(struct i40iw_sc_dev *, struct i40iw_puda_buf *);
  136. void (*xmit_complete)(struct i40iw_sc_dev *, void *);
  137. /* puda stats */
  138. u64 stats_buf_alloc_fail;
  139. u64 stats_pkt_rcvd;
  140. u64 stats_pkt_sent;
  141. u64 stats_rcvd_pkt_err;
  142. u64 stats_sent_pkt_q;
  143. u64 stats_bad_qp_id;
  144. };
  145. struct i40iw_puda_buf *i40iw_puda_get_bufpool(struct i40iw_puda_rsrc *rsrc);
  146. void i40iw_puda_ret_bufpool(struct i40iw_puda_rsrc *rsrc,
  147. struct i40iw_puda_buf *buf);
  148. void i40iw_puda_send_buf(struct i40iw_puda_rsrc *rsrc,
  149. struct i40iw_puda_buf *buf);
  150. enum i40iw_status_code i40iw_puda_send(struct i40iw_sc_qp *qp,
  151. struct i40iw_puda_send_info *info);
  152. enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_dev *dev,
  153. struct i40iw_puda_rsrc_info *info);
  154. void i40iw_puda_dele_resources(struct i40iw_sc_dev *dev,
  155. enum puda_resource_type type,
  156. bool reset);
  157. enum i40iw_status_code i40iw_puda_poll_completion(struct i40iw_sc_dev *dev,
  158. struct i40iw_sc_cq *cq, u32 *compl_err);
  159. void i40iw_ieq_cleanup_qp(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
  160. struct i40iw_sc_qp *i40iw_ieq_get_qp(struct i40iw_sc_dev *dev,
  161. struct i40iw_puda_buf *buf);
  162. enum i40iw_status_code i40iw_puda_get_tcpip_info(struct i40iw_puda_completion_info *info,
  163. struct i40iw_puda_buf *buf);
  164. enum i40iw_status_code i40iw_ieq_check_mpacrc(struct shash_desc *desc,
  165. void *addr, u32 length, u32 value);
  166. enum i40iw_status_code i40iw_init_hash_desc(struct shash_desc **desc);
  167. void i40iw_ieq_mpa_crc_ae(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
  168. void i40iw_free_hash_desc(struct shash_desc *desc);
  169. void i40iw_ieq_update_tcpip_info(struct i40iw_puda_buf *buf, u16 length,
  170. u32 seqnum);
  171. #endif