radeon_vce.c 20 KB

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  1. /*
  2. * Copyright 2013 Advanced Micro Devices, Inc.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. * Authors: Christian König <christian.koenig@amd.com>
  26. */
  27. #include <linux/firmware.h>
  28. #include <linux/module.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm.h>
  31. #include "radeon.h"
  32. #include "radeon_asic.h"
  33. #include "sid.h"
  34. /* 1 second timeout */
  35. #define VCE_IDLE_TIMEOUT_MS 1000
  36. /* Firmware Names */
  37. #define FIRMWARE_TAHITI "/*(DEBLOBBED)*/"
  38. #define FIRMWARE_BONAIRE "/*(DEBLOBBED)*/"
  39. /*(DEBLOBBED)*/
  40. static void radeon_vce_idle_work_handler(struct work_struct *work);
  41. /**
  42. * radeon_vce_init - allocate memory, load vce firmware
  43. *
  44. * @rdev: radeon_device pointer
  45. *
  46. * First step to get VCE online, allocate memory and load the firmware
  47. */
  48. int radeon_vce_init(struct radeon_device *rdev)
  49. {
  50. static const char *fw_version = "[ATI LIB=VCEFW,";
  51. static const char *fb_version = "[ATI LIB=VCEFWSTATS,";
  52. unsigned long size;
  53. const char *fw_name, *c;
  54. uint8_t start, mid, end;
  55. int i, r;
  56. INIT_DELAYED_WORK(&rdev->vce.idle_work, radeon_vce_idle_work_handler);
  57. switch (rdev->family) {
  58. case CHIP_TAHITI:
  59. case CHIP_PITCAIRN:
  60. case CHIP_VERDE:
  61. case CHIP_OLAND:
  62. case CHIP_ARUBA:
  63. fw_name = FIRMWARE_TAHITI;
  64. break;
  65. case CHIP_BONAIRE:
  66. case CHIP_KAVERI:
  67. case CHIP_KABINI:
  68. case CHIP_HAWAII:
  69. case CHIP_MULLINS:
  70. fw_name = FIRMWARE_BONAIRE;
  71. break;
  72. default:
  73. return -EINVAL;
  74. }
  75. r = reject_firmware(&rdev->vce_fw, fw_name, rdev->dev);
  76. if (r) {
  77. dev_err(rdev->dev, "radeon_vce: Can't load firmware \"%s\"\n",
  78. fw_name);
  79. return r;
  80. }
  81. /* search for firmware version */
  82. size = rdev->vce_fw->size - strlen(fw_version) - 9;
  83. c = rdev->vce_fw->data;
  84. for (;size > 0; --size, ++c)
  85. if (strncmp(c, fw_version, strlen(fw_version)) == 0)
  86. break;
  87. if (size == 0)
  88. return -EINVAL;
  89. c += strlen(fw_version);
  90. if (sscanf(c, "%2hhd.%2hhd.%2hhd]", &start, &mid, &end) != 3)
  91. return -EINVAL;
  92. /* search for feedback version */
  93. size = rdev->vce_fw->size - strlen(fb_version) - 3;
  94. c = rdev->vce_fw->data;
  95. for (;size > 0; --size, ++c)
  96. if (strncmp(c, fb_version, strlen(fb_version)) == 0)
  97. break;
  98. if (size == 0)
  99. return -EINVAL;
  100. c += strlen(fb_version);
  101. if (sscanf(c, "%2u]", &rdev->vce.fb_version) != 1)
  102. return -EINVAL;
  103. DRM_INFO("Found VCE firmware/feedback version %hhd.%hhd.%hhd / %d!\n",
  104. start, mid, end, rdev->vce.fb_version);
  105. rdev->vce.fw_version = (start << 24) | (mid << 16) | (end << 8);
  106. /* we can only work with this fw version for now */
  107. if ((rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8))) &&
  108. (rdev->vce.fw_version != ((50 << 24) | (0 << 16) | (1 << 8))) &&
  109. (rdev->vce.fw_version != ((50 << 24) | (1 << 16) | (2 << 8))))
  110. return -EINVAL;
  111. /* allocate firmware, stack and heap BO */
  112. if (rdev->family < CHIP_BONAIRE)
  113. size = vce_v1_0_bo_size(rdev);
  114. else
  115. size = vce_v2_0_bo_size(rdev);
  116. r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
  117. RADEON_GEM_DOMAIN_VRAM, 0, NULL, NULL,
  118. &rdev->vce.vcpu_bo);
  119. if (r) {
  120. dev_err(rdev->dev, "(%d) failed to allocate VCE bo\n", r);
  121. return r;
  122. }
  123. r = radeon_bo_reserve(rdev->vce.vcpu_bo, false);
  124. if (r) {
  125. radeon_bo_unref(&rdev->vce.vcpu_bo);
  126. dev_err(rdev->dev, "(%d) failed to reserve VCE bo\n", r);
  127. return r;
  128. }
  129. r = radeon_bo_pin(rdev->vce.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
  130. &rdev->vce.gpu_addr);
  131. radeon_bo_unreserve(rdev->vce.vcpu_bo);
  132. if (r) {
  133. radeon_bo_unref(&rdev->vce.vcpu_bo);
  134. dev_err(rdev->dev, "(%d) VCE bo pin failed\n", r);
  135. return r;
  136. }
  137. for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
  138. atomic_set(&rdev->vce.handles[i], 0);
  139. rdev->vce.filp[i] = NULL;
  140. }
  141. return 0;
  142. }
  143. /**
  144. * radeon_vce_fini - free memory
  145. *
  146. * @rdev: radeon_device pointer
  147. *
  148. * Last step on VCE teardown, free firmware memory
  149. */
  150. void radeon_vce_fini(struct radeon_device *rdev)
  151. {
  152. if (rdev->vce.vcpu_bo == NULL)
  153. return;
  154. radeon_bo_unref(&rdev->vce.vcpu_bo);
  155. release_firmware(rdev->vce_fw);
  156. }
  157. /**
  158. * radeon_vce_suspend - unpin VCE fw memory
  159. *
  160. * @rdev: radeon_device pointer
  161. *
  162. */
  163. int radeon_vce_suspend(struct radeon_device *rdev)
  164. {
  165. int i;
  166. if (rdev->vce.vcpu_bo == NULL)
  167. return 0;
  168. for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i)
  169. if (atomic_read(&rdev->vce.handles[i]))
  170. break;
  171. if (i == RADEON_MAX_VCE_HANDLES)
  172. return 0;
  173. /* TODO: suspending running encoding sessions isn't supported */
  174. return -EINVAL;
  175. }
  176. /**
  177. * radeon_vce_resume - pin VCE fw memory
  178. *
  179. * @rdev: radeon_device pointer
  180. *
  181. */
  182. int radeon_vce_resume(struct radeon_device *rdev)
  183. {
  184. void *cpu_addr;
  185. int r;
  186. if (rdev->vce.vcpu_bo == NULL)
  187. return -EINVAL;
  188. r = radeon_bo_reserve(rdev->vce.vcpu_bo, false);
  189. if (r) {
  190. dev_err(rdev->dev, "(%d) failed to reserve VCE bo\n", r);
  191. return r;
  192. }
  193. r = radeon_bo_kmap(rdev->vce.vcpu_bo, &cpu_addr);
  194. if (r) {
  195. radeon_bo_unreserve(rdev->vce.vcpu_bo);
  196. dev_err(rdev->dev, "(%d) VCE map failed\n", r);
  197. return r;
  198. }
  199. memset(cpu_addr, 0, radeon_bo_size(rdev->vce.vcpu_bo));
  200. if (rdev->family < CHIP_BONAIRE)
  201. r = vce_v1_0_load_fw(rdev, cpu_addr);
  202. else
  203. memcpy(cpu_addr, rdev->vce_fw->data, rdev->vce_fw->size);
  204. radeon_bo_kunmap(rdev->vce.vcpu_bo);
  205. radeon_bo_unreserve(rdev->vce.vcpu_bo);
  206. return r;
  207. }
  208. /**
  209. * radeon_vce_idle_work_handler - power off VCE
  210. *
  211. * @work: pointer to work structure
  212. *
  213. * power of VCE when it's not used any more
  214. */
  215. static void radeon_vce_idle_work_handler(struct work_struct *work)
  216. {
  217. struct radeon_device *rdev =
  218. container_of(work, struct radeon_device, vce.idle_work.work);
  219. if ((radeon_fence_count_emitted(rdev, TN_RING_TYPE_VCE1_INDEX) == 0) &&
  220. (radeon_fence_count_emitted(rdev, TN_RING_TYPE_VCE2_INDEX) == 0)) {
  221. if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
  222. radeon_dpm_enable_vce(rdev, false);
  223. } else {
  224. radeon_set_vce_clocks(rdev, 0, 0);
  225. }
  226. } else {
  227. schedule_delayed_work(&rdev->vce.idle_work,
  228. msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
  229. }
  230. }
  231. /**
  232. * radeon_vce_note_usage - power up VCE
  233. *
  234. * @rdev: radeon_device pointer
  235. *
  236. * Make sure VCE is powerd up when we want to use it
  237. */
  238. void radeon_vce_note_usage(struct radeon_device *rdev)
  239. {
  240. bool streams_changed = false;
  241. bool set_clocks = !cancel_delayed_work_sync(&rdev->vce.idle_work);
  242. set_clocks &= schedule_delayed_work(&rdev->vce.idle_work,
  243. msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
  244. if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
  245. /* XXX figure out if the streams changed */
  246. streams_changed = false;
  247. }
  248. if (set_clocks || streams_changed) {
  249. if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
  250. radeon_dpm_enable_vce(rdev, true);
  251. } else {
  252. radeon_set_vce_clocks(rdev, 53300, 40000);
  253. }
  254. }
  255. }
  256. /**
  257. * radeon_vce_free_handles - free still open VCE handles
  258. *
  259. * @rdev: radeon_device pointer
  260. * @filp: drm file pointer
  261. *
  262. * Close all VCE handles still open by this file pointer
  263. */
  264. void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp)
  265. {
  266. int i, r;
  267. for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
  268. uint32_t handle = atomic_read(&rdev->vce.handles[i]);
  269. if (!handle || rdev->vce.filp[i] != filp)
  270. continue;
  271. radeon_vce_note_usage(rdev);
  272. r = radeon_vce_get_destroy_msg(rdev, TN_RING_TYPE_VCE1_INDEX,
  273. handle, NULL);
  274. if (r)
  275. DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
  276. rdev->vce.filp[i] = NULL;
  277. atomic_set(&rdev->vce.handles[i], 0);
  278. }
  279. }
  280. /**
  281. * radeon_vce_get_create_msg - generate a VCE create msg
  282. *
  283. * @rdev: radeon_device pointer
  284. * @ring: ring we should submit the msg to
  285. * @handle: VCE session handle to use
  286. * @fence: optional fence to return
  287. *
  288. * Open up a stream for HW test
  289. */
  290. int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
  291. uint32_t handle, struct radeon_fence **fence)
  292. {
  293. const unsigned ib_size_dw = 1024;
  294. struct radeon_ib ib;
  295. uint64_t dummy;
  296. int i, r;
  297. r = radeon_ib_get(rdev, ring, &ib, NULL, ib_size_dw * 4);
  298. if (r) {
  299. DRM_ERROR("radeon: failed to get ib (%d).\n", r);
  300. return r;
  301. }
  302. dummy = ib.gpu_addr + 1024;
  303. /* stitch together an VCE create msg */
  304. ib.length_dw = 0;
  305. ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c); /* len */
  306. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001); /* session cmd */
  307. ib.ptr[ib.length_dw++] = cpu_to_le32(handle);
  308. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000030); /* len */
  309. ib.ptr[ib.length_dw++] = cpu_to_le32(0x01000001); /* create cmd */
  310. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000000);
  311. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000042);
  312. ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000a);
  313. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
  314. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000080);
  315. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000060);
  316. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000100);
  317. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000100);
  318. ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c);
  319. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000000);
  320. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000014); /* len */
  321. ib.ptr[ib.length_dw++] = cpu_to_le32(0x05000005); /* feedback buffer */
  322. ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));
  323. ib.ptr[ib.length_dw++] = cpu_to_le32(dummy);
  324. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
  325. for (i = ib.length_dw; i < ib_size_dw; ++i)
  326. ib.ptr[i] = cpu_to_le32(0x0);
  327. r = radeon_ib_schedule(rdev, &ib, NULL, false);
  328. if (r) {
  329. DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
  330. }
  331. if (fence)
  332. *fence = radeon_fence_ref(ib.fence);
  333. radeon_ib_free(rdev, &ib);
  334. return r;
  335. }
  336. /**
  337. * radeon_vce_get_destroy_msg - generate a VCE destroy msg
  338. *
  339. * @rdev: radeon_device pointer
  340. * @ring: ring we should submit the msg to
  341. * @handle: VCE session handle to use
  342. * @fence: optional fence to return
  343. *
  344. * Close up a stream for HW test or if userspace failed to do so
  345. */
  346. int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
  347. uint32_t handle, struct radeon_fence **fence)
  348. {
  349. const unsigned ib_size_dw = 1024;
  350. struct radeon_ib ib;
  351. uint64_t dummy;
  352. int i, r;
  353. r = radeon_ib_get(rdev, ring, &ib, NULL, ib_size_dw * 4);
  354. if (r) {
  355. DRM_ERROR("radeon: failed to get ib (%d).\n", r);
  356. return r;
  357. }
  358. dummy = ib.gpu_addr + 1024;
  359. /* stitch together an VCE destroy msg */
  360. ib.length_dw = 0;
  361. ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c); /* len */
  362. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001); /* session cmd */
  363. ib.ptr[ib.length_dw++] = cpu_to_le32(handle);
  364. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000014); /* len */
  365. ib.ptr[ib.length_dw++] = cpu_to_le32(0x05000005); /* feedback buffer */
  366. ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));
  367. ib.ptr[ib.length_dw++] = cpu_to_le32(dummy);
  368. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
  369. ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000008); /* len */
  370. ib.ptr[ib.length_dw++] = cpu_to_le32(0x02000001); /* destroy cmd */
  371. for (i = ib.length_dw; i < ib_size_dw; ++i)
  372. ib.ptr[i] = cpu_to_le32(0x0);
  373. r = radeon_ib_schedule(rdev, &ib, NULL, false);
  374. if (r) {
  375. DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
  376. }
  377. if (fence)
  378. *fence = radeon_fence_ref(ib.fence);
  379. radeon_ib_free(rdev, &ib);
  380. return r;
  381. }
  382. /**
  383. * radeon_vce_cs_reloc - command submission relocation
  384. *
  385. * @p: parser context
  386. * @lo: address of lower dword
  387. * @hi: address of higher dword
  388. * @size: size of checker for relocation buffer
  389. *
  390. * Patch relocation inside command stream with real buffer address
  391. */
  392. int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi,
  393. unsigned size)
  394. {
  395. struct radeon_cs_chunk *relocs_chunk;
  396. struct radeon_bo_list *reloc;
  397. uint64_t start, end, offset;
  398. unsigned idx;
  399. relocs_chunk = p->chunk_relocs;
  400. offset = radeon_get_ib_value(p, lo);
  401. idx = radeon_get_ib_value(p, hi);
  402. if (idx >= relocs_chunk->length_dw) {
  403. DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
  404. idx, relocs_chunk->length_dw);
  405. return -EINVAL;
  406. }
  407. reloc = &p->relocs[(idx / 4)];
  408. start = reloc->gpu_offset;
  409. end = start + radeon_bo_size(reloc->robj);
  410. start += offset;
  411. p->ib.ptr[lo] = start & 0xFFFFFFFF;
  412. p->ib.ptr[hi] = start >> 32;
  413. if (end <= start) {
  414. DRM_ERROR("invalid reloc offset %llX!\n", offset);
  415. return -EINVAL;
  416. }
  417. if ((end - start) < size) {
  418. DRM_ERROR("buffer to small (%d / %d)!\n",
  419. (unsigned)(end - start), size);
  420. return -EINVAL;
  421. }
  422. return 0;
  423. }
  424. /**
  425. * radeon_vce_validate_handle - validate stream handle
  426. *
  427. * @p: parser context
  428. * @handle: handle to validate
  429. * @allocated: allocated a new handle?
  430. *
  431. * Validates the handle and return the found session index or -EINVAL
  432. * we we don't have another free session index.
  433. */
  434. static int radeon_vce_validate_handle(struct radeon_cs_parser *p,
  435. uint32_t handle, bool *allocated)
  436. {
  437. unsigned i;
  438. *allocated = false;
  439. /* validate the handle */
  440. for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
  441. if (atomic_read(&p->rdev->vce.handles[i]) == handle) {
  442. if (p->rdev->vce.filp[i] != p->filp) {
  443. DRM_ERROR("VCE handle collision detected!\n");
  444. return -EINVAL;
  445. }
  446. return i;
  447. }
  448. }
  449. /* handle not found try to alloc a new one */
  450. for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
  451. if (!atomic_cmpxchg(&p->rdev->vce.handles[i], 0, handle)) {
  452. p->rdev->vce.filp[i] = p->filp;
  453. p->rdev->vce.img_size[i] = 0;
  454. *allocated = true;
  455. return i;
  456. }
  457. }
  458. DRM_ERROR("No more free VCE handles!\n");
  459. return -EINVAL;
  460. }
  461. /**
  462. * radeon_vce_cs_parse - parse and validate the command stream
  463. *
  464. * @p: parser context
  465. *
  466. */
  467. int radeon_vce_cs_parse(struct radeon_cs_parser *p)
  468. {
  469. int session_idx = -1;
  470. bool destroyed = false, created = false, allocated = false;
  471. uint32_t tmp, handle = 0;
  472. uint32_t *size = &tmp;
  473. int i, r = 0;
  474. while (p->idx < p->chunk_ib->length_dw) {
  475. uint32_t len = radeon_get_ib_value(p, p->idx);
  476. uint32_t cmd = radeon_get_ib_value(p, p->idx + 1);
  477. if ((len < 8) || (len & 3)) {
  478. DRM_ERROR("invalid VCE command length (%d)!\n", len);
  479. r = -EINVAL;
  480. goto out;
  481. }
  482. if (destroyed) {
  483. DRM_ERROR("No other command allowed after destroy!\n");
  484. r = -EINVAL;
  485. goto out;
  486. }
  487. switch (cmd) {
  488. case 0x00000001: // session
  489. handle = radeon_get_ib_value(p, p->idx + 2);
  490. session_idx = radeon_vce_validate_handle(p, handle,
  491. &allocated);
  492. if (session_idx < 0)
  493. return session_idx;
  494. size = &p->rdev->vce.img_size[session_idx];
  495. break;
  496. case 0x00000002: // task info
  497. break;
  498. case 0x01000001: // create
  499. created = true;
  500. if (!allocated) {
  501. DRM_ERROR("Handle already in use!\n");
  502. r = -EINVAL;
  503. goto out;
  504. }
  505. *size = radeon_get_ib_value(p, p->idx + 8) *
  506. radeon_get_ib_value(p, p->idx + 10) *
  507. 8 * 3 / 2;
  508. break;
  509. case 0x04000001: // config extension
  510. case 0x04000002: // pic control
  511. case 0x04000005: // rate control
  512. case 0x04000007: // motion estimation
  513. case 0x04000008: // rdo
  514. case 0x04000009: // vui
  515. break;
  516. case 0x03000001: // encode
  517. r = radeon_vce_cs_reloc(p, p->idx + 10, p->idx + 9,
  518. *size);
  519. if (r)
  520. goto out;
  521. r = radeon_vce_cs_reloc(p, p->idx + 12, p->idx + 11,
  522. *size / 3);
  523. if (r)
  524. goto out;
  525. break;
  526. case 0x02000001: // destroy
  527. destroyed = true;
  528. break;
  529. case 0x05000001: // context buffer
  530. r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
  531. *size * 2);
  532. if (r)
  533. goto out;
  534. break;
  535. case 0x05000004: // video bitstream buffer
  536. tmp = radeon_get_ib_value(p, p->idx + 4);
  537. r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
  538. tmp);
  539. if (r)
  540. goto out;
  541. break;
  542. case 0x05000005: // feedback buffer
  543. r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
  544. 4096);
  545. if (r)
  546. goto out;
  547. break;
  548. default:
  549. DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
  550. r = -EINVAL;
  551. goto out;
  552. }
  553. if (session_idx == -1) {
  554. DRM_ERROR("no session command at start of IB\n");
  555. r = -EINVAL;
  556. goto out;
  557. }
  558. p->idx += len / 4;
  559. }
  560. if (allocated && !created) {
  561. DRM_ERROR("New session without create command!\n");
  562. r = -ENOENT;
  563. }
  564. out:
  565. if ((!r && destroyed) || (r && allocated)) {
  566. /*
  567. * IB contains a destroy msg or we have allocated an
  568. * handle and got an error, anyway free the handle
  569. */
  570. for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i)
  571. atomic_cmpxchg(&p->rdev->vce.handles[i], handle, 0);
  572. }
  573. return r;
  574. }
  575. /**
  576. * radeon_vce_semaphore_emit - emit a semaphore command
  577. *
  578. * @rdev: radeon_device pointer
  579. * @ring: engine to use
  580. * @semaphore: address of semaphore
  581. * @emit_wait: true=emit wait, false=emit signal
  582. *
  583. */
  584. bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
  585. struct radeon_ring *ring,
  586. struct radeon_semaphore *semaphore,
  587. bool emit_wait)
  588. {
  589. uint64_t addr = semaphore->gpu_addr;
  590. radeon_ring_write(ring, cpu_to_le32(VCE_CMD_SEMAPHORE));
  591. radeon_ring_write(ring, cpu_to_le32((addr >> 3) & 0x000FFFFF));
  592. radeon_ring_write(ring, cpu_to_le32((addr >> 23) & 0x000FFFFF));
  593. radeon_ring_write(ring, cpu_to_le32(0x01003000 | (emit_wait ? 1 : 0)));
  594. if (!emit_wait)
  595. radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
  596. return true;
  597. }
  598. /**
  599. * radeon_vce_ib_execute - execute indirect buffer
  600. *
  601. * @rdev: radeon_device pointer
  602. * @ib: the IB to execute
  603. *
  604. */
  605. void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
  606. {
  607. struct radeon_ring *ring = &rdev->ring[ib->ring];
  608. radeon_ring_write(ring, cpu_to_le32(VCE_CMD_IB));
  609. radeon_ring_write(ring, cpu_to_le32(ib->gpu_addr));
  610. radeon_ring_write(ring, cpu_to_le32(upper_32_bits(ib->gpu_addr)));
  611. radeon_ring_write(ring, cpu_to_le32(ib->length_dw));
  612. }
  613. /**
  614. * radeon_vce_fence_emit - add a fence command to the ring
  615. *
  616. * @rdev: radeon_device pointer
  617. * @fence: the fence
  618. *
  619. */
  620. void radeon_vce_fence_emit(struct radeon_device *rdev,
  621. struct radeon_fence *fence)
  622. {
  623. struct radeon_ring *ring = &rdev->ring[fence->ring];
  624. uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
  625. radeon_ring_write(ring, cpu_to_le32(VCE_CMD_FENCE));
  626. radeon_ring_write(ring, cpu_to_le32(addr));
  627. radeon_ring_write(ring, cpu_to_le32(upper_32_bits(addr)));
  628. radeon_ring_write(ring, cpu_to_le32(fence->seq));
  629. radeon_ring_write(ring, cpu_to_le32(VCE_CMD_TRAP));
  630. radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
  631. }
  632. /**
  633. * radeon_vce_ring_test - test if VCE ring is working
  634. *
  635. * @rdev: radeon_device pointer
  636. * @ring: the engine to test on
  637. *
  638. */
  639. int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
  640. {
  641. uint32_t rptr = vce_v1_0_get_rptr(rdev, ring);
  642. unsigned i;
  643. int r;
  644. r = radeon_ring_lock(rdev, ring, 16);
  645. if (r) {
  646. DRM_ERROR("radeon: vce failed to lock ring %d (%d).\n",
  647. ring->idx, r);
  648. return r;
  649. }
  650. radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
  651. radeon_ring_unlock_commit(rdev, ring, false);
  652. for (i = 0; i < rdev->usec_timeout; i++) {
  653. if (vce_v1_0_get_rptr(rdev, ring) != rptr)
  654. break;
  655. DRM_UDELAY(1);
  656. }
  657. if (i < rdev->usec_timeout) {
  658. DRM_INFO("ring test on %d succeeded in %d usecs\n",
  659. ring->idx, i);
  660. } else {
  661. DRM_ERROR("radeon: ring %d test failed\n",
  662. ring->idx);
  663. r = -ETIMEDOUT;
  664. }
  665. return r;
  666. }
  667. /**
  668. * radeon_vce_ib_test - test if VCE IBs are working
  669. *
  670. * @rdev: radeon_device pointer
  671. * @ring: the engine to test on
  672. *
  673. */
  674. int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
  675. {
  676. struct radeon_fence *fence = NULL;
  677. int r;
  678. r = radeon_vce_get_create_msg(rdev, ring->idx, 1, NULL);
  679. if (r) {
  680. DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
  681. goto error;
  682. }
  683. r = radeon_vce_get_destroy_msg(rdev, ring->idx, 1, &fence);
  684. if (r) {
  685. DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
  686. goto error;
  687. }
  688. r = radeon_fence_wait_timeout(fence, false, usecs_to_jiffies(
  689. RADEON_USEC_IB_TEST_TIMEOUT));
  690. if (r < 0) {
  691. DRM_ERROR("radeon: fence wait failed (%d).\n", r);
  692. } else if (r == 0) {
  693. DRM_ERROR("radeon: fence wait timed out.\n");
  694. r = -ETIMEDOUT;
  695. } else {
  696. DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
  697. r = 0;
  698. }
  699. error:
  700. radeon_fence_unref(&fence);
  701. return r;
  702. }