mtk_dpi.c 20 KB

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  1. /*
  2. * Copyright (c) 2014 MediaTek Inc.
  3. * Author: Jie Qiu <jie.qiu@mediatek.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <drm/drmP.h>
  15. #include <drm/drm_crtc.h>
  16. #include <drm/drm_crtc_helper.h>
  17. #include <linux/kernel.h>
  18. #include <linux/component.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/of.h>
  21. #include <linux/of_graph.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/types.h>
  24. #include <linux/clk.h>
  25. #include "mtk_dpi_regs.h"
  26. #include "mtk_drm_ddp_comp.h"
  27. enum mtk_dpi_out_bit_num {
  28. MTK_DPI_OUT_BIT_NUM_8BITS,
  29. MTK_DPI_OUT_BIT_NUM_10BITS,
  30. MTK_DPI_OUT_BIT_NUM_12BITS,
  31. MTK_DPI_OUT_BIT_NUM_16BITS
  32. };
  33. enum mtk_dpi_out_yc_map {
  34. MTK_DPI_OUT_YC_MAP_RGB,
  35. MTK_DPI_OUT_YC_MAP_CYCY,
  36. MTK_DPI_OUT_YC_MAP_YCYC,
  37. MTK_DPI_OUT_YC_MAP_CY,
  38. MTK_DPI_OUT_YC_MAP_YC
  39. };
  40. enum mtk_dpi_out_channel_swap {
  41. MTK_DPI_OUT_CHANNEL_SWAP_RGB,
  42. MTK_DPI_OUT_CHANNEL_SWAP_GBR,
  43. MTK_DPI_OUT_CHANNEL_SWAP_BRG,
  44. MTK_DPI_OUT_CHANNEL_SWAP_RBG,
  45. MTK_DPI_OUT_CHANNEL_SWAP_GRB,
  46. MTK_DPI_OUT_CHANNEL_SWAP_BGR
  47. };
  48. enum mtk_dpi_out_color_format {
  49. MTK_DPI_COLOR_FORMAT_RGB,
  50. MTK_DPI_COLOR_FORMAT_RGB_FULL,
  51. MTK_DPI_COLOR_FORMAT_YCBCR_444,
  52. MTK_DPI_COLOR_FORMAT_YCBCR_422,
  53. MTK_DPI_COLOR_FORMAT_XV_YCC,
  54. MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL,
  55. MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL
  56. };
  57. struct mtk_dpi {
  58. struct mtk_ddp_comp ddp_comp;
  59. struct drm_encoder encoder;
  60. void __iomem *regs;
  61. struct device *dev;
  62. struct clk *engine_clk;
  63. struct clk *pixel_clk;
  64. struct clk *tvd_clk;
  65. int irq;
  66. struct drm_display_mode mode;
  67. enum mtk_dpi_out_color_format color_format;
  68. enum mtk_dpi_out_yc_map yc_map;
  69. enum mtk_dpi_out_bit_num bit_num;
  70. enum mtk_dpi_out_channel_swap channel_swap;
  71. bool power_sta;
  72. u8 power_ctl;
  73. };
  74. static inline struct mtk_dpi *mtk_dpi_from_encoder(struct drm_encoder *e)
  75. {
  76. return container_of(e, struct mtk_dpi, encoder);
  77. }
  78. enum mtk_dpi_polarity {
  79. MTK_DPI_POLARITY_RISING,
  80. MTK_DPI_POLARITY_FALLING,
  81. };
  82. enum mtk_dpi_power_ctl {
  83. DPI_POWER_START = BIT(0),
  84. DPI_POWER_ENABLE = BIT(1),
  85. };
  86. struct mtk_dpi_polarities {
  87. enum mtk_dpi_polarity de_pol;
  88. enum mtk_dpi_polarity ck_pol;
  89. enum mtk_dpi_polarity hsync_pol;
  90. enum mtk_dpi_polarity vsync_pol;
  91. };
  92. struct mtk_dpi_sync_param {
  93. u32 sync_width;
  94. u32 front_porch;
  95. u32 back_porch;
  96. bool shift_half_line;
  97. };
  98. struct mtk_dpi_yc_limit {
  99. u16 y_top;
  100. u16 y_bottom;
  101. u16 c_top;
  102. u16 c_bottom;
  103. };
  104. static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
  105. {
  106. u32 tmp = readl(dpi->regs + offset) & ~mask;
  107. tmp |= (val & mask);
  108. writel(tmp, dpi->regs + offset);
  109. }
  110. static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
  111. {
  112. mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
  113. }
  114. static void mtk_dpi_enable(struct mtk_dpi *dpi)
  115. {
  116. mtk_dpi_mask(dpi, DPI_EN, EN, EN);
  117. }
  118. static void mtk_dpi_disable(struct mtk_dpi *dpi)
  119. {
  120. mtk_dpi_mask(dpi, DPI_EN, 0, EN);
  121. }
  122. static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
  123. struct mtk_dpi_sync_param *sync)
  124. {
  125. mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH,
  126. sync->sync_width << HPW, HPW_MASK);
  127. mtk_dpi_mask(dpi, DPI_TGEN_HPORCH,
  128. sync->back_porch << HBP, HBP_MASK);
  129. mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
  130. HFP_MASK);
  131. }
  132. static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
  133. struct mtk_dpi_sync_param *sync,
  134. u32 width_addr, u32 porch_addr)
  135. {
  136. mtk_dpi_mask(dpi, width_addr,
  137. sync->sync_width << VSYNC_WIDTH_SHIFT,
  138. VSYNC_WIDTH_MASK);
  139. mtk_dpi_mask(dpi, width_addr,
  140. sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
  141. VSYNC_HALF_LINE_MASK);
  142. mtk_dpi_mask(dpi, porch_addr,
  143. sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
  144. VSYNC_BACK_PORCH_MASK);
  145. mtk_dpi_mask(dpi, porch_addr,
  146. sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
  147. VSYNC_FRONT_PORCH_MASK);
  148. }
  149. static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi,
  150. struct mtk_dpi_sync_param *sync)
  151. {
  152. mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH);
  153. }
  154. static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi,
  155. struct mtk_dpi_sync_param *sync)
  156. {
  157. mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN,
  158. DPI_TGEN_VPORCH_LEVEN);
  159. }
  160. static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi,
  161. struct mtk_dpi_sync_param *sync)
  162. {
  163. mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD,
  164. DPI_TGEN_VPORCH_RODD);
  165. }
  166. static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi,
  167. struct mtk_dpi_sync_param *sync)
  168. {
  169. mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN,
  170. DPI_TGEN_VPORCH_REVEN);
  171. }
  172. static void mtk_dpi_config_pol(struct mtk_dpi *dpi,
  173. struct mtk_dpi_polarities *dpi_pol)
  174. {
  175. unsigned int pol;
  176. pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL) |
  177. (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL) |
  178. (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) |
  179. (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL);
  180. mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol,
  181. CK_POL | DE_POL | HSYNC_POL | VSYNC_POL);
  182. }
  183. static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d)
  184. {
  185. mtk_dpi_mask(dpi, DPI_CON, en_3d ? TDFP_EN : 0, TDFP_EN);
  186. }
  187. static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter)
  188. {
  189. mtk_dpi_mask(dpi, DPI_CON, inter ? INTL_EN : 0, INTL_EN);
  190. }
  191. static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height)
  192. {
  193. mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK);
  194. mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK);
  195. }
  196. static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi,
  197. struct mtk_dpi_yc_limit *limit)
  198. {
  199. mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT,
  200. Y_LIMINT_BOT_MASK);
  201. mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP,
  202. Y_LIMINT_TOP_MASK);
  203. mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT,
  204. C_LIMIT_BOT_MASK);
  205. mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP,
  206. C_LIMIT_TOP_MASK);
  207. }
  208. static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi,
  209. enum mtk_dpi_out_bit_num num)
  210. {
  211. u32 val;
  212. switch (num) {
  213. case MTK_DPI_OUT_BIT_NUM_8BITS:
  214. val = OUT_BIT_8;
  215. break;
  216. case MTK_DPI_OUT_BIT_NUM_10BITS:
  217. val = OUT_BIT_10;
  218. break;
  219. case MTK_DPI_OUT_BIT_NUM_12BITS:
  220. val = OUT_BIT_12;
  221. break;
  222. case MTK_DPI_OUT_BIT_NUM_16BITS:
  223. val = OUT_BIT_16;
  224. break;
  225. default:
  226. val = OUT_BIT_8;
  227. break;
  228. }
  229. mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT,
  230. OUT_BIT_MASK);
  231. }
  232. static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi,
  233. enum mtk_dpi_out_yc_map map)
  234. {
  235. u32 val;
  236. switch (map) {
  237. case MTK_DPI_OUT_YC_MAP_RGB:
  238. val = YC_MAP_RGB;
  239. break;
  240. case MTK_DPI_OUT_YC_MAP_CYCY:
  241. val = YC_MAP_CYCY;
  242. break;
  243. case MTK_DPI_OUT_YC_MAP_YCYC:
  244. val = YC_MAP_YCYC;
  245. break;
  246. case MTK_DPI_OUT_YC_MAP_CY:
  247. val = YC_MAP_CY;
  248. break;
  249. case MTK_DPI_OUT_YC_MAP_YC:
  250. val = YC_MAP_YC;
  251. break;
  252. default:
  253. val = YC_MAP_RGB;
  254. break;
  255. }
  256. mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK);
  257. }
  258. static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi,
  259. enum mtk_dpi_out_channel_swap swap)
  260. {
  261. u32 val;
  262. switch (swap) {
  263. case MTK_DPI_OUT_CHANNEL_SWAP_RGB:
  264. val = SWAP_RGB;
  265. break;
  266. case MTK_DPI_OUT_CHANNEL_SWAP_GBR:
  267. val = SWAP_GBR;
  268. break;
  269. case MTK_DPI_OUT_CHANNEL_SWAP_BRG:
  270. val = SWAP_BRG;
  271. break;
  272. case MTK_DPI_OUT_CHANNEL_SWAP_RBG:
  273. val = SWAP_RBG;
  274. break;
  275. case MTK_DPI_OUT_CHANNEL_SWAP_GRB:
  276. val = SWAP_GRB;
  277. break;
  278. case MTK_DPI_OUT_CHANNEL_SWAP_BGR:
  279. val = SWAP_BGR;
  280. break;
  281. default:
  282. val = SWAP_RGB;
  283. break;
  284. }
  285. mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK);
  286. }
  287. static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable)
  288. {
  289. mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN);
  290. }
  291. static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable)
  292. {
  293. mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE);
  294. }
  295. static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
  296. {
  297. mtk_dpi_mask(dpi, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP);
  298. }
  299. static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
  300. {
  301. mtk_dpi_mask(dpi, DPI_H_FRE_CON, H_FRE_2N, H_FRE_2N);
  302. }
  303. static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
  304. enum mtk_dpi_out_color_format format)
  305. {
  306. if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_444) ||
  307. (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) {
  308. mtk_dpi_config_yuv422_enable(dpi, false);
  309. mtk_dpi_config_csc_enable(dpi, true);
  310. mtk_dpi_config_swap_input(dpi, false);
  311. mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR);
  312. } else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) ||
  313. (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) {
  314. mtk_dpi_config_yuv422_enable(dpi, true);
  315. mtk_dpi_config_csc_enable(dpi, true);
  316. mtk_dpi_config_swap_input(dpi, true);
  317. mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
  318. } else {
  319. mtk_dpi_config_yuv422_enable(dpi, false);
  320. mtk_dpi_config_csc_enable(dpi, false);
  321. mtk_dpi_config_swap_input(dpi, false);
  322. mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
  323. }
  324. }
  325. static void mtk_dpi_power_off(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
  326. {
  327. dpi->power_ctl &= ~pctl;
  328. if ((dpi->power_ctl & DPI_POWER_START) ||
  329. (dpi->power_ctl & DPI_POWER_ENABLE))
  330. return;
  331. if (!dpi->power_sta)
  332. return;
  333. mtk_dpi_disable(dpi);
  334. clk_disable_unprepare(dpi->pixel_clk);
  335. clk_disable_unprepare(dpi->engine_clk);
  336. dpi->power_sta = false;
  337. }
  338. static int mtk_dpi_power_on(struct mtk_dpi *dpi, enum mtk_dpi_power_ctl pctl)
  339. {
  340. int ret;
  341. dpi->power_ctl |= pctl;
  342. if (!(dpi->power_ctl & DPI_POWER_START) &&
  343. !(dpi->power_ctl & DPI_POWER_ENABLE))
  344. return 0;
  345. if (dpi->power_sta)
  346. return 0;
  347. ret = clk_prepare_enable(dpi->engine_clk);
  348. if (ret) {
  349. dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret);
  350. goto err_eng;
  351. }
  352. ret = clk_prepare_enable(dpi->pixel_clk);
  353. if (ret) {
  354. dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
  355. goto err_pixel;
  356. }
  357. mtk_dpi_enable(dpi);
  358. dpi->power_sta = true;
  359. return 0;
  360. err_pixel:
  361. clk_disable_unprepare(dpi->engine_clk);
  362. err_eng:
  363. dpi->power_ctl &= ~pctl;
  364. return ret;
  365. }
  366. static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
  367. struct drm_display_mode *mode)
  368. {
  369. struct mtk_dpi_yc_limit limit;
  370. struct mtk_dpi_polarities dpi_pol;
  371. struct mtk_dpi_sync_param hsync;
  372. struct mtk_dpi_sync_param vsync_lodd = { 0 };
  373. struct mtk_dpi_sync_param vsync_leven = { 0 };
  374. struct mtk_dpi_sync_param vsync_rodd = { 0 };
  375. struct mtk_dpi_sync_param vsync_reven = { 0 };
  376. unsigned long pix_rate;
  377. unsigned long pll_rate;
  378. unsigned int factor;
  379. /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
  380. pix_rate = 1000UL * mode->clock;
  381. if (mode->clock <= 27000)
  382. factor = 16 * 3;
  383. else if (mode->clock <= 84000)
  384. factor = 8 * 3;
  385. else if (mode->clock <= 167000)
  386. factor = 4 * 3;
  387. else
  388. factor = 2 * 3;
  389. pll_rate = pix_rate * factor;
  390. dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
  391. pll_rate, pix_rate);
  392. clk_set_rate(dpi->tvd_clk, pll_rate);
  393. pll_rate = clk_get_rate(dpi->tvd_clk);
  394. pix_rate = pll_rate / factor;
  395. clk_set_rate(dpi->pixel_clk, pix_rate);
  396. pix_rate = clk_get_rate(dpi->pixel_clk);
  397. dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
  398. pll_rate, pix_rate);
  399. limit.c_bottom = 0x0010;
  400. limit.c_top = 0x0FE0;
  401. limit.y_bottom = 0x0010;
  402. limit.y_top = 0x0FE0;
  403. dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
  404. dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
  405. dpi_pol.hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ?
  406. MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
  407. dpi_pol.vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ?
  408. MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
  409. hsync.sync_width = mode->hsync_end - mode->hsync_start;
  410. hsync.back_porch = mode->htotal - mode->hsync_end;
  411. hsync.front_porch = mode->hsync_start - mode->hdisplay;
  412. hsync.shift_half_line = false;
  413. vsync_lodd.sync_width = mode->vsync_end - mode->vsync_start;
  414. vsync_lodd.back_porch = mode->vtotal - mode->vsync_end;
  415. vsync_lodd.front_porch = mode->vsync_start - mode->vdisplay;
  416. vsync_lodd.shift_half_line = false;
  417. if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
  418. mode->flags & DRM_MODE_FLAG_3D_MASK) {
  419. vsync_leven = vsync_lodd;
  420. vsync_rodd = vsync_lodd;
  421. vsync_reven = vsync_lodd;
  422. vsync_leven.shift_half_line = true;
  423. vsync_reven.shift_half_line = true;
  424. } else if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
  425. !(mode->flags & DRM_MODE_FLAG_3D_MASK)) {
  426. vsync_leven = vsync_lodd;
  427. vsync_leven.shift_half_line = true;
  428. } else if (!(mode->flags & DRM_MODE_FLAG_INTERLACE) &&
  429. mode->flags & DRM_MODE_FLAG_3D_MASK) {
  430. vsync_rodd = vsync_lodd;
  431. }
  432. mtk_dpi_sw_reset(dpi, true);
  433. mtk_dpi_config_pol(dpi, &dpi_pol);
  434. mtk_dpi_config_hsync(dpi, &hsync);
  435. mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd);
  436. mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd);
  437. mtk_dpi_config_vsync_leven(dpi, &vsync_leven);
  438. mtk_dpi_config_vsync_reven(dpi, &vsync_reven);
  439. mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK));
  440. mtk_dpi_config_interface(dpi, !!(mode->flags &
  441. DRM_MODE_FLAG_INTERLACE));
  442. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  443. mtk_dpi_config_fb_size(dpi, mode->hdisplay, mode->vdisplay / 2);
  444. else
  445. mtk_dpi_config_fb_size(dpi, mode->hdisplay, mode->vdisplay);
  446. mtk_dpi_config_channel_limit(dpi, &limit);
  447. mtk_dpi_config_bit_num(dpi, dpi->bit_num);
  448. mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
  449. mtk_dpi_config_yc_map(dpi, dpi->yc_map);
  450. mtk_dpi_config_color_format(dpi, dpi->color_format);
  451. mtk_dpi_config_2n_h_fre(dpi);
  452. mtk_dpi_sw_reset(dpi, false);
  453. return 0;
  454. }
  455. static void mtk_dpi_encoder_destroy(struct drm_encoder *encoder)
  456. {
  457. drm_encoder_cleanup(encoder);
  458. }
  459. static const struct drm_encoder_funcs mtk_dpi_encoder_funcs = {
  460. .destroy = mtk_dpi_encoder_destroy,
  461. };
  462. static bool mtk_dpi_encoder_mode_fixup(struct drm_encoder *encoder,
  463. const struct drm_display_mode *mode,
  464. struct drm_display_mode *adjusted_mode)
  465. {
  466. return true;
  467. }
  468. static void mtk_dpi_encoder_mode_set(struct drm_encoder *encoder,
  469. struct drm_display_mode *mode,
  470. struct drm_display_mode *adjusted_mode)
  471. {
  472. struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder);
  473. drm_mode_copy(&dpi->mode, adjusted_mode);
  474. }
  475. static void mtk_dpi_encoder_disable(struct drm_encoder *encoder)
  476. {
  477. struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder);
  478. mtk_dpi_power_off(dpi, DPI_POWER_ENABLE);
  479. }
  480. static void mtk_dpi_encoder_enable(struct drm_encoder *encoder)
  481. {
  482. struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder);
  483. mtk_dpi_power_on(dpi, DPI_POWER_ENABLE);
  484. mtk_dpi_set_display_mode(dpi, &dpi->mode);
  485. }
  486. static int mtk_dpi_atomic_check(struct drm_encoder *encoder,
  487. struct drm_crtc_state *crtc_state,
  488. struct drm_connector_state *conn_state)
  489. {
  490. return 0;
  491. }
  492. static const struct drm_encoder_helper_funcs mtk_dpi_encoder_helper_funcs = {
  493. .mode_fixup = mtk_dpi_encoder_mode_fixup,
  494. .mode_set = mtk_dpi_encoder_mode_set,
  495. .disable = mtk_dpi_encoder_disable,
  496. .enable = mtk_dpi_encoder_enable,
  497. .atomic_check = mtk_dpi_atomic_check,
  498. };
  499. static void mtk_dpi_start(struct mtk_ddp_comp *comp)
  500. {
  501. struct mtk_dpi *dpi = container_of(comp, struct mtk_dpi, ddp_comp);
  502. mtk_dpi_power_on(dpi, DPI_POWER_START);
  503. }
  504. static void mtk_dpi_stop(struct mtk_ddp_comp *comp)
  505. {
  506. struct mtk_dpi *dpi = container_of(comp, struct mtk_dpi, ddp_comp);
  507. mtk_dpi_power_off(dpi, DPI_POWER_START);
  508. }
  509. static const struct mtk_ddp_comp_funcs mtk_dpi_funcs = {
  510. .start = mtk_dpi_start,
  511. .stop = mtk_dpi_stop,
  512. };
  513. static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
  514. {
  515. struct mtk_dpi *dpi = dev_get_drvdata(dev);
  516. struct drm_device *drm_dev = data;
  517. int ret;
  518. ret = mtk_ddp_comp_register(drm_dev, &dpi->ddp_comp);
  519. if (ret < 0) {
  520. dev_err(dev, "Failed to register component %s: %d\n",
  521. dev->of_node->full_name, ret);
  522. return ret;
  523. }
  524. ret = drm_encoder_init(drm_dev, &dpi->encoder, &mtk_dpi_encoder_funcs,
  525. DRM_MODE_ENCODER_TMDS, NULL);
  526. if (ret) {
  527. dev_err(dev, "Failed to initialize decoder: %d\n", ret);
  528. goto err_unregister;
  529. }
  530. drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs);
  531. /* Currently DPI0 is fixed to be driven by OVL1 */
  532. dpi->encoder.possible_crtcs = BIT(1);
  533. dpi->encoder.bridge->encoder = &dpi->encoder;
  534. ret = drm_bridge_attach(dpi->encoder.dev, dpi->encoder.bridge);
  535. if (ret) {
  536. dev_err(dev, "Failed to attach bridge: %d\n", ret);
  537. goto err_cleanup;
  538. }
  539. dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
  540. dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
  541. dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
  542. dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
  543. return 0;
  544. err_cleanup:
  545. drm_encoder_cleanup(&dpi->encoder);
  546. err_unregister:
  547. mtk_ddp_comp_unregister(drm_dev, &dpi->ddp_comp);
  548. return ret;
  549. }
  550. static void mtk_dpi_unbind(struct device *dev, struct device *master,
  551. void *data)
  552. {
  553. struct mtk_dpi *dpi = dev_get_drvdata(dev);
  554. struct drm_device *drm_dev = data;
  555. drm_encoder_cleanup(&dpi->encoder);
  556. mtk_ddp_comp_unregister(drm_dev, &dpi->ddp_comp);
  557. }
  558. static const struct component_ops mtk_dpi_component_ops = {
  559. .bind = mtk_dpi_bind,
  560. .unbind = mtk_dpi_unbind,
  561. };
  562. static int mtk_dpi_probe(struct platform_device *pdev)
  563. {
  564. struct device *dev = &pdev->dev;
  565. struct mtk_dpi *dpi;
  566. struct resource *mem;
  567. struct device_node *ep, *bridge_node = NULL;
  568. int comp_id;
  569. int ret;
  570. dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
  571. if (!dpi)
  572. return -ENOMEM;
  573. dpi->dev = dev;
  574. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  575. dpi->regs = devm_ioremap_resource(dev, mem);
  576. if (IS_ERR(dpi->regs)) {
  577. ret = PTR_ERR(dpi->regs);
  578. dev_err(dev, "Failed to ioremap mem resource: %d\n", ret);
  579. return ret;
  580. }
  581. dpi->engine_clk = devm_clk_get(dev, "engine");
  582. if (IS_ERR(dpi->engine_clk)) {
  583. ret = PTR_ERR(dpi->engine_clk);
  584. dev_err(dev, "Failed to get engine clock: %d\n", ret);
  585. return ret;
  586. }
  587. dpi->pixel_clk = devm_clk_get(dev, "pixel");
  588. if (IS_ERR(dpi->pixel_clk)) {
  589. ret = PTR_ERR(dpi->pixel_clk);
  590. dev_err(dev, "Failed to get pixel clock: %d\n", ret);
  591. return ret;
  592. }
  593. dpi->tvd_clk = devm_clk_get(dev, "pll");
  594. if (IS_ERR(dpi->tvd_clk)) {
  595. ret = PTR_ERR(dpi->tvd_clk);
  596. dev_err(dev, "Failed to get tvdpll clock: %d\n", ret);
  597. return ret;
  598. }
  599. dpi->irq = platform_get_irq(pdev, 0);
  600. if (dpi->irq <= 0) {
  601. dev_err(dev, "Failed to get irq: %d\n", dpi->irq);
  602. return -EINVAL;
  603. }
  604. ep = of_graph_get_next_endpoint(dev->of_node, NULL);
  605. if (ep) {
  606. bridge_node = of_graph_get_remote_port_parent(ep);
  607. of_node_put(ep);
  608. }
  609. if (!bridge_node) {
  610. dev_err(dev, "Failed to find bridge node\n");
  611. return -ENODEV;
  612. }
  613. dev_info(dev, "Found bridge node: %s\n", bridge_node->full_name);
  614. dpi->encoder.bridge = of_drm_find_bridge(bridge_node);
  615. of_node_put(bridge_node);
  616. if (!dpi->encoder.bridge)
  617. return -EPROBE_DEFER;
  618. comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI);
  619. if (comp_id < 0) {
  620. dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
  621. return comp_id;
  622. }
  623. ret = mtk_ddp_comp_init(dev, dev->of_node, &dpi->ddp_comp, comp_id,
  624. &mtk_dpi_funcs);
  625. if (ret) {
  626. dev_err(dev, "Failed to initialize component: %d\n", ret);
  627. return ret;
  628. }
  629. platform_set_drvdata(pdev, dpi);
  630. ret = component_add(dev, &mtk_dpi_component_ops);
  631. if (ret) {
  632. dev_err(dev, "Failed to add component: %d\n", ret);
  633. return ret;
  634. }
  635. return 0;
  636. }
  637. static int mtk_dpi_remove(struct platform_device *pdev)
  638. {
  639. component_del(&pdev->dev, &mtk_dpi_component_ops);
  640. return 0;
  641. }
  642. static const struct of_device_id mtk_dpi_of_ids[] = {
  643. { .compatible = "mediatek,mt8173-dpi", },
  644. {}
  645. };
  646. struct platform_driver mtk_dpi_driver = {
  647. .probe = mtk_dpi_probe,
  648. .remove = mtk_dpi_remove,
  649. .driver = {
  650. .name = "mediatek-dpi",
  651. .of_match_table = mtk_dpi_of_ids,
  652. },
  653. };