nwflash.c 13 KB

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  1. /*
  2. * Flash memory interface rev.5 driver for the Intel
  3. * Flash chips used on the NetWinder.
  4. *
  5. * 20/08/2000 RMK use __ioremap to map flash into virtual memory
  6. * make a few more places use "volatile"
  7. * 22/05/2001 RMK - Lock read against write
  8. * - merge printk level changes (with mods) from Alan Cox.
  9. * - use *ppos as the file position, not file->f_pos.
  10. * - fix check for out of range pos and r/w size
  11. *
  12. * Please note that we are tampering with the only flash chip in the
  13. * machine, which contains the bootup code. We therefore have the
  14. * power to convert these machines into doorstops...
  15. */
  16. #include <linux/module.h>
  17. #include <linux/types.h>
  18. #include <linux/fs.h>
  19. #include <linux/errno.h>
  20. #include <linux/mm.h>
  21. #include <linux/delay.h>
  22. #include <linux/proc_fs.h>
  23. #include <linux/miscdevice.h>
  24. #include <linux/spinlock.h>
  25. #include <linux/rwsem.h>
  26. #include <linux/init.h>
  27. #include <linux/mutex.h>
  28. #include <linux/jiffies.h>
  29. #include <asm/hardware/dec21285.h>
  30. #include <asm/io.h>
  31. #include <asm/mach-types.h>
  32. #include <asm/uaccess.h>
  33. /*****************************************************************************/
  34. #include <asm/nwflash.h>
  35. #define NWFLASH_VERSION "6.4"
  36. static DEFINE_MUTEX(flash_mutex);
  37. static void kick_open(void);
  38. static int get_flash_id(void);
  39. static int erase_block(int nBlock);
  40. static int write_block(unsigned long p, const char __user *buf, int count);
  41. #define KFLASH_SIZE 1024*1024 //1 Meg
  42. #define KFLASH_SIZE4 4*1024*1024 //4 Meg
  43. #define KFLASH_ID 0x89A6 //Intel flash
  44. #define KFLASH_ID4 0xB0D4 //Intel flash 4Meg
  45. static bool flashdebug; //if set - we will display progress msgs
  46. static int gbWriteEnable;
  47. static int gbWriteBase64Enable;
  48. static volatile unsigned char *FLASH_BASE;
  49. static int gbFlashSize = KFLASH_SIZE;
  50. static DEFINE_MUTEX(nwflash_mutex);
  51. static int get_flash_id(void)
  52. {
  53. volatile unsigned int c1, c2;
  54. /*
  55. * try to get flash chip ID
  56. */
  57. kick_open();
  58. c2 = inb(0x80);
  59. *(volatile unsigned char *) (FLASH_BASE + 0x8000) = 0x90;
  60. udelay(15);
  61. c1 = *(volatile unsigned char *) FLASH_BASE;
  62. c2 = inb(0x80);
  63. /*
  64. * on 4 Meg flash the second byte is actually at offset 2...
  65. */
  66. if (c1 == 0xB0)
  67. c2 = *(volatile unsigned char *) (FLASH_BASE + 2);
  68. else
  69. c2 = *(volatile unsigned char *) (FLASH_BASE + 1);
  70. c2 += (c1 << 8);
  71. /*
  72. * set it back to read mode
  73. */
  74. *(volatile unsigned char *) (FLASH_BASE + 0x8000) = 0xFF;
  75. if (c2 == KFLASH_ID4)
  76. gbFlashSize = KFLASH_SIZE4;
  77. return c2;
  78. }
  79. static long flash_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
  80. {
  81. mutex_lock(&flash_mutex);
  82. switch (cmd) {
  83. case CMD_WRITE_DISABLE:
  84. gbWriteBase64Enable = 0;
  85. gbWriteEnable = 0;
  86. break;
  87. case CMD_WRITE_ENABLE:
  88. gbWriteEnable = 1;
  89. break;
  90. case CMD_WRITE_BASE64K_ENABLE:
  91. gbWriteBase64Enable = 1;
  92. break;
  93. default:
  94. gbWriteBase64Enable = 0;
  95. gbWriteEnable = 0;
  96. mutex_unlock(&flash_mutex);
  97. return -EINVAL;
  98. }
  99. mutex_unlock(&flash_mutex);
  100. return 0;
  101. }
  102. static ssize_t flash_read(struct file *file, char __user *buf, size_t size,
  103. loff_t *ppos)
  104. {
  105. ssize_t ret;
  106. if (flashdebug)
  107. printk(KERN_DEBUG "flash_read: flash_read: offset=0x%llx, "
  108. "buffer=%p, count=0x%zx.\n", *ppos, buf, size);
  109. /*
  110. * We now lock against reads and writes. --rmk
  111. */
  112. if (mutex_lock_interruptible(&nwflash_mutex))
  113. return -ERESTARTSYS;
  114. ret = simple_read_from_buffer(buf, size, ppos, (void *)FLASH_BASE, gbFlashSize);
  115. mutex_unlock(&nwflash_mutex);
  116. return ret;
  117. }
  118. static ssize_t flash_write(struct file *file, const char __user *buf,
  119. size_t size, loff_t * ppos)
  120. {
  121. unsigned long p = *ppos;
  122. unsigned int count = size;
  123. int written;
  124. int nBlock, temp, rc;
  125. int i, j;
  126. if (flashdebug)
  127. printk("flash_write: offset=0x%lX, buffer=0x%p, count=0x%X.\n",
  128. p, buf, count);
  129. if (!gbWriteEnable)
  130. return -EINVAL;
  131. if (p < 64 * 1024 && (!gbWriteBase64Enable))
  132. return -EINVAL;
  133. /*
  134. * check for out of range pos or count
  135. */
  136. if (p >= gbFlashSize)
  137. return count ? -ENXIO : 0;
  138. if (count > gbFlashSize - p)
  139. count = gbFlashSize - p;
  140. if (!access_ok(VERIFY_READ, buf, count))
  141. return -EFAULT;
  142. /*
  143. * We now lock against reads and writes. --rmk
  144. */
  145. if (mutex_lock_interruptible(&nwflash_mutex))
  146. return -ERESTARTSYS;
  147. written = 0;
  148. nBlock = (int) p >> 16; //block # of 64K bytes
  149. /*
  150. * # of 64K blocks to erase and write
  151. */
  152. temp = ((int) (p + count) >> 16) - nBlock + 1;
  153. /*
  154. * write ends at exactly 64k boundary?
  155. */
  156. if (((int) (p + count) & 0xFFFF) == 0)
  157. temp -= 1;
  158. if (flashdebug)
  159. printk(KERN_DEBUG "flash_write: writing %d block(s) "
  160. "starting at %d.\n", temp, nBlock);
  161. for (; temp; temp--, nBlock++) {
  162. if (flashdebug)
  163. printk(KERN_DEBUG "flash_write: erasing block %d.\n", nBlock);
  164. /*
  165. * first we have to erase the block(s), where we will write...
  166. */
  167. i = 0;
  168. j = 0;
  169. RetryBlock:
  170. do {
  171. rc = erase_block(nBlock);
  172. i++;
  173. } while (rc && i < 10);
  174. if (rc) {
  175. printk(KERN_ERR "flash_write: erase error %x\n", rc);
  176. break;
  177. }
  178. if (flashdebug)
  179. printk(KERN_DEBUG "flash_write: writing offset %lX, "
  180. "from buf %p, bytes left %X.\n", p, buf,
  181. count - written);
  182. /*
  183. * write_block will limit write to space left in this block
  184. */
  185. rc = write_block(p, buf, count - written);
  186. j++;
  187. /*
  188. * if somehow write verify failed? Can't happen??
  189. */
  190. if (!rc) {
  191. /*
  192. * retry up to 10 times
  193. */
  194. if (j < 10)
  195. goto RetryBlock;
  196. else
  197. /*
  198. * else quit with error...
  199. */
  200. rc = -1;
  201. }
  202. if (rc < 0) {
  203. printk(KERN_ERR "flash_write: write error %X\n", rc);
  204. break;
  205. }
  206. p += rc;
  207. buf += rc;
  208. written += rc;
  209. *ppos += rc;
  210. if (flashdebug)
  211. printk(KERN_DEBUG "flash_write: written 0x%X bytes OK.\n", written);
  212. }
  213. mutex_unlock(&nwflash_mutex);
  214. return written;
  215. }
  216. /*
  217. * The memory devices use the full 32/64 bits of the offset, and so we cannot
  218. * check against negative addresses: they are ok. The return value is weird,
  219. * though, in that case (0).
  220. *
  221. * also note that seeking relative to the "end of file" isn't supported:
  222. * it has no meaning, so it returns -EINVAL.
  223. */
  224. static loff_t flash_llseek(struct file *file, loff_t offset, int orig)
  225. {
  226. loff_t ret;
  227. mutex_lock(&flash_mutex);
  228. if (flashdebug)
  229. printk(KERN_DEBUG "flash_llseek: offset=0x%X, orig=0x%X.\n",
  230. (unsigned int) offset, orig);
  231. ret = no_seek_end_llseek_size(file, offset, orig, gbFlashSize);
  232. mutex_unlock(&flash_mutex);
  233. return ret;
  234. }
  235. /*
  236. * assume that main Write routine did the parameter checking...
  237. * so just go ahead and erase, what requested!
  238. */
  239. static int erase_block(int nBlock)
  240. {
  241. volatile unsigned int c1;
  242. volatile unsigned char *pWritePtr;
  243. unsigned long timeout;
  244. int temp, temp1;
  245. /*
  246. * reset footbridge to the correct offset 0 (...0..3)
  247. */
  248. *CSR_ROMWRITEREG = 0;
  249. /*
  250. * dummy ROM read
  251. */
  252. c1 = *(volatile unsigned char *) (FLASH_BASE + 0x8000);
  253. kick_open();
  254. /*
  255. * reset status if old errors
  256. */
  257. *(volatile unsigned char *) (FLASH_BASE + 0x8000) = 0x50;
  258. /*
  259. * erase a block...
  260. * aim at the middle of a current block...
  261. */
  262. pWritePtr = (unsigned char *) ((unsigned int) (FLASH_BASE + 0x8000 + (nBlock << 16)));
  263. /*
  264. * dummy read
  265. */
  266. c1 = *pWritePtr;
  267. kick_open();
  268. /*
  269. * erase
  270. */
  271. *(volatile unsigned char *) pWritePtr = 0x20;
  272. /*
  273. * confirm
  274. */
  275. *(volatile unsigned char *) pWritePtr = 0xD0;
  276. /*
  277. * wait 10 ms
  278. */
  279. msleep(10);
  280. /*
  281. * wait while erasing in process (up to 10 sec)
  282. */
  283. timeout = jiffies + 10 * HZ;
  284. c1 = 0;
  285. while (!(c1 & 0x80) && time_before(jiffies, timeout)) {
  286. msleep(10);
  287. /*
  288. * read any address
  289. */
  290. c1 = *(volatile unsigned char *) (pWritePtr);
  291. // printk("Flash_erase: status=%X.\n",c1);
  292. }
  293. /*
  294. * set flash for normal read access
  295. */
  296. kick_open();
  297. // *(volatile unsigned char*)(FLASH_BASE+0x8000) = 0xFF;
  298. *(volatile unsigned char *) pWritePtr = 0xFF; //back to normal operation
  299. /*
  300. * check if erase errors were reported
  301. */
  302. if (c1 & 0x20) {
  303. printk(KERN_ERR "flash_erase: err at %p\n", pWritePtr);
  304. /*
  305. * reset error
  306. */
  307. *(volatile unsigned char *) (FLASH_BASE + 0x8000) = 0x50;
  308. return -2;
  309. }
  310. /*
  311. * just to make sure - verify if erased OK...
  312. */
  313. msleep(10);
  314. pWritePtr = (unsigned char *) ((unsigned int) (FLASH_BASE + (nBlock << 16)));
  315. for (temp = 0; temp < 16 * 1024; temp++, pWritePtr += 4) {
  316. if ((temp1 = *(volatile unsigned int *) pWritePtr) != 0xFFFFFFFF) {
  317. printk(KERN_ERR "flash_erase: verify err at %p = %X\n",
  318. pWritePtr, temp1);
  319. return -1;
  320. }
  321. }
  322. return 0;
  323. }
  324. /*
  325. * write_block will limit number of bytes written to the space in this block
  326. */
  327. static int write_block(unsigned long p, const char __user *buf, int count)
  328. {
  329. volatile unsigned int c1;
  330. volatile unsigned int c2;
  331. unsigned char *pWritePtr;
  332. unsigned int uAddress;
  333. unsigned int offset;
  334. unsigned long timeout;
  335. unsigned long timeout1;
  336. pWritePtr = (unsigned char *) ((unsigned int) (FLASH_BASE + p));
  337. /*
  338. * check if write will end in this block....
  339. */
  340. offset = p & 0xFFFF;
  341. if (offset + count > 0x10000)
  342. count = 0x10000 - offset;
  343. /*
  344. * wait up to 30 sec for this block
  345. */
  346. timeout = jiffies + 30 * HZ;
  347. for (offset = 0; offset < count; offset++, pWritePtr++) {
  348. uAddress = (unsigned int) pWritePtr;
  349. uAddress &= 0xFFFFFFFC;
  350. if (__get_user(c2, buf + offset))
  351. return -EFAULT;
  352. WriteRetry:
  353. /*
  354. * dummy read
  355. */
  356. c1 = *(volatile unsigned char *) (FLASH_BASE + 0x8000);
  357. /*
  358. * kick open the write gate
  359. */
  360. kick_open();
  361. /*
  362. * program footbridge to the correct offset...0..3
  363. */
  364. *CSR_ROMWRITEREG = (unsigned int) pWritePtr & 3;
  365. /*
  366. * write cmd
  367. */
  368. *(volatile unsigned char *) (uAddress) = 0x40;
  369. /*
  370. * data to write
  371. */
  372. *(volatile unsigned char *) (uAddress) = c2;
  373. /*
  374. * get status
  375. */
  376. *(volatile unsigned char *) (FLASH_BASE + 0x10000) = 0x70;
  377. c1 = 0;
  378. /*
  379. * wait up to 1 sec for this byte
  380. */
  381. timeout1 = jiffies + 1 * HZ;
  382. /*
  383. * while not ready...
  384. */
  385. while (!(c1 & 0x80) && time_before(jiffies, timeout1))
  386. c1 = *(volatile unsigned char *) (FLASH_BASE + 0x8000);
  387. /*
  388. * if timeout getting status
  389. */
  390. if (time_after_eq(jiffies, timeout1)) {
  391. kick_open();
  392. /*
  393. * reset err
  394. */
  395. *(volatile unsigned char *) (FLASH_BASE + 0x8000) = 0x50;
  396. goto WriteRetry;
  397. }
  398. /*
  399. * switch on read access, as a default flash operation mode
  400. */
  401. kick_open();
  402. /*
  403. * read access
  404. */
  405. *(volatile unsigned char *) (FLASH_BASE + 0x8000) = 0xFF;
  406. /*
  407. * if hardware reports an error writing, and not timeout -
  408. * reset the chip and retry
  409. */
  410. if (c1 & 0x10) {
  411. kick_open();
  412. /*
  413. * reset err
  414. */
  415. *(volatile unsigned char *) (FLASH_BASE + 0x8000) = 0x50;
  416. /*
  417. * before timeout?
  418. */
  419. if (time_before(jiffies, timeout)) {
  420. if (flashdebug)
  421. printk(KERN_DEBUG "write_block: Retrying write at 0x%X)n",
  422. pWritePtr - FLASH_BASE);
  423. /*
  424. * wait couple ms
  425. */
  426. msleep(10);
  427. goto WriteRetry;
  428. } else {
  429. printk(KERN_ERR "write_block: timeout at 0x%X\n",
  430. pWritePtr - FLASH_BASE);
  431. /*
  432. * return error -2
  433. */
  434. return -2;
  435. }
  436. }
  437. }
  438. msleep(10);
  439. pWritePtr = (unsigned char *) ((unsigned int) (FLASH_BASE + p));
  440. for (offset = 0; offset < count; offset++) {
  441. char c, c1;
  442. if (__get_user(c, buf))
  443. return -EFAULT;
  444. buf++;
  445. if ((c1 = *pWritePtr++) != c) {
  446. printk(KERN_ERR "write_block: verify error at 0x%X (%02X!=%02X)\n",
  447. pWritePtr - FLASH_BASE, c1, c);
  448. return 0;
  449. }
  450. }
  451. return count;
  452. }
  453. static void kick_open(void)
  454. {
  455. unsigned long flags;
  456. /*
  457. * we want to write a bit pattern XXX1 to Xilinx to enable
  458. * the write gate, which will be open for about the next 2ms.
  459. */
  460. raw_spin_lock_irqsave(&nw_gpio_lock, flags);
  461. nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE);
  462. raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
  463. /*
  464. * let the ISA bus to catch on...
  465. */
  466. udelay(25);
  467. }
  468. static const struct file_operations flash_fops =
  469. {
  470. .owner = THIS_MODULE,
  471. .llseek = flash_llseek,
  472. .read = flash_read,
  473. .write = flash_write,
  474. .unlocked_ioctl = flash_ioctl,
  475. };
  476. static struct miscdevice flash_miscdev =
  477. {
  478. FLASH_MINOR,
  479. "nwflash",
  480. &flash_fops
  481. };
  482. static int __init nwflash_init(void)
  483. {
  484. int ret = -ENODEV;
  485. if (machine_is_netwinder()) {
  486. int id;
  487. FLASH_BASE = ioremap(DC21285_FLASH, KFLASH_SIZE4);
  488. if (!FLASH_BASE)
  489. goto out;
  490. id = get_flash_id();
  491. if ((id != KFLASH_ID) && (id != KFLASH_ID4)) {
  492. ret = -ENXIO;
  493. iounmap((void *)FLASH_BASE);
  494. printk("Flash: incorrect ID 0x%04X.\n", id);
  495. goto out;
  496. }
  497. printk("Flash ROM driver v.%s, flash device ID 0x%04X, size %d Mb.\n",
  498. NWFLASH_VERSION, id, gbFlashSize / (1024 * 1024));
  499. ret = misc_register(&flash_miscdev);
  500. if (ret < 0) {
  501. iounmap((void *)FLASH_BASE);
  502. }
  503. }
  504. out:
  505. return ret;
  506. }
  507. static void __exit nwflash_exit(void)
  508. {
  509. misc_deregister(&flash_miscdev);
  510. iounmap((void *)FLASH_BASE);
  511. }
  512. MODULE_LICENSE("GPL");
  513. module_param(flashdebug, bool, 0644);
  514. module_init(nwflash_init);
  515. module_exit(nwflash_exit);