topology.c 2.5 KB

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  1. /*
  2. * Check for extended topology enumeration cpuid leaf 0xb and if it
  3. * exists, use it for populating initial_apicid and cpu topology
  4. * detection.
  5. */
  6. #include <linux/cpu.h>
  7. #include <asm/apic.h>
  8. #include <asm/pat.h>
  9. #include <asm/processor.h>
  10. /* leaf 0xb SMT level */
  11. #define SMT_LEVEL 0
  12. /* leaf 0xb sub-leaf types */
  13. #define INVALID_TYPE 0
  14. #define SMT_TYPE 1
  15. #define CORE_TYPE 2
  16. #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
  17. #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
  18. #define LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff)
  19. /*
  20. * Check for extended topology enumeration cpuid leaf 0xb and if it
  21. * exists, use it for populating initial_apicid and cpu topology
  22. * detection.
  23. */
  24. void detect_extended_topology(struct cpuinfo_x86 *c)
  25. {
  26. #ifdef CONFIG_SMP
  27. unsigned int eax, ebx, ecx, edx, sub_index;
  28. unsigned int ht_mask_width, core_plus_mask_width;
  29. unsigned int core_select_mask, core_level_siblings;
  30. static bool printed;
  31. if (c->cpuid_level < 0xb)
  32. return;
  33. cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
  34. /*
  35. * check if the cpuid leaf 0xb is actually implemented.
  36. */
  37. if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE))
  38. return;
  39. set_cpu_cap(c, X86_FEATURE_XTOPOLOGY);
  40. /*
  41. * initial apic id, which also represents 32-bit extended x2apic id.
  42. */
  43. c->initial_apicid = edx;
  44. /*
  45. * Populate HT related information from sub-leaf level 0.
  46. */
  47. core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx);
  48. core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
  49. sub_index = 1;
  50. do {
  51. cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
  52. /*
  53. * Check for the Core type in the implemented sub leaves.
  54. */
  55. if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
  56. core_level_siblings = LEVEL_MAX_SIBLINGS(ebx);
  57. core_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
  58. break;
  59. }
  60. sub_index++;
  61. } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
  62. core_select_mask = (~(-1 << core_plus_mask_width)) >> ht_mask_width;
  63. c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, ht_mask_width)
  64. & core_select_mask;
  65. c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, core_plus_mask_width);
  66. /*
  67. * Reinit the apicid, now that we have extended initial_apicid.
  68. */
  69. c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
  70. c->x86_max_cores = (core_level_siblings / smp_num_siblings);
  71. if (!printed) {
  72. pr_info("CPU: Physical Processor ID: %d\n",
  73. c->phys_proc_id);
  74. if (c->x86_max_cores > 1)
  75. pr_info("CPU: Processor Core ID: %d\n",
  76. c->cpu_core_id);
  77. printed = 1;
  78. }
  79. return;
  80. #endif
  81. }