entry_64.S 45 KB

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  1. /*
  2. * linux/arch/x86_64/entry.S
  3. *
  4. * Copyright (C) 1991, 1992 Linus Torvalds
  5. * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
  6. * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
  7. *
  8. * entry.S contains the system-call and fault low-level handling routines.
  9. *
  10. * Some of this is documented in Documentation/x86/entry_64.txt
  11. *
  12. * A note on terminology:
  13. * - iret frame: Architecture defined interrupt frame from SS to RIP
  14. * at the top of the kernel process stack.
  15. *
  16. * Some macro usage:
  17. * - ENTRY/END: Define functions in the symbol table.
  18. * - TRACE_IRQ_*: Trace hardirq state for lock debugging.
  19. * - idtentry: Define exception entry points.
  20. */
  21. #include <linux/linkage.h>
  22. #include <asm/segment.h>
  23. #include <asm/cache.h>
  24. #include <asm/errno.h>
  25. #include "calling.h"
  26. #include <asm/asm-offsets.h>
  27. #include <asm/msr.h>
  28. #include <asm/unistd.h>
  29. #include <asm/thread_info.h>
  30. #include <asm/hw_irq.h>
  31. #include <asm/page_types.h>
  32. #include <asm/irqflags.h>
  33. #include <asm/paravirt.h>
  34. #include <asm/percpu.h>
  35. #include <asm/asm.h>
  36. #include <asm/smap.h>
  37. #include <asm/pgtable_types.h>
  38. #include <asm/export.h>
  39. #include <asm/kaiser.h>
  40. #include <asm/nospec-branch.h>
  41. #include <linux/err.h>
  42. /* Avoid __ASSEMBLER__'ifying <linux/audit.h> just for this. */
  43. #include <linux/elf-em.h>
  44. #define AUDIT_ARCH_X86_64 (EM_X86_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
  45. #define __AUDIT_ARCH_64BIT 0x80000000
  46. #define __AUDIT_ARCH_LE 0x40000000
  47. .code64
  48. .section .entry.text, "ax"
  49. #ifdef CONFIG_PARAVIRT
  50. ENTRY(native_usergs_sysret64)
  51. swapgs
  52. sysretq
  53. ENDPROC(native_usergs_sysret64)
  54. #endif /* CONFIG_PARAVIRT */
  55. .macro TRACE_IRQS_IRETQ
  56. #ifdef CONFIG_TRACE_IRQFLAGS
  57. bt $9, EFLAGS(%rsp) /* interrupts off? */
  58. jnc 1f
  59. TRACE_IRQS_ON
  60. 1:
  61. #endif
  62. .endm
  63. /*
  64. * When dynamic function tracer is enabled it will add a breakpoint
  65. * to all locations that it is about to modify, sync CPUs, update
  66. * all the code, sync CPUs, then remove the breakpoints. In this time
  67. * if lockdep is enabled, it might jump back into the debug handler
  68. * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF).
  69. *
  70. * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to
  71. * make sure the stack pointer does not get reset back to the top
  72. * of the debug stack, and instead just reuses the current stack.
  73. */
  74. #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS)
  75. .macro TRACE_IRQS_OFF_DEBUG
  76. call debug_stack_set_zero
  77. TRACE_IRQS_OFF
  78. call debug_stack_reset
  79. .endm
  80. .macro TRACE_IRQS_ON_DEBUG
  81. call debug_stack_set_zero
  82. TRACE_IRQS_ON
  83. call debug_stack_reset
  84. .endm
  85. .macro TRACE_IRQS_IRETQ_DEBUG
  86. bt $9, EFLAGS(%rsp) /* interrupts off? */
  87. jnc 1f
  88. TRACE_IRQS_ON_DEBUG
  89. 1:
  90. .endm
  91. #else
  92. # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF
  93. # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON
  94. # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ
  95. #endif
  96. /*
  97. * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
  98. *
  99. * This is the only entry point used for 64-bit system calls. The
  100. * hardware interface is reasonably well designed and the register to
  101. * argument mapping Linux uses fits well with the registers that are
  102. * available when SYSCALL is used.
  103. *
  104. * SYSCALL instructions can be found inlined in libc implementations as
  105. * well as some other programs and libraries. There are also a handful
  106. * of SYSCALL instructions in the vDSO used, for example, as a
  107. * clock_gettimeofday fallback.
  108. *
  109. * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
  110. * then loads new ss, cs, and rip from previously programmed MSRs.
  111. * rflags gets masked by a value from another MSR (so CLD and CLAC
  112. * are not needed). SYSCALL does not save anything on the stack
  113. * and does not change rsp.
  114. *
  115. * Registers on entry:
  116. * rax system call number
  117. * rcx return address
  118. * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
  119. * rdi arg0
  120. * rsi arg1
  121. * rdx arg2
  122. * r10 arg3 (needs to be moved to rcx to conform to C ABI)
  123. * r8 arg4
  124. * r9 arg5
  125. * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
  126. *
  127. * Only called from user space.
  128. *
  129. * When user can change pt_regs->foo always force IRET. That is because
  130. * it deals with uncanonical addresses better. SYSRET has trouble
  131. * with them due to bugs in both AMD and Intel CPUs.
  132. */
  133. ENTRY(entry_SYSCALL_64)
  134. /*
  135. * Interrupts are off on entry.
  136. * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON,
  137. * it is too small to ever cause noticeable irq latency.
  138. */
  139. SWAPGS_UNSAFE_STACK
  140. SWITCH_KERNEL_CR3_NO_STACK
  141. /*
  142. * A hypervisor implementation might want to use a label
  143. * after the swapgs, so that it can do the swapgs
  144. * for the guest and jump here on syscall.
  145. */
  146. GLOBAL(entry_SYSCALL_64_after_swapgs)
  147. movq %rsp, PER_CPU_VAR(rsp_scratch)
  148. movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
  149. TRACE_IRQS_OFF
  150. /* Construct struct pt_regs on stack */
  151. pushq $__USER_DS /* pt_regs->ss */
  152. pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */
  153. pushq %r11 /* pt_regs->flags */
  154. pushq $__USER_CS /* pt_regs->cs */
  155. pushq %rcx /* pt_regs->ip */
  156. pushq %rax /* pt_regs->orig_ax */
  157. pushq %rdi /* pt_regs->di */
  158. pushq %rsi /* pt_regs->si */
  159. pushq %rdx /* pt_regs->dx */
  160. pushq %rcx /* pt_regs->cx */
  161. pushq $-ENOSYS /* pt_regs->ax */
  162. pushq %r8 /* pt_regs->r8 */
  163. pushq %r9 /* pt_regs->r9 */
  164. pushq %r10 /* pt_regs->r10 */
  165. /*
  166. * Clear extra registers that a speculation attack might
  167. * otherwise want to exploit. Interleave XOR with PUSH
  168. * for better uop scheduling:
  169. */
  170. xorq %r10, %r10 /* nospec r10 */
  171. pushq %r11 /* pt_regs->r11 */
  172. xorq %r11, %r11 /* nospec r11 */
  173. pushq %rbx /* pt_regs->rbx */
  174. xorl %ebx, %ebx /* nospec rbx */
  175. pushq %rbp /* pt_regs->rbp */
  176. xorl %ebp, %ebp /* nospec rbp */
  177. pushq %r12 /* pt_regs->r12 */
  178. xorq %r12, %r12 /* nospec r12 */
  179. pushq %r13 /* pt_regs->r13 */
  180. xorq %r13, %r13 /* nospec r13 */
  181. pushq %r14 /* pt_regs->r14 */
  182. xorq %r14, %r14 /* nospec r14 */
  183. pushq %r15 /* pt_regs->r15 */
  184. xorq %r15, %r15 /* nospec r15 */
  185. /* IRQs are off. */
  186. movq %rsp, %rdi
  187. call do_syscall_64 /* returns with IRQs disabled */
  188. RESTORE_EXTRA_REGS
  189. TRACE_IRQS_IRETQ /* we're about to change IF */
  190. /*
  191. * Try to use SYSRET instead of IRET if we're returning to
  192. * a completely clean 64-bit userspace context.
  193. */
  194. movq RCX(%rsp), %rcx
  195. movq RIP(%rsp), %r11
  196. cmpq %rcx, %r11 /* RCX == RIP */
  197. jne opportunistic_sysret_failed
  198. /*
  199. * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
  200. * in kernel space. This essentially lets the user take over
  201. * the kernel, since userspace controls RSP.
  202. *
  203. * If width of "canonical tail" ever becomes variable, this will need
  204. * to be updated to remain correct on both old and new CPUs.
  205. */
  206. .ifne __VIRTUAL_MASK_SHIFT - 47
  207. .error "virtual address width changed -- SYSRET checks need update"
  208. .endif
  209. /* Change top 16 bits to be the sign-extension of 47th bit */
  210. shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
  211. sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
  212. /* If this changed %rcx, it was not canonical */
  213. cmpq %rcx, %r11
  214. jne opportunistic_sysret_failed
  215. cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
  216. jne opportunistic_sysret_failed
  217. movq R11(%rsp), %r11
  218. cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
  219. jne opportunistic_sysret_failed
  220. /*
  221. * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
  222. * restore RF properly. If the slowpath sets it for whatever reason, we
  223. * need to restore it correctly.
  224. *
  225. * SYSRET can restore TF, but unlike IRET, restoring TF results in a
  226. * trap from userspace immediately after SYSRET. This would cause an
  227. * infinite loop whenever #DB happens with register state that satisfies
  228. * the opportunistic SYSRET conditions. For example, single-stepping
  229. * this user code:
  230. *
  231. * movq $stuck_here, %rcx
  232. * pushfq
  233. * popq %r11
  234. * stuck_here:
  235. *
  236. * would never get past 'stuck_here'.
  237. */
  238. testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
  239. jnz opportunistic_sysret_failed
  240. /* nothing to check for RSP */
  241. cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
  242. jne opportunistic_sysret_failed
  243. /*
  244. * We win! This label is here just for ease of understanding
  245. * perf profiles. Nothing jumps here.
  246. */
  247. syscall_return_via_sysret:
  248. /* rcx and r11 are already restored (see code above) */
  249. RESTORE_C_REGS_EXCEPT_RCX_R11
  250. /*
  251. * This opens a window where we have a user CR3, but are
  252. * running in the kernel. This makes using the CS
  253. * register useless for telling whether or not we need to
  254. * switch CR3 in NMIs. Normal interrupts are OK because
  255. * they are off here.
  256. */
  257. SWITCH_USER_CR3
  258. movq RSP(%rsp), %rsp
  259. USERGS_SYSRET64
  260. opportunistic_sysret_failed:
  261. /*
  262. * This opens a window where we have a user CR3, but are
  263. * running in the kernel. This makes using the CS
  264. * register useless for telling whether or not we need to
  265. * switch CR3 in NMIs. Normal interrupts are OK because
  266. * they are off here.
  267. */
  268. SWITCH_USER_CR3
  269. SWAPGS
  270. jmp restore_c_regs_and_iret
  271. END(entry_SYSCALL_64)
  272. /*
  273. * %rdi: prev task
  274. * %rsi: next task
  275. */
  276. ENTRY(__switch_to_asm)
  277. /*
  278. * Save callee-saved registers
  279. * This must match the order in inactive_task_frame
  280. */
  281. pushq %rbp
  282. pushq %rbx
  283. pushq %r12
  284. pushq %r13
  285. pushq %r14
  286. pushq %r15
  287. /* switch stack */
  288. movq %rsp, TASK_threadsp(%rdi)
  289. movq TASK_threadsp(%rsi), %rsp
  290. #ifdef CONFIG_CC_STACKPROTECTOR
  291. movq TASK_stack_canary(%rsi), %rbx
  292. movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset
  293. #endif
  294. #ifdef CONFIG_RETPOLINE
  295. /*
  296. * When switching from a shallower to a deeper call stack
  297. * the RSB may either underflow or use entries populated
  298. * with userspace addresses. On CPUs where those concerns
  299. * exist, overwrite the RSB with entries which capture
  300. * speculative execution to prevent attack.
  301. */
  302. FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
  303. #endif
  304. /* restore callee-saved registers */
  305. popq %r15
  306. popq %r14
  307. popq %r13
  308. popq %r12
  309. popq %rbx
  310. popq %rbp
  311. jmp __switch_to
  312. END(__switch_to_asm)
  313. /*
  314. * A newly forked process directly context switches into this address.
  315. *
  316. * rax: prev task we switched from
  317. * rbx: kernel thread func (NULL for user thread)
  318. * r12: kernel thread arg
  319. */
  320. ENTRY(ret_from_fork)
  321. movq %rax, %rdi
  322. call schedule_tail /* rdi: 'prev' task parameter */
  323. testq %rbx, %rbx /* from kernel_thread? */
  324. jnz 1f /* kernel threads are uncommon */
  325. 2:
  326. movq %rsp, %rdi
  327. call syscall_return_slowpath /* returns with IRQs disabled */
  328. TRACE_IRQS_ON /* user mode is traced as IRQS on */
  329. SWITCH_USER_CR3
  330. SWAPGS
  331. jmp restore_regs_and_iret
  332. 1:
  333. /* kernel thread */
  334. movq %r12, %rdi
  335. CALL_NOSPEC %rbx
  336. /*
  337. * A kernel thread is allowed to return here after successfully
  338. * calling do_execve(). Exit to userspace to complete the execve()
  339. * syscall.
  340. */
  341. movq $0, RAX(%rsp)
  342. jmp 2b
  343. END(ret_from_fork)
  344. /*
  345. * Build the entry stubs with some assembler magic.
  346. * We pack 1 stub into every 8-byte block.
  347. */
  348. .align 8
  349. ENTRY(irq_entries_start)
  350. vector=FIRST_EXTERNAL_VECTOR
  351. .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
  352. pushq $(~vector+0x80) /* Note: always in signed byte range */
  353. vector=vector+1
  354. jmp common_interrupt
  355. .align 8
  356. .endr
  357. END(irq_entries_start)
  358. /*
  359. * Interrupt entry/exit.
  360. *
  361. * Interrupt entry points save only callee clobbered registers in fast path.
  362. *
  363. * Entry runs with interrupts off.
  364. */
  365. /* 0(%rsp): ~(interrupt number) */
  366. .macro interrupt func
  367. cld
  368. ALLOC_PT_GPREGS_ON_STACK
  369. SAVE_C_REGS
  370. SAVE_EXTRA_REGS
  371. testb $3, CS(%rsp)
  372. jz 1f
  373. /*
  374. * IRQ from user mode. Switch to kernel gsbase and inform context
  375. * tracking that we're in kernel mode.
  376. */
  377. SWAPGS
  378. SWITCH_KERNEL_CR3
  379. /*
  380. * We need to tell lockdep that IRQs are off. We can't do this until
  381. * we fix gsbase, and we should do it before enter_from_user_mode
  382. * (which can take locks). Since TRACE_IRQS_OFF idempotent,
  383. * the simplest way to handle it is to just call it twice if
  384. * we enter from user mode. There's no reason to optimize this since
  385. * TRACE_IRQS_OFF is a no-op if lockdep is off.
  386. */
  387. TRACE_IRQS_OFF
  388. CALL_enter_from_user_mode
  389. 1:
  390. /*
  391. * Save previous stack pointer, optionally switch to interrupt stack.
  392. * irq_count is used to check if a CPU is already on an interrupt stack
  393. * or not. While this is essentially redundant with preempt_count it is
  394. * a little cheaper to use a separate counter in the PDA (short of
  395. * moving irq_enter into assembly, which would be too much work)
  396. */
  397. movq %rsp, %rdi
  398. incl PER_CPU_VAR(irq_count)
  399. cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp
  400. pushq %rdi
  401. /* We entered an interrupt context - irqs are off: */
  402. TRACE_IRQS_OFF
  403. call \func /* rdi points to pt_regs */
  404. .endm
  405. /*
  406. * The interrupt stubs push (~vector+0x80) onto the stack and
  407. * then jump to common_interrupt.
  408. */
  409. .p2align CONFIG_X86_L1_CACHE_SHIFT
  410. common_interrupt:
  411. ASM_CLAC
  412. addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */
  413. interrupt do_IRQ
  414. /* 0(%rsp): old RSP */
  415. ret_from_intr:
  416. DISABLE_INTERRUPTS(CLBR_NONE)
  417. TRACE_IRQS_OFF
  418. decl PER_CPU_VAR(irq_count)
  419. /* Restore saved previous stack */
  420. popq %rsp
  421. testb $3, CS(%rsp)
  422. jz retint_kernel
  423. /* Interrupt came from user space */
  424. GLOBAL(retint_user)
  425. mov %rsp,%rdi
  426. call prepare_exit_to_usermode
  427. TRACE_IRQS_IRETQ
  428. SWITCH_USER_CR3
  429. SWAPGS
  430. jmp restore_regs_and_iret
  431. /* Returning to kernel space */
  432. retint_kernel:
  433. #ifdef CONFIG_PREEMPT
  434. /* Interrupts are off */
  435. /* Check if we need preemption */
  436. bt $9, EFLAGS(%rsp) /* were interrupts off? */
  437. jnc 1f
  438. 0: cmpl $0, PER_CPU_VAR(__preempt_count)
  439. jnz 1f
  440. call preempt_schedule_irq
  441. jmp 0b
  442. 1:
  443. #endif
  444. /*
  445. * The iretq could re-enable interrupts:
  446. */
  447. TRACE_IRQS_IRETQ
  448. /*
  449. * At this label, code paths which return to kernel and to user,
  450. * which come from interrupts/exception and from syscalls, merge.
  451. */
  452. GLOBAL(restore_regs_and_iret)
  453. RESTORE_EXTRA_REGS
  454. restore_c_regs_and_iret:
  455. RESTORE_C_REGS
  456. REMOVE_PT_GPREGS_FROM_STACK 8
  457. INTERRUPT_RETURN
  458. ENTRY(native_iret)
  459. /*
  460. * Are we returning to a stack segment from the LDT? Note: in
  461. * 64-bit mode SS:RSP on the exception stack is always valid.
  462. */
  463. #ifdef CONFIG_X86_ESPFIX64
  464. testb $4, (SS-RIP)(%rsp)
  465. jnz native_irq_return_ldt
  466. #endif
  467. .global native_irq_return_iret
  468. native_irq_return_iret:
  469. /*
  470. * This may fault. Non-paranoid faults on return to userspace are
  471. * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
  472. * Double-faults due to espfix64 are handled in do_double_fault.
  473. * Other faults here are fatal.
  474. */
  475. iretq
  476. #ifdef CONFIG_X86_ESPFIX64
  477. native_irq_return_ldt:
  478. /*
  479. * We are running with user GSBASE. All GPRs contain their user
  480. * values. We have a percpu ESPFIX stack that is eight slots
  481. * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
  482. * of the ESPFIX stack.
  483. *
  484. * We clobber RAX and RDI in this code. We stash RDI on the
  485. * normal stack and RAX on the ESPFIX stack.
  486. *
  487. * The ESPFIX stack layout we set up looks like this:
  488. *
  489. * --- top of ESPFIX stack ---
  490. * SS
  491. * RSP
  492. * RFLAGS
  493. * CS
  494. * RIP <-- RSP points here when we're done
  495. * RAX <-- espfix_waddr points here
  496. * --- bottom of ESPFIX stack ---
  497. */
  498. pushq %rdi /* Stash user RDI */
  499. SWAPGS
  500. SWITCH_KERNEL_CR3
  501. movq PER_CPU_VAR(espfix_waddr), %rdi
  502. movq %rax, (0*8)(%rdi) /* user RAX */
  503. movq (1*8)(%rsp), %rax /* user RIP */
  504. movq %rax, (1*8)(%rdi)
  505. movq (2*8)(%rsp), %rax /* user CS */
  506. movq %rax, (2*8)(%rdi)
  507. movq (3*8)(%rsp), %rax /* user RFLAGS */
  508. movq %rax, (3*8)(%rdi)
  509. movq (5*8)(%rsp), %rax /* user SS */
  510. movq %rax, (5*8)(%rdi)
  511. movq (4*8)(%rsp), %rax /* user RSP */
  512. movq %rax, (4*8)(%rdi)
  513. /* Now RAX == RSP. */
  514. andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
  515. popq %rdi /* Restore user RDI */
  516. /*
  517. * espfix_stack[31:16] == 0. The page tables are set up such that
  518. * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
  519. * espfix_waddr for any X. That is, there are 65536 RO aliases of
  520. * the same page. Set up RSP so that RSP[31:16] contains the
  521. * respective 16 bits of the /userspace/ RSP and RSP nonetheless
  522. * still points to an RO alias of the ESPFIX stack.
  523. */
  524. orq PER_CPU_VAR(espfix_stack), %rax
  525. SWITCH_USER_CR3
  526. SWAPGS
  527. movq %rax, %rsp
  528. /*
  529. * At this point, we cannot write to the stack any more, but we can
  530. * still read.
  531. */
  532. popq %rax /* Restore user RAX */
  533. /*
  534. * RSP now points to an ordinary IRET frame, except that the page
  535. * is read-only and RSP[31:16] are preloaded with the userspace
  536. * values. We can now IRET back to userspace.
  537. */
  538. jmp native_irq_return_iret
  539. #endif
  540. END(common_interrupt)
  541. /*
  542. * APIC interrupts.
  543. */
  544. .macro apicinterrupt3 num sym do_sym
  545. ENTRY(\sym)
  546. ASM_CLAC
  547. pushq $~(\num)
  548. .Lcommon_\sym:
  549. interrupt \do_sym
  550. jmp ret_from_intr
  551. END(\sym)
  552. .endm
  553. #ifdef CONFIG_TRACING
  554. #define trace(sym) trace_##sym
  555. #define smp_trace(sym) smp_trace_##sym
  556. .macro trace_apicinterrupt num sym
  557. apicinterrupt3 \num trace(\sym) smp_trace(\sym)
  558. .endm
  559. #else
  560. .macro trace_apicinterrupt num sym do_sym
  561. .endm
  562. #endif
  563. /* Make sure APIC interrupt handlers end up in the irqentry section: */
  564. #if defined(CONFIG_FUNCTION_GRAPH_TRACER) || defined(CONFIG_KASAN)
  565. # define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax"
  566. # define POP_SECTION_IRQENTRY .popsection
  567. #else
  568. # define PUSH_SECTION_IRQENTRY
  569. # define POP_SECTION_IRQENTRY
  570. #endif
  571. .macro apicinterrupt num sym do_sym
  572. PUSH_SECTION_IRQENTRY
  573. apicinterrupt3 \num \sym \do_sym
  574. trace_apicinterrupt \num \sym
  575. POP_SECTION_IRQENTRY
  576. .endm
  577. #ifdef CONFIG_SMP
  578. apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt
  579. apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt
  580. #endif
  581. #ifdef CONFIG_X86_UV
  582. apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt
  583. #endif
  584. apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt
  585. apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi
  586. #ifdef CONFIG_HAVE_KVM
  587. apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi
  588. apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi
  589. #endif
  590. #ifdef CONFIG_X86_MCE_THRESHOLD
  591. apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt
  592. #endif
  593. #ifdef CONFIG_X86_MCE_AMD
  594. apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt
  595. #endif
  596. #ifdef CONFIG_X86_THERMAL_VECTOR
  597. apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt
  598. #endif
  599. #ifdef CONFIG_SMP
  600. apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt
  601. apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt
  602. apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt
  603. #endif
  604. apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt
  605. apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt
  606. #ifdef CONFIG_IRQ_WORK
  607. apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt
  608. #endif
  609. /*
  610. * Exception entry points.
  611. */
  612. #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss) + (TSS_ist + ((x) - 1) * 8)
  613. .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1
  614. ENTRY(\sym)
  615. /* Sanity check */
  616. .if \shift_ist != -1 && \paranoid == 0
  617. .error "using shift_ist requires paranoid=1"
  618. .endif
  619. ASM_CLAC
  620. PARAVIRT_ADJUST_EXCEPTION_FRAME
  621. .ifeq \has_error_code
  622. pushq $-1 /* ORIG_RAX: no syscall to restart */
  623. .endif
  624. ALLOC_PT_GPREGS_ON_STACK
  625. .if \paranoid
  626. .if \paranoid == 1
  627. testb $3, CS(%rsp) /* If coming from userspace, switch stacks */
  628. jnz 1f
  629. .endif
  630. call paranoid_entry
  631. .else
  632. call error_entry
  633. .endif
  634. /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */
  635. .if \paranoid
  636. .if \shift_ist != -1
  637. TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */
  638. .else
  639. TRACE_IRQS_OFF
  640. .endif
  641. .endif
  642. movq %rsp, %rdi /* pt_regs pointer */
  643. .if \has_error_code
  644. movq ORIG_RAX(%rsp), %rsi /* get error code */
  645. movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
  646. .else
  647. xorl %esi, %esi /* no error code */
  648. .endif
  649. .if \shift_ist != -1
  650. subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
  651. .endif
  652. call \do_sym
  653. .if \shift_ist != -1
  654. addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
  655. .endif
  656. /* these procedures expect "no swapgs" flag in ebx */
  657. .if \paranoid
  658. jmp paranoid_exit
  659. .else
  660. jmp error_exit
  661. .endif
  662. .if \paranoid == 1
  663. /*
  664. * Paranoid entry from userspace. Switch stacks and treat it
  665. * as a normal entry. This means that paranoid handlers
  666. * run in real process context if user_mode(regs).
  667. */
  668. 1:
  669. call error_entry
  670. movq %rsp, %rdi /* pt_regs pointer */
  671. call sync_regs
  672. movq %rax, %rsp /* switch stack */
  673. movq %rsp, %rdi /* pt_regs pointer */
  674. .if \has_error_code
  675. movq ORIG_RAX(%rsp), %rsi /* get error code */
  676. movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
  677. .else
  678. xorl %esi, %esi /* no error code */
  679. .endif
  680. call \do_sym
  681. jmp error_exit /* %ebx: no swapgs flag */
  682. .endif
  683. END(\sym)
  684. .endm
  685. #ifdef CONFIG_TRACING
  686. .macro trace_idtentry sym do_sym has_error_code:req
  687. idtentry trace(\sym) trace(\do_sym) has_error_code=\has_error_code
  688. idtentry \sym \do_sym has_error_code=\has_error_code
  689. .endm
  690. #else
  691. .macro trace_idtentry sym do_sym has_error_code:req
  692. idtentry \sym \do_sym has_error_code=\has_error_code
  693. .endm
  694. #endif
  695. idtentry divide_error do_divide_error has_error_code=0
  696. idtentry overflow do_overflow has_error_code=0
  697. idtentry bounds do_bounds has_error_code=0
  698. idtentry invalid_op do_invalid_op has_error_code=0
  699. idtentry device_not_available do_device_not_available has_error_code=0
  700. idtentry double_fault do_double_fault has_error_code=1 paranoid=2
  701. idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
  702. idtentry invalid_TSS do_invalid_TSS has_error_code=1
  703. idtentry segment_not_present do_segment_not_present has_error_code=1
  704. idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0
  705. idtentry coprocessor_error do_coprocessor_error has_error_code=0
  706. idtentry alignment_check do_alignment_check has_error_code=1
  707. idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0
  708. /*
  709. * Reload gs selector with exception handling
  710. * edi: new selector
  711. */
  712. ENTRY(native_load_gs_index)
  713. pushfq
  714. DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI)
  715. SWAPGS
  716. .Lgs_change:
  717. movl %edi, %gs
  718. 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
  719. SWAPGS
  720. popfq
  721. ret
  722. END(native_load_gs_index)
  723. EXPORT_SYMBOL(native_load_gs_index)
  724. _ASM_EXTABLE(.Lgs_change, bad_gs)
  725. .section .fixup, "ax"
  726. /* running with kernelgs */
  727. bad_gs:
  728. SWAPGS /* switch back to user gs */
  729. .macro ZAP_GS
  730. /* This can't be a string because the preprocessor needs to see it. */
  731. movl $__USER_DS, %eax
  732. movl %eax, %gs
  733. .endm
  734. ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
  735. xorl %eax, %eax
  736. movl %eax, %gs
  737. jmp 2b
  738. .previous
  739. /* Call softirq on interrupt stack. Interrupts are off. */
  740. ENTRY(do_softirq_own_stack)
  741. pushq %rbp
  742. mov %rsp, %rbp
  743. incl PER_CPU_VAR(irq_count)
  744. cmove PER_CPU_VAR(irq_stack_ptr), %rsp
  745. push %rbp /* frame pointer backlink */
  746. call __do_softirq
  747. leaveq
  748. decl PER_CPU_VAR(irq_count)
  749. ret
  750. END(do_softirq_own_stack)
  751. #ifdef CONFIG_XEN
  752. idtentry xen_hypervisor_callback xen_do_hypervisor_callback has_error_code=0
  753. /*
  754. * A note on the "critical region" in our callback handler.
  755. * We want to avoid stacking callback handlers due to events occurring
  756. * during handling of the last event. To do this, we keep events disabled
  757. * until we've done all processing. HOWEVER, we must enable events before
  758. * popping the stack frame (can't be done atomically) and so it would still
  759. * be possible to get enough handler activations to overflow the stack.
  760. * Although unlikely, bugs of that kind are hard to track down, so we'd
  761. * like to avoid the possibility.
  762. * So, on entry to the handler we detect whether we interrupted an
  763. * existing activation in its critical region -- if so, we pop the current
  764. * activation and restart the handler using the previous one.
  765. */
  766. ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */
  767. /*
  768. * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
  769. * see the correct pointer to the pt_regs
  770. */
  771. movq %rdi, %rsp /* we don't return, adjust the stack frame */
  772. 11: incl PER_CPU_VAR(irq_count)
  773. movq %rsp, %rbp
  774. cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp
  775. pushq %rbp /* frame pointer backlink */
  776. call xen_evtchn_do_upcall
  777. popq %rsp
  778. decl PER_CPU_VAR(irq_count)
  779. #ifndef CONFIG_PREEMPT
  780. call xen_maybe_preempt_hcall
  781. #endif
  782. jmp error_exit
  783. END(xen_do_hypervisor_callback)
  784. /*
  785. * Hypervisor uses this for application faults while it executes.
  786. * We get here for two reasons:
  787. * 1. Fault while reloading DS, ES, FS or GS
  788. * 2. Fault while executing IRET
  789. * Category 1 we do not need to fix up as Xen has already reloaded all segment
  790. * registers that could be reloaded and zeroed the others.
  791. * Category 2 we fix up by killing the current process. We cannot use the
  792. * normal Linux return path in this case because if we use the IRET hypercall
  793. * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
  794. * We distinguish between categories by comparing each saved segment register
  795. * with its current contents: any discrepancy means we in category 1.
  796. */
  797. ENTRY(xen_failsafe_callback)
  798. movl %ds, %ecx
  799. cmpw %cx, 0x10(%rsp)
  800. jne 1f
  801. movl %es, %ecx
  802. cmpw %cx, 0x18(%rsp)
  803. jne 1f
  804. movl %fs, %ecx
  805. cmpw %cx, 0x20(%rsp)
  806. jne 1f
  807. movl %gs, %ecx
  808. cmpw %cx, 0x28(%rsp)
  809. jne 1f
  810. /* All segments match their saved values => Category 2 (Bad IRET). */
  811. movq (%rsp), %rcx
  812. movq 8(%rsp), %r11
  813. addq $0x30, %rsp
  814. pushq $0 /* RIP */
  815. pushq %r11
  816. pushq %rcx
  817. jmp general_protection
  818. 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
  819. movq (%rsp), %rcx
  820. movq 8(%rsp), %r11
  821. addq $0x30, %rsp
  822. pushq $-1 /* orig_ax = -1 => not a system call */
  823. ALLOC_PT_GPREGS_ON_STACK
  824. SAVE_C_REGS
  825. SAVE_EXTRA_REGS
  826. jmp error_exit
  827. END(xen_failsafe_callback)
  828. apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
  829. xen_hvm_callback_vector xen_evtchn_do_upcall
  830. #endif /* CONFIG_XEN */
  831. #if IS_ENABLED(CONFIG_HYPERV)
  832. apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
  833. hyperv_callback_vector hyperv_vector_handler
  834. #endif /* CONFIG_HYPERV */
  835. idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
  836. idtentry int3 do_int3 has_error_code=0
  837. idtentry stack_segment do_stack_segment has_error_code=1
  838. #ifdef CONFIG_XEN
  839. idtentry xen_debug do_debug has_error_code=0
  840. idtentry xen_int3 do_int3 has_error_code=0
  841. idtentry xen_stack_segment do_stack_segment has_error_code=1
  842. #endif
  843. idtentry general_protection do_general_protection has_error_code=1
  844. trace_idtentry page_fault do_page_fault has_error_code=1
  845. #ifdef CONFIG_KVM_GUEST
  846. idtentry async_page_fault do_async_page_fault has_error_code=1
  847. #endif
  848. #ifdef CONFIG_X86_MCE
  849. idtentry machine_check do_mce has_error_code=0 paranoid=1
  850. #endif
  851. /*
  852. * Save all registers in pt_regs, and switch gs if needed.
  853. * Use slow, but surefire "are we in kernel?" check.
  854. *
  855. * Return: ebx=0: needs swapgs but not SWITCH_USER_CR3 in paranoid_exit
  856. * ebx=1: needs neither swapgs nor SWITCH_USER_CR3 in paranoid_exit
  857. * ebx=2: needs both swapgs and SWITCH_USER_CR3 in paranoid_exit
  858. * ebx=3: needs SWITCH_USER_CR3 but not swapgs in paranoid_exit
  859. */
  860. ENTRY(paranoid_entry)
  861. cld
  862. SAVE_C_REGS 8
  863. SAVE_EXTRA_REGS 8
  864. movl $1, %ebx
  865. movl $MSR_GS_BASE, %ecx
  866. rdmsr
  867. testl %edx, %edx
  868. js 1f /* negative -> in kernel */
  869. SWAPGS
  870. xorl %ebx, %ebx
  871. 1:
  872. #ifdef CONFIG_PAGE_TABLE_ISOLATION
  873. /*
  874. * We might have come in between a swapgs and a SWITCH_KERNEL_CR3
  875. * on entry, or between a SWITCH_USER_CR3 and a swapgs on exit.
  876. * Do a conditional SWITCH_KERNEL_CR3: this could safely be done
  877. * unconditionally, but we need to find out whether the reverse
  878. * should be done on return (conveyed to paranoid_exit in %ebx).
  879. */
  880. ALTERNATIVE "jmp 2f", "movq %cr3, %rax", X86_FEATURE_KAISER
  881. testl $KAISER_SHADOW_PGD_OFFSET, %eax
  882. jz 2f
  883. orl $2, %ebx
  884. andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax
  885. /* If PCID enabled, set X86_CR3_PCID_NOFLUSH_BIT */
  886. ALTERNATIVE "", "bts $63, %rax", X86_FEATURE_PCID
  887. movq %rax, %cr3
  888. 2:
  889. #endif
  890. ret
  891. END(paranoid_entry)
  892. /*
  893. * "Paranoid" exit path from exception stack. This is invoked
  894. * only on return from non-NMI IST interrupts that came
  895. * from kernel space.
  896. *
  897. * We may be returning to very strange contexts (e.g. very early
  898. * in syscall entry), so checking for preemption here would
  899. * be complicated. Fortunately, we there's no good reason
  900. * to try to handle preemption here.
  901. *
  902. * On entry: ebx=0: needs swapgs but not SWITCH_USER_CR3
  903. * ebx=1: needs neither swapgs nor SWITCH_USER_CR3
  904. * ebx=2: needs both swapgs and SWITCH_USER_CR3
  905. * ebx=3: needs SWITCH_USER_CR3 but not swapgs
  906. */
  907. ENTRY(paranoid_exit)
  908. DISABLE_INTERRUPTS(CLBR_NONE)
  909. TRACE_IRQS_OFF_DEBUG
  910. TRACE_IRQS_IRETQ_DEBUG
  911. #ifdef CONFIG_PAGE_TABLE_ISOLATION
  912. /* No ALTERNATIVE for X86_FEATURE_KAISER: paranoid_entry sets %ebx */
  913. testl $2, %ebx /* SWITCH_USER_CR3 needed? */
  914. jz paranoid_exit_no_switch
  915. SWITCH_USER_CR3
  916. paranoid_exit_no_switch:
  917. #endif
  918. testl $1, %ebx /* swapgs needed? */
  919. jnz paranoid_exit_no_swapgs
  920. SWAPGS_UNSAFE_STACK
  921. paranoid_exit_no_swapgs:
  922. RESTORE_EXTRA_REGS
  923. RESTORE_C_REGS
  924. REMOVE_PT_GPREGS_FROM_STACK 8
  925. INTERRUPT_RETURN
  926. END(paranoid_exit)
  927. /*
  928. * Save all registers in pt_regs, and switch gs if needed.
  929. * Return: EBX=0: came from user mode; EBX=1: otherwise
  930. */
  931. ENTRY(error_entry)
  932. cld
  933. SAVE_C_REGS 8
  934. SAVE_EXTRA_REGS 8
  935. /*
  936. * error_entry() always returns with a kernel gsbase and
  937. * CR3. We must also have a kernel CR3/gsbase before
  938. * calling TRACE_IRQS_*. Just unconditionally switch to
  939. * the kernel CR3 here.
  940. */
  941. SWITCH_KERNEL_CR3
  942. xorl %ebx, %ebx
  943. testb $3, CS+8(%rsp)
  944. jz .Lerror_kernelspace
  945. /*
  946. * We entered from user mode or we're pretending to have entered
  947. * from user mode due to an IRET fault.
  948. */
  949. SWAPGS
  950. .Lerror_entry_from_usermode_after_swapgs:
  951. /*
  952. * We need to tell lockdep that IRQs are off. We can't do this until
  953. * we fix gsbase, and we should do it before enter_from_user_mode
  954. * (which can take locks).
  955. */
  956. TRACE_IRQS_OFF
  957. CALL_enter_from_user_mode
  958. ret
  959. .Lerror_entry_done:
  960. TRACE_IRQS_OFF
  961. ret
  962. /*
  963. * There are two places in the kernel that can potentially fault with
  964. * usergs. Handle them here. B stepping K8s sometimes report a
  965. * truncated RIP for IRET exceptions returning to compat mode. Check
  966. * for these here too.
  967. */
  968. .Lerror_kernelspace:
  969. incl %ebx
  970. leaq native_irq_return_iret(%rip), %rcx
  971. cmpq %rcx, RIP+8(%rsp)
  972. je .Lerror_bad_iret
  973. movl %ecx, %eax /* zero extend */
  974. cmpq %rax, RIP+8(%rsp)
  975. je .Lbstep_iret
  976. cmpq $.Lgs_change, RIP+8(%rsp)
  977. jne .Lerror_entry_done
  978. /*
  979. * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
  980. * gsbase and proceed. We'll fix up the exception and land in
  981. * .Lgs_change's error handler with kernel gsbase.
  982. */
  983. SWAPGS
  984. jmp .Lerror_entry_done
  985. .Lbstep_iret:
  986. /* Fix truncated RIP */
  987. movq %rcx, RIP+8(%rsp)
  988. /* fall through */
  989. .Lerror_bad_iret:
  990. /*
  991. * We came from an IRET to user mode, so we have user gsbase.
  992. * Switch to kernel gsbase:
  993. */
  994. SWAPGS
  995. /*
  996. * Pretend that the exception came from user mode: set up pt_regs
  997. * as if we faulted immediately after IRET and clear EBX so that
  998. * error_exit knows that we will be returning to user mode.
  999. */
  1000. mov %rsp, %rdi
  1001. call fixup_bad_iret
  1002. mov %rax, %rsp
  1003. decl %ebx
  1004. jmp .Lerror_entry_from_usermode_after_swapgs
  1005. END(error_entry)
  1006. /*
  1007. * On entry, EBX is a "return to kernel mode" flag:
  1008. * 1: already in kernel mode, don't need SWAPGS
  1009. * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode
  1010. */
  1011. ENTRY(error_exit)
  1012. movl %ebx, %eax
  1013. DISABLE_INTERRUPTS(CLBR_NONE)
  1014. TRACE_IRQS_OFF
  1015. testl %eax, %eax
  1016. jnz retint_kernel
  1017. jmp retint_user
  1018. END(error_exit)
  1019. /* Runs on exception stack */
  1020. ENTRY(nmi)
  1021. /*
  1022. * Fix up the exception frame if we're on Xen.
  1023. * PARAVIRT_ADJUST_EXCEPTION_FRAME is guaranteed to push at most
  1024. * one value to the stack on native, so it may clobber the rdx
  1025. * scratch slot, but it won't clobber any of the important
  1026. * slots past it.
  1027. *
  1028. * Xen is a different story, because the Xen frame itself overlaps
  1029. * the "NMI executing" variable.
  1030. */
  1031. PARAVIRT_ADJUST_EXCEPTION_FRAME
  1032. /*
  1033. * We allow breakpoints in NMIs. If a breakpoint occurs, then
  1034. * the iretq it performs will take us out of NMI context.
  1035. * This means that we can have nested NMIs where the next
  1036. * NMI is using the top of the stack of the previous NMI. We
  1037. * can't let it execute because the nested NMI will corrupt the
  1038. * stack of the previous NMI. NMI handlers are not re-entrant
  1039. * anyway.
  1040. *
  1041. * To handle this case we do the following:
  1042. * Check the a special location on the stack that contains
  1043. * a variable that is set when NMIs are executing.
  1044. * The interrupted task's stack is also checked to see if it
  1045. * is an NMI stack.
  1046. * If the variable is not set and the stack is not the NMI
  1047. * stack then:
  1048. * o Set the special variable on the stack
  1049. * o Copy the interrupt frame into an "outermost" location on the
  1050. * stack
  1051. * o Copy the interrupt frame into an "iret" location on the stack
  1052. * o Continue processing the NMI
  1053. * If the variable is set or the previous stack is the NMI stack:
  1054. * o Modify the "iret" location to jump to the repeat_nmi
  1055. * o return back to the first NMI
  1056. *
  1057. * Now on exit of the first NMI, we first clear the stack variable
  1058. * The NMI stack will tell any nested NMIs at that point that it is
  1059. * nested. Then we pop the stack normally with iret, and if there was
  1060. * a nested NMI that updated the copy interrupt stack frame, a
  1061. * jump will be made to the repeat_nmi code that will handle the second
  1062. * NMI.
  1063. *
  1064. * However, espfix prevents us from directly returning to userspace
  1065. * with a single IRET instruction. Similarly, IRET to user mode
  1066. * can fault. We therefore handle NMIs from user space like
  1067. * other IST entries.
  1068. */
  1069. ASM_CLAC
  1070. /* Use %rdx as our temp variable throughout */
  1071. pushq %rdx
  1072. testb $3, CS-RIP+8(%rsp)
  1073. jz .Lnmi_from_kernel
  1074. /*
  1075. * NMI from user mode. We need to run on the thread stack, but we
  1076. * can't go through the normal entry paths: NMIs are masked, and
  1077. * we don't want to enable interrupts, because then we'll end
  1078. * up in an awkward situation in which IRQs are on but NMIs
  1079. * are off.
  1080. *
  1081. * We also must not push anything to the stack before switching
  1082. * stacks lest we corrupt the "NMI executing" variable.
  1083. */
  1084. SWAPGS_UNSAFE_STACK
  1085. /*
  1086. * percpu variables are mapped with user CR3, so no need
  1087. * to switch CR3 here.
  1088. */
  1089. cld
  1090. movq %rsp, %rdx
  1091. movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
  1092. pushq 5*8(%rdx) /* pt_regs->ss */
  1093. pushq 4*8(%rdx) /* pt_regs->rsp */
  1094. pushq 3*8(%rdx) /* pt_regs->flags */
  1095. pushq 2*8(%rdx) /* pt_regs->cs */
  1096. pushq 1*8(%rdx) /* pt_regs->rip */
  1097. pushq $-1 /* pt_regs->orig_ax */
  1098. pushq %rdi /* pt_regs->di */
  1099. pushq %rsi /* pt_regs->si */
  1100. pushq (%rdx) /* pt_regs->dx */
  1101. pushq %rcx /* pt_regs->cx */
  1102. pushq %rax /* pt_regs->ax */
  1103. pushq %r8 /* pt_regs->r8 */
  1104. pushq %r9 /* pt_regs->r9 */
  1105. pushq %r10 /* pt_regs->r10 */
  1106. pushq %r11 /* pt_regs->r11 */
  1107. pushq %rbx /* pt_regs->rbx */
  1108. pushq %rbp /* pt_regs->rbp */
  1109. pushq %r12 /* pt_regs->r12 */
  1110. pushq %r13 /* pt_regs->r13 */
  1111. pushq %r14 /* pt_regs->r14 */
  1112. pushq %r15 /* pt_regs->r15 */
  1113. /*
  1114. * At this point we no longer need to worry about stack damage
  1115. * due to nesting -- we're on the normal thread stack and we're
  1116. * done with the NMI stack.
  1117. */
  1118. movq %rsp, %rdi
  1119. movq $-1, %rsi
  1120. #ifdef CONFIG_PAGE_TABLE_ISOLATION
  1121. /* Unconditionally use kernel CR3 for do_nmi() */
  1122. /* %rax is saved above, so OK to clobber here */
  1123. ALTERNATIVE "jmp 2f", "movq %cr3, %rax", X86_FEATURE_KAISER
  1124. /* If PCID enabled, NOFLUSH now and NOFLUSH on return */
  1125. ALTERNATIVE "", "bts $63, %rax", X86_FEATURE_PCID
  1126. pushq %rax
  1127. /* mask off "user" bit of pgd address and 12 PCID bits: */
  1128. andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax
  1129. movq %rax, %cr3
  1130. 2:
  1131. #endif
  1132. call do_nmi
  1133. #ifdef CONFIG_PAGE_TABLE_ISOLATION
  1134. /*
  1135. * Unconditionally restore CR3. I know we return to
  1136. * kernel code that needs user CR3, but do we ever return
  1137. * to "user mode" where we need the kernel CR3?
  1138. */
  1139. ALTERNATIVE "", "popq %rax; movq %rax, %cr3", X86_FEATURE_KAISER
  1140. #endif
  1141. /*
  1142. * Return back to user mode. We must *not* do the normal exit
  1143. * work, because we don't want to enable interrupts. Do not
  1144. * switch to user CR3: we might be going back to kernel code
  1145. * that had a user CR3 set.
  1146. */
  1147. SWAPGS
  1148. jmp restore_c_regs_and_iret
  1149. .Lnmi_from_kernel:
  1150. /*
  1151. * Here's what our stack frame will look like:
  1152. * +---------------------------------------------------------+
  1153. * | original SS |
  1154. * | original Return RSP |
  1155. * | original RFLAGS |
  1156. * | original CS |
  1157. * | original RIP |
  1158. * +---------------------------------------------------------+
  1159. * | temp storage for rdx |
  1160. * +---------------------------------------------------------+
  1161. * | "NMI executing" variable |
  1162. * +---------------------------------------------------------+
  1163. * | iret SS } Copied from "outermost" frame |
  1164. * | iret Return RSP } on each loop iteration; overwritten |
  1165. * | iret RFLAGS } by a nested NMI to force another |
  1166. * | iret CS } iteration if needed. |
  1167. * | iret RIP } |
  1168. * +---------------------------------------------------------+
  1169. * | outermost SS } initialized in first_nmi; |
  1170. * | outermost Return RSP } will not be changed before |
  1171. * | outermost RFLAGS } NMI processing is done. |
  1172. * | outermost CS } Copied to "iret" frame on each |
  1173. * | outermost RIP } iteration. |
  1174. * +---------------------------------------------------------+
  1175. * | pt_regs |
  1176. * +---------------------------------------------------------+
  1177. *
  1178. * The "original" frame is used by hardware. Before re-enabling
  1179. * NMIs, we need to be done with it, and we need to leave enough
  1180. * space for the asm code here.
  1181. *
  1182. * We return by executing IRET while RSP points to the "iret" frame.
  1183. * That will either return for real or it will loop back into NMI
  1184. * processing.
  1185. *
  1186. * The "outermost" frame is copied to the "iret" frame on each
  1187. * iteration of the loop, so each iteration starts with the "iret"
  1188. * frame pointing to the final return target.
  1189. */
  1190. /*
  1191. * Determine whether we're a nested NMI.
  1192. *
  1193. * If we interrupted kernel code between repeat_nmi and
  1194. * end_repeat_nmi, then we are a nested NMI. We must not
  1195. * modify the "iret" frame because it's being written by
  1196. * the outer NMI. That's okay; the outer NMI handler is
  1197. * about to about to call do_nmi anyway, so we can just
  1198. * resume the outer NMI.
  1199. */
  1200. movq $repeat_nmi, %rdx
  1201. cmpq 8(%rsp), %rdx
  1202. ja 1f
  1203. movq $end_repeat_nmi, %rdx
  1204. cmpq 8(%rsp), %rdx
  1205. ja nested_nmi_out
  1206. 1:
  1207. /*
  1208. * Now check "NMI executing". If it's set, then we're nested.
  1209. * This will not detect if we interrupted an outer NMI just
  1210. * before IRET.
  1211. */
  1212. cmpl $1, -8(%rsp)
  1213. je nested_nmi
  1214. /*
  1215. * Now test if the previous stack was an NMI stack. This covers
  1216. * the case where we interrupt an outer NMI after it clears
  1217. * "NMI executing" but before IRET. We need to be careful, though:
  1218. * there is one case in which RSP could point to the NMI stack
  1219. * despite there being no NMI active: naughty userspace controls
  1220. * RSP at the very beginning of the SYSCALL targets. We can
  1221. * pull a fast one on naughty userspace, though: we program
  1222. * SYSCALL to mask DF, so userspace cannot cause DF to be set
  1223. * if it controls the kernel's RSP. We set DF before we clear
  1224. * "NMI executing".
  1225. */
  1226. lea 6*8(%rsp), %rdx
  1227. /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
  1228. cmpq %rdx, 4*8(%rsp)
  1229. /* If the stack pointer is above the NMI stack, this is a normal NMI */
  1230. ja first_nmi
  1231. subq $EXCEPTION_STKSZ, %rdx
  1232. cmpq %rdx, 4*8(%rsp)
  1233. /* If it is below the NMI stack, it is a normal NMI */
  1234. jb first_nmi
  1235. /* Ah, it is within the NMI stack. */
  1236. testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
  1237. jz first_nmi /* RSP was user controlled. */
  1238. /* This is a nested NMI. */
  1239. nested_nmi:
  1240. /*
  1241. * Modify the "iret" frame to point to repeat_nmi, forcing another
  1242. * iteration of NMI handling.
  1243. */
  1244. subq $8, %rsp
  1245. leaq -10*8(%rsp), %rdx
  1246. pushq $__KERNEL_DS
  1247. pushq %rdx
  1248. pushfq
  1249. pushq $__KERNEL_CS
  1250. pushq $repeat_nmi
  1251. /* Put stack back */
  1252. addq $(6*8), %rsp
  1253. nested_nmi_out:
  1254. popq %rdx
  1255. /* We are returning to kernel mode, so this cannot result in a fault. */
  1256. INTERRUPT_RETURN
  1257. first_nmi:
  1258. /* Restore rdx. */
  1259. movq (%rsp), %rdx
  1260. /* Make room for "NMI executing". */
  1261. pushq $0
  1262. /* Leave room for the "iret" frame */
  1263. subq $(5*8), %rsp
  1264. /* Copy the "original" frame to the "outermost" frame */
  1265. .rept 5
  1266. pushq 11*8(%rsp)
  1267. .endr
  1268. /* Everything up to here is safe from nested NMIs */
  1269. #ifdef CONFIG_DEBUG_ENTRY
  1270. /*
  1271. * For ease of testing, unmask NMIs right away. Disabled by
  1272. * default because IRET is very expensive.
  1273. */
  1274. pushq $0 /* SS */
  1275. pushq %rsp /* RSP (minus 8 because of the previous push) */
  1276. addq $8, (%rsp) /* Fix up RSP */
  1277. pushfq /* RFLAGS */
  1278. pushq $__KERNEL_CS /* CS */
  1279. pushq $1f /* RIP */
  1280. INTERRUPT_RETURN /* continues at repeat_nmi below */
  1281. 1:
  1282. #endif
  1283. repeat_nmi:
  1284. /*
  1285. * If there was a nested NMI, the first NMI's iret will return
  1286. * here. But NMIs are still enabled and we can take another
  1287. * nested NMI. The nested NMI checks the interrupted RIP to see
  1288. * if it is between repeat_nmi and end_repeat_nmi, and if so
  1289. * it will just return, as we are about to repeat an NMI anyway.
  1290. * This makes it safe to copy to the stack frame that a nested
  1291. * NMI will update.
  1292. *
  1293. * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
  1294. * we're repeating an NMI, gsbase has the same value that it had on
  1295. * the first iteration. paranoid_entry will load the kernel
  1296. * gsbase if needed before we call do_nmi. "NMI executing"
  1297. * is zero.
  1298. */
  1299. movq $1, 10*8(%rsp) /* Set "NMI executing". */
  1300. /*
  1301. * Copy the "outermost" frame to the "iret" frame. NMIs that nest
  1302. * here must not modify the "iret" frame while we're writing to
  1303. * it or it will end up containing garbage.
  1304. */
  1305. addq $(10*8), %rsp
  1306. .rept 5
  1307. pushq -6*8(%rsp)
  1308. .endr
  1309. subq $(5*8), %rsp
  1310. end_repeat_nmi:
  1311. /*
  1312. * Everything below this point can be preempted by a nested NMI.
  1313. * If this happens, then the inner NMI will change the "iret"
  1314. * frame to point back to repeat_nmi.
  1315. */
  1316. pushq $-1 /* ORIG_RAX: no syscall to restart */
  1317. ALLOC_PT_GPREGS_ON_STACK
  1318. /*
  1319. * Use the same approach as paranoid_entry to handle SWAPGS, but
  1320. * without CR3 handling since we do that differently in NMIs. No
  1321. * need to use paranoid_exit as we should not be calling schedule
  1322. * in NMI context. Even with normal interrupts enabled. An NMI
  1323. * should not be setting NEED_RESCHED or anything that normal
  1324. * interrupts and exceptions might do.
  1325. */
  1326. cld
  1327. SAVE_C_REGS
  1328. SAVE_EXTRA_REGS
  1329. movl $1, %ebx
  1330. movl $MSR_GS_BASE, %ecx
  1331. rdmsr
  1332. testl %edx, %edx
  1333. js 1f /* negative -> in kernel */
  1334. SWAPGS
  1335. xorl %ebx, %ebx
  1336. 1:
  1337. movq %rsp, %rdi
  1338. movq $-1, %rsi
  1339. #ifdef CONFIG_PAGE_TABLE_ISOLATION
  1340. /* Unconditionally use kernel CR3 for do_nmi() */
  1341. /* %rax is saved above, so OK to clobber here */
  1342. ALTERNATIVE "jmp 2f", "movq %cr3, %rax", X86_FEATURE_KAISER
  1343. /* If PCID enabled, NOFLUSH now and NOFLUSH on return */
  1344. ALTERNATIVE "", "bts $63, %rax", X86_FEATURE_PCID
  1345. pushq %rax
  1346. /* mask off "user" bit of pgd address and 12 PCID bits: */
  1347. andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax
  1348. movq %rax, %cr3
  1349. 2:
  1350. #endif
  1351. /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */
  1352. call do_nmi
  1353. #ifdef CONFIG_PAGE_TABLE_ISOLATION
  1354. /*
  1355. * Unconditionally restore CR3. We might be returning to
  1356. * kernel code that needs user CR3, like just just before
  1357. * a sysret.
  1358. */
  1359. ALTERNATIVE "", "popq %rax; movq %rax, %cr3", X86_FEATURE_KAISER
  1360. #endif
  1361. testl %ebx, %ebx /* swapgs needed? */
  1362. jnz nmi_restore
  1363. nmi_swapgs:
  1364. /* We fixed up CR3 above, so no need to switch it here */
  1365. SWAPGS_UNSAFE_STACK
  1366. nmi_restore:
  1367. RESTORE_EXTRA_REGS
  1368. RESTORE_C_REGS
  1369. /* Point RSP at the "iret" frame. */
  1370. REMOVE_PT_GPREGS_FROM_STACK 6*8
  1371. /*
  1372. * Clear "NMI executing". Set DF first so that we can easily
  1373. * distinguish the remaining code between here and IRET from
  1374. * the SYSCALL entry and exit paths. On a native kernel, we
  1375. * could just inspect RIP, but, on paravirt kernels,
  1376. * INTERRUPT_RETURN can translate into a jump into a
  1377. * hypercall page.
  1378. */
  1379. std
  1380. movq $0, 5*8(%rsp) /* clear "NMI executing" */
  1381. /*
  1382. * INTERRUPT_RETURN reads the "iret" frame and exits the NMI
  1383. * stack in a single instruction. We are returning to kernel
  1384. * mode, so this cannot result in a fault.
  1385. */
  1386. INTERRUPT_RETURN
  1387. END(nmi)
  1388. ENTRY(ignore_sysret)
  1389. mov $-ENOSYS, %eax
  1390. sysret
  1391. END(ignore_sysret)
  1392. ENTRY(rewind_stack_do_exit)
  1393. /* Prevent any naive code from trying to unwind to our caller. */
  1394. xorl %ebp, %ebp
  1395. movq PER_CPU_VAR(cpu_current_top_of_stack), %rax
  1396. leaq -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%rax), %rsp
  1397. call do_exit
  1398. 1: jmp 1b
  1399. END(rewind_stack_do_exit)