aesni-intel_glue.c 42 KB

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  1. /*
  2. * Support for Intel AES-NI instructions. This file contains glue
  3. * code, the real AES implementation is in intel-aes_asm.S.
  4. *
  5. * Copyright (C) 2008, Intel Corp.
  6. * Author: Huang Ying <ying.huang@intel.com>
  7. *
  8. * Added RFC4106 AES-GCM support for 128-bit keys under the AEAD
  9. * interface for 64-bit kernels.
  10. * Authors: Adrian Hoban <adrian.hoban@intel.com>
  11. * Gabriele Paoloni <gabriele.paoloni@intel.com>
  12. * Tadeusz Struk (tadeusz.struk@intel.com)
  13. * Aidan O'Mahony (aidan.o.mahony@intel.com)
  14. * Copyright (c) 2010, Intel Corporation.
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License as published by
  18. * the Free Software Foundation; either version 2 of the License, or
  19. * (at your option) any later version.
  20. */
  21. #include <linux/hardirq.h>
  22. #include <linux/types.h>
  23. #include <linux/crypto.h>
  24. #include <linux/module.h>
  25. #include <linux/err.h>
  26. #include <crypto/algapi.h>
  27. #include <crypto/aes.h>
  28. #include <crypto/cryptd.h>
  29. #include <crypto/ctr.h>
  30. #include <crypto/b128ops.h>
  31. #include <crypto/lrw.h>
  32. #include <crypto/xts.h>
  33. #include <asm/cpu_device_id.h>
  34. #include <asm/fpu/api.h>
  35. #include <asm/crypto/aes.h>
  36. #include <crypto/ablk_helper.h>
  37. #include <crypto/scatterwalk.h>
  38. #include <crypto/internal/aead.h>
  39. #include <linux/workqueue.h>
  40. #include <linux/spinlock.h>
  41. #ifdef CONFIG_X86_64
  42. #include <asm/crypto/glue_helper.h>
  43. #endif
  44. #define AESNI_ALIGN 16
  45. #define AES_BLOCK_MASK (~(AES_BLOCK_SIZE - 1))
  46. #define RFC4106_HASH_SUBKEY_SIZE 16
  47. /* This data is stored at the end of the crypto_tfm struct.
  48. * It's a type of per "session" data storage location.
  49. * This needs to be 16 byte aligned.
  50. */
  51. struct aesni_rfc4106_gcm_ctx {
  52. u8 hash_subkey[16] __attribute__ ((__aligned__(AESNI_ALIGN)));
  53. struct crypto_aes_ctx aes_key_expanded
  54. __attribute__ ((__aligned__(AESNI_ALIGN)));
  55. u8 nonce[4];
  56. };
  57. struct aesni_lrw_ctx {
  58. struct lrw_table_ctx lrw_table;
  59. u8 raw_aes_ctx[sizeof(struct crypto_aes_ctx) + AESNI_ALIGN - 1];
  60. };
  61. struct aesni_xts_ctx {
  62. u8 raw_tweak_ctx[sizeof(struct crypto_aes_ctx) + AESNI_ALIGN - 1];
  63. u8 raw_crypt_ctx[sizeof(struct crypto_aes_ctx) + AESNI_ALIGN - 1];
  64. };
  65. asmlinkage int aesni_set_key(struct crypto_aes_ctx *ctx, const u8 *in_key,
  66. unsigned int key_len);
  67. asmlinkage void aesni_enc(struct crypto_aes_ctx *ctx, u8 *out,
  68. const u8 *in);
  69. asmlinkage void aesni_dec(struct crypto_aes_ctx *ctx, u8 *out,
  70. const u8 *in);
  71. asmlinkage void aesni_ecb_enc(struct crypto_aes_ctx *ctx, u8 *out,
  72. const u8 *in, unsigned int len);
  73. asmlinkage void aesni_ecb_dec(struct crypto_aes_ctx *ctx, u8 *out,
  74. const u8 *in, unsigned int len);
  75. asmlinkage void aesni_cbc_enc(struct crypto_aes_ctx *ctx, u8 *out,
  76. const u8 *in, unsigned int len, u8 *iv);
  77. asmlinkage void aesni_cbc_dec(struct crypto_aes_ctx *ctx, u8 *out,
  78. const u8 *in, unsigned int len, u8 *iv);
  79. int crypto_fpu_init(void);
  80. void crypto_fpu_exit(void);
  81. #define AVX_GEN2_OPTSIZE 640
  82. #define AVX_GEN4_OPTSIZE 4096
  83. #ifdef CONFIG_X86_64
  84. static void (*aesni_ctr_enc_tfm)(struct crypto_aes_ctx *ctx, u8 *out,
  85. const u8 *in, unsigned int len, u8 *iv);
  86. asmlinkage void aesni_ctr_enc(struct crypto_aes_ctx *ctx, u8 *out,
  87. const u8 *in, unsigned int len, u8 *iv);
  88. asmlinkage void aesni_xts_crypt8(struct crypto_aes_ctx *ctx, u8 *out,
  89. const u8 *in, bool enc, u8 *iv);
  90. /* asmlinkage void aesni_gcm_enc()
  91. * void *ctx, AES Key schedule. Starts on a 16 byte boundary.
  92. * u8 *out, Ciphertext output. Encrypt in-place is allowed.
  93. * const u8 *in, Plaintext input
  94. * unsigned long plaintext_len, Length of data in bytes for encryption.
  95. * u8 *iv, Pre-counter block j0: 4 byte salt (from Security Association)
  96. * concatenated with 8 byte Initialisation Vector (from IPSec ESP
  97. * Payload) concatenated with 0x00000001. 16-byte aligned pointer.
  98. * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary.
  99. * const u8 *aad, Additional Authentication Data (AAD)
  100. * unsigned long aad_len, Length of AAD in bytes. With RFC4106 this
  101. * is going to be 8 or 12 bytes
  102. * u8 *auth_tag, Authenticated Tag output.
  103. * unsigned long auth_tag_len), Authenticated Tag Length in bytes.
  104. * Valid values are 16 (most likely), 12 or 8.
  105. */
  106. asmlinkage void aesni_gcm_enc(void *ctx, u8 *out,
  107. const u8 *in, unsigned long plaintext_len, u8 *iv,
  108. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  109. u8 *auth_tag, unsigned long auth_tag_len);
  110. /* asmlinkage void aesni_gcm_dec()
  111. * void *ctx, AES Key schedule. Starts on a 16 byte boundary.
  112. * u8 *out, Plaintext output. Decrypt in-place is allowed.
  113. * const u8 *in, Ciphertext input
  114. * unsigned long ciphertext_len, Length of data in bytes for decryption.
  115. * u8 *iv, Pre-counter block j0: 4 byte salt (from Security Association)
  116. * concatenated with 8 byte Initialisation Vector (from IPSec ESP
  117. * Payload) concatenated with 0x00000001. 16-byte aligned pointer.
  118. * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary.
  119. * const u8 *aad, Additional Authentication Data (AAD)
  120. * unsigned long aad_len, Length of AAD in bytes. With RFC4106 this is going
  121. * to be 8 or 12 bytes
  122. * u8 *auth_tag, Authenticated Tag output.
  123. * unsigned long auth_tag_len) Authenticated Tag Length in bytes.
  124. * Valid values are 16 (most likely), 12 or 8.
  125. */
  126. asmlinkage void aesni_gcm_dec(void *ctx, u8 *out,
  127. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  128. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  129. u8 *auth_tag, unsigned long auth_tag_len);
  130. #ifdef CONFIG_AS_AVX
  131. asmlinkage void aes_ctr_enc_128_avx_by8(const u8 *in, u8 *iv,
  132. void *keys, u8 *out, unsigned int num_bytes);
  133. asmlinkage void aes_ctr_enc_192_avx_by8(const u8 *in, u8 *iv,
  134. void *keys, u8 *out, unsigned int num_bytes);
  135. asmlinkage void aes_ctr_enc_256_avx_by8(const u8 *in, u8 *iv,
  136. void *keys, u8 *out, unsigned int num_bytes);
  137. /*
  138. * asmlinkage void aesni_gcm_precomp_avx_gen2()
  139. * gcm_data *my_ctx_data, context data
  140. * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary.
  141. */
  142. asmlinkage void aesni_gcm_precomp_avx_gen2(void *my_ctx_data, u8 *hash_subkey);
  143. asmlinkage void aesni_gcm_enc_avx_gen2(void *ctx, u8 *out,
  144. const u8 *in, unsigned long plaintext_len, u8 *iv,
  145. const u8 *aad, unsigned long aad_len,
  146. u8 *auth_tag, unsigned long auth_tag_len);
  147. asmlinkage void aesni_gcm_dec_avx_gen2(void *ctx, u8 *out,
  148. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  149. const u8 *aad, unsigned long aad_len,
  150. u8 *auth_tag, unsigned long auth_tag_len);
  151. static void aesni_gcm_enc_avx(void *ctx, u8 *out,
  152. const u8 *in, unsigned long plaintext_len, u8 *iv,
  153. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  154. u8 *auth_tag, unsigned long auth_tag_len)
  155. {
  156. struct crypto_aes_ctx *aes_ctx = (struct crypto_aes_ctx*)ctx;
  157. if ((plaintext_len < AVX_GEN2_OPTSIZE) || (aes_ctx-> key_length != AES_KEYSIZE_128)){
  158. aesni_gcm_enc(ctx, out, in, plaintext_len, iv, hash_subkey, aad,
  159. aad_len, auth_tag, auth_tag_len);
  160. } else {
  161. aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
  162. aesni_gcm_enc_avx_gen2(ctx, out, in, plaintext_len, iv, aad,
  163. aad_len, auth_tag, auth_tag_len);
  164. }
  165. }
  166. static void aesni_gcm_dec_avx(void *ctx, u8 *out,
  167. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  168. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  169. u8 *auth_tag, unsigned long auth_tag_len)
  170. {
  171. struct crypto_aes_ctx *aes_ctx = (struct crypto_aes_ctx*)ctx;
  172. if ((ciphertext_len < AVX_GEN2_OPTSIZE) || (aes_ctx-> key_length != AES_KEYSIZE_128)) {
  173. aesni_gcm_dec(ctx, out, in, ciphertext_len, iv, hash_subkey, aad,
  174. aad_len, auth_tag, auth_tag_len);
  175. } else {
  176. aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
  177. aesni_gcm_dec_avx_gen2(ctx, out, in, ciphertext_len, iv, aad,
  178. aad_len, auth_tag, auth_tag_len);
  179. }
  180. }
  181. #endif
  182. #ifdef CONFIG_AS_AVX2
  183. /*
  184. * asmlinkage void aesni_gcm_precomp_avx_gen4()
  185. * gcm_data *my_ctx_data, context data
  186. * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary.
  187. */
  188. asmlinkage void aesni_gcm_precomp_avx_gen4(void *my_ctx_data, u8 *hash_subkey);
  189. asmlinkage void aesni_gcm_enc_avx_gen4(void *ctx, u8 *out,
  190. const u8 *in, unsigned long plaintext_len, u8 *iv,
  191. const u8 *aad, unsigned long aad_len,
  192. u8 *auth_tag, unsigned long auth_tag_len);
  193. asmlinkage void aesni_gcm_dec_avx_gen4(void *ctx, u8 *out,
  194. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  195. const u8 *aad, unsigned long aad_len,
  196. u8 *auth_tag, unsigned long auth_tag_len);
  197. static void aesni_gcm_enc_avx2(void *ctx, u8 *out,
  198. const u8 *in, unsigned long plaintext_len, u8 *iv,
  199. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  200. u8 *auth_tag, unsigned long auth_tag_len)
  201. {
  202. struct crypto_aes_ctx *aes_ctx = (struct crypto_aes_ctx*)ctx;
  203. if ((plaintext_len < AVX_GEN2_OPTSIZE) || (aes_ctx-> key_length != AES_KEYSIZE_128)) {
  204. aesni_gcm_enc(ctx, out, in, plaintext_len, iv, hash_subkey, aad,
  205. aad_len, auth_tag, auth_tag_len);
  206. } else if (plaintext_len < AVX_GEN4_OPTSIZE) {
  207. aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
  208. aesni_gcm_enc_avx_gen2(ctx, out, in, plaintext_len, iv, aad,
  209. aad_len, auth_tag, auth_tag_len);
  210. } else {
  211. aesni_gcm_precomp_avx_gen4(ctx, hash_subkey);
  212. aesni_gcm_enc_avx_gen4(ctx, out, in, plaintext_len, iv, aad,
  213. aad_len, auth_tag, auth_tag_len);
  214. }
  215. }
  216. static void aesni_gcm_dec_avx2(void *ctx, u8 *out,
  217. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  218. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  219. u8 *auth_tag, unsigned long auth_tag_len)
  220. {
  221. struct crypto_aes_ctx *aes_ctx = (struct crypto_aes_ctx*)ctx;
  222. if ((ciphertext_len < AVX_GEN2_OPTSIZE) || (aes_ctx-> key_length != AES_KEYSIZE_128)) {
  223. aesni_gcm_dec(ctx, out, in, ciphertext_len, iv, hash_subkey,
  224. aad, aad_len, auth_tag, auth_tag_len);
  225. } else if (ciphertext_len < AVX_GEN4_OPTSIZE) {
  226. aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
  227. aesni_gcm_dec_avx_gen2(ctx, out, in, ciphertext_len, iv, aad,
  228. aad_len, auth_tag, auth_tag_len);
  229. } else {
  230. aesni_gcm_precomp_avx_gen4(ctx, hash_subkey);
  231. aesni_gcm_dec_avx_gen4(ctx, out, in, ciphertext_len, iv, aad,
  232. aad_len, auth_tag, auth_tag_len);
  233. }
  234. }
  235. #endif
  236. static void (*aesni_gcm_enc_tfm)(void *ctx, u8 *out,
  237. const u8 *in, unsigned long plaintext_len, u8 *iv,
  238. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  239. u8 *auth_tag, unsigned long auth_tag_len);
  240. static void (*aesni_gcm_dec_tfm)(void *ctx, u8 *out,
  241. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  242. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  243. u8 *auth_tag, unsigned long auth_tag_len);
  244. static inline struct
  245. aesni_rfc4106_gcm_ctx *aesni_rfc4106_gcm_ctx_get(struct crypto_aead *tfm)
  246. {
  247. unsigned long align = AESNI_ALIGN;
  248. if (align <= crypto_tfm_ctx_alignment())
  249. align = 1;
  250. return PTR_ALIGN(crypto_aead_ctx(tfm), align);
  251. }
  252. #endif
  253. static inline struct crypto_aes_ctx *aes_ctx(void *raw_ctx)
  254. {
  255. unsigned long addr = (unsigned long)raw_ctx;
  256. unsigned long align = AESNI_ALIGN;
  257. if (align <= crypto_tfm_ctx_alignment())
  258. align = 1;
  259. return (struct crypto_aes_ctx *)ALIGN(addr, align);
  260. }
  261. static int aes_set_key_common(struct crypto_tfm *tfm, void *raw_ctx,
  262. const u8 *in_key, unsigned int key_len)
  263. {
  264. struct crypto_aes_ctx *ctx = aes_ctx(raw_ctx);
  265. u32 *flags = &tfm->crt_flags;
  266. int err;
  267. if (key_len != AES_KEYSIZE_128 && key_len != AES_KEYSIZE_192 &&
  268. key_len != AES_KEYSIZE_256) {
  269. *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
  270. return -EINVAL;
  271. }
  272. if (!irq_fpu_usable())
  273. err = crypto_aes_expand_key(ctx, in_key, key_len);
  274. else {
  275. kernel_fpu_begin();
  276. err = aesni_set_key(ctx, in_key, key_len);
  277. kernel_fpu_end();
  278. }
  279. return err;
  280. }
  281. static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
  282. unsigned int key_len)
  283. {
  284. return aes_set_key_common(tfm, crypto_tfm_ctx(tfm), in_key, key_len);
  285. }
  286. static void aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
  287. {
  288. struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
  289. if (!irq_fpu_usable())
  290. crypto_aes_encrypt_x86(ctx, dst, src);
  291. else {
  292. kernel_fpu_begin();
  293. aesni_enc(ctx, dst, src);
  294. kernel_fpu_end();
  295. }
  296. }
  297. static void aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
  298. {
  299. struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
  300. if (!irq_fpu_usable())
  301. crypto_aes_decrypt_x86(ctx, dst, src);
  302. else {
  303. kernel_fpu_begin();
  304. aesni_dec(ctx, dst, src);
  305. kernel_fpu_end();
  306. }
  307. }
  308. static void __aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
  309. {
  310. struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
  311. aesni_enc(ctx, dst, src);
  312. }
  313. static void __aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
  314. {
  315. struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
  316. aesni_dec(ctx, dst, src);
  317. }
  318. static int ecb_encrypt(struct blkcipher_desc *desc,
  319. struct scatterlist *dst, struct scatterlist *src,
  320. unsigned int nbytes)
  321. {
  322. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  323. struct blkcipher_walk walk;
  324. int err;
  325. blkcipher_walk_init(&walk, dst, src, nbytes);
  326. err = blkcipher_walk_virt(desc, &walk);
  327. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  328. kernel_fpu_begin();
  329. while ((nbytes = walk.nbytes)) {
  330. aesni_ecb_enc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  331. nbytes & AES_BLOCK_MASK);
  332. nbytes &= AES_BLOCK_SIZE - 1;
  333. err = blkcipher_walk_done(desc, &walk, nbytes);
  334. }
  335. kernel_fpu_end();
  336. return err;
  337. }
  338. static int ecb_decrypt(struct blkcipher_desc *desc,
  339. struct scatterlist *dst, struct scatterlist *src,
  340. unsigned int nbytes)
  341. {
  342. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  343. struct blkcipher_walk walk;
  344. int err;
  345. blkcipher_walk_init(&walk, dst, src, nbytes);
  346. err = blkcipher_walk_virt(desc, &walk);
  347. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  348. kernel_fpu_begin();
  349. while ((nbytes = walk.nbytes)) {
  350. aesni_ecb_dec(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  351. nbytes & AES_BLOCK_MASK);
  352. nbytes &= AES_BLOCK_SIZE - 1;
  353. err = blkcipher_walk_done(desc, &walk, nbytes);
  354. }
  355. kernel_fpu_end();
  356. return err;
  357. }
  358. static int cbc_encrypt(struct blkcipher_desc *desc,
  359. struct scatterlist *dst, struct scatterlist *src,
  360. unsigned int nbytes)
  361. {
  362. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  363. struct blkcipher_walk walk;
  364. int err;
  365. blkcipher_walk_init(&walk, dst, src, nbytes);
  366. err = blkcipher_walk_virt(desc, &walk);
  367. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  368. kernel_fpu_begin();
  369. while ((nbytes = walk.nbytes)) {
  370. aesni_cbc_enc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  371. nbytes & AES_BLOCK_MASK, walk.iv);
  372. nbytes &= AES_BLOCK_SIZE - 1;
  373. err = blkcipher_walk_done(desc, &walk, nbytes);
  374. }
  375. kernel_fpu_end();
  376. return err;
  377. }
  378. static int cbc_decrypt(struct blkcipher_desc *desc,
  379. struct scatterlist *dst, struct scatterlist *src,
  380. unsigned int nbytes)
  381. {
  382. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  383. struct blkcipher_walk walk;
  384. int err;
  385. blkcipher_walk_init(&walk, dst, src, nbytes);
  386. err = blkcipher_walk_virt(desc, &walk);
  387. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  388. kernel_fpu_begin();
  389. while ((nbytes = walk.nbytes)) {
  390. aesni_cbc_dec(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  391. nbytes & AES_BLOCK_MASK, walk.iv);
  392. nbytes &= AES_BLOCK_SIZE - 1;
  393. err = blkcipher_walk_done(desc, &walk, nbytes);
  394. }
  395. kernel_fpu_end();
  396. return err;
  397. }
  398. #ifdef CONFIG_X86_64
  399. static void ctr_crypt_final(struct crypto_aes_ctx *ctx,
  400. struct blkcipher_walk *walk)
  401. {
  402. u8 *ctrblk = walk->iv;
  403. u8 keystream[AES_BLOCK_SIZE];
  404. u8 *src = walk->src.virt.addr;
  405. u8 *dst = walk->dst.virt.addr;
  406. unsigned int nbytes = walk->nbytes;
  407. aesni_enc(ctx, keystream, ctrblk);
  408. crypto_xor(keystream, src, nbytes);
  409. memcpy(dst, keystream, nbytes);
  410. crypto_inc(ctrblk, AES_BLOCK_SIZE);
  411. }
  412. #ifdef CONFIG_AS_AVX
  413. static void aesni_ctr_enc_avx_tfm(struct crypto_aes_ctx *ctx, u8 *out,
  414. const u8 *in, unsigned int len, u8 *iv)
  415. {
  416. /*
  417. * based on key length, override with the by8 version
  418. * of ctr mode encryption/decryption for improved performance
  419. * aes_set_key_common() ensures that key length is one of
  420. * {128,192,256}
  421. */
  422. if (ctx->key_length == AES_KEYSIZE_128)
  423. aes_ctr_enc_128_avx_by8(in, iv, (void *)ctx, out, len);
  424. else if (ctx->key_length == AES_KEYSIZE_192)
  425. aes_ctr_enc_192_avx_by8(in, iv, (void *)ctx, out, len);
  426. else
  427. aes_ctr_enc_256_avx_by8(in, iv, (void *)ctx, out, len);
  428. }
  429. #endif
  430. static int ctr_crypt(struct blkcipher_desc *desc,
  431. struct scatterlist *dst, struct scatterlist *src,
  432. unsigned int nbytes)
  433. {
  434. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  435. struct blkcipher_walk walk;
  436. int err;
  437. blkcipher_walk_init(&walk, dst, src, nbytes);
  438. err = blkcipher_walk_virt_block(desc, &walk, AES_BLOCK_SIZE);
  439. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  440. kernel_fpu_begin();
  441. while ((nbytes = walk.nbytes) >= AES_BLOCK_SIZE) {
  442. aesni_ctr_enc_tfm(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  443. nbytes & AES_BLOCK_MASK, walk.iv);
  444. nbytes &= AES_BLOCK_SIZE - 1;
  445. err = blkcipher_walk_done(desc, &walk, nbytes);
  446. }
  447. if (walk.nbytes) {
  448. ctr_crypt_final(ctx, &walk);
  449. err = blkcipher_walk_done(desc, &walk, 0);
  450. }
  451. kernel_fpu_end();
  452. return err;
  453. }
  454. #endif
  455. static int ablk_ecb_init(struct crypto_tfm *tfm)
  456. {
  457. return ablk_init_common(tfm, "__driver-ecb-aes-aesni");
  458. }
  459. static int ablk_cbc_init(struct crypto_tfm *tfm)
  460. {
  461. return ablk_init_common(tfm, "__driver-cbc-aes-aesni");
  462. }
  463. #ifdef CONFIG_X86_64
  464. static int ablk_ctr_init(struct crypto_tfm *tfm)
  465. {
  466. return ablk_init_common(tfm, "__driver-ctr-aes-aesni");
  467. }
  468. #endif
  469. #if IS_ENABLED(CONFIG_CRYPTO_PCBC)
  470. static int ablk_pcbc_init(struct crypto_tfm *tfm)
  471. {
  472. return ablk_init_common(tfm, "fpu(pcbc(__driver-aes-aesni))");
  473. }
  474. #endif
  475. static void lrw_xts_encrypt_callback(void *ctx, u8 *blks, unsigned int nbytes)
  476. {
  477. aesni_ecb_enc(ctx, blks, blks, nbytes);
  478. }
  479. static void lrw_xts_decrypt_callback(void *ctx, u8 *blks, unsigned int nbytes)
  480. {
  481. aesni_ecb_dec(ctx, blks, blks, nbytes);
  482. }
  483. static int lrw_aesni_setkey(struct crypto_tfm *tfm, const u8 *key,
  484. unsigned int keylen)
  485. {
  486. struct aesni_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
  487. int err;
  488. err = aes_set_key_common(tfm, ctx->raw_aes_ctx, key,
  489. keylen - AES_BLOCK_SIZE);
  490. if (err)
  491. return err;
  492. return lrw_init_table(&ctx->lrw_table, key + keylen - AES_BLOCK_SIZE);
  493. }
  494. static void lrw_aesni_exit_tfm(struct crypto_tfm *tfm)
  495. {
  496. struct aesni_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
  497. lrw_free_table(&ctx->lrw_table);
  498. }
  499. static int lrw_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  500. struct scatterlist *src, unsigned int nbytes)
  501. {
  502. struct aesni_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  503. be128 buf[8];
  504. struct lrw_crypt_req req = {
  505. .tbuf = buf,
  506. .tbuflen = sizeof(buf),
  507. .table_ctx = &ctx->lrw_table,
  508. .crypt_ctx = aes_ctx(ctx->raw_aes_ctx),
  509. .crypt_fn = lrw_xts_encrypt_callback,
  510. };
  511. int ret;
  512. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  513. kernel_fpu_begin();
  514. ret = lrw_crypt(desc, dst, src, nbytes, &req);
  515. kernel_fpu_end();
  516. return ret;
  517. }
  518. static int lrw_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  519. struct scatterlist *src, unsigned int nbytes)
  520. {
  521. struct aesni_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  522. be128 buf[8];
  523. struct lrw_crypt_req req = {
  524. .tbuf = buf,
  525. .tbuflen = sizeof(buf),
  526. .table_ctx = &ctx->lrw_table,
  527. .crypt_ctx = aes_ctx(ctx->raw_aes_ctx),
  528. .crypt_fn = lrw_xts_decrypt_callback,
  529. };
  530. int ret;
  531. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  532. kernel_fpu_begin();
  533. ret = lrw_crypt(desc, dst, src, nbytes, &req);
  534. kernel_fpu_end();
  535. return ret;
  536. }
  537. static int xts_aesni_setkey(struct crypto_tfm *tfm, const u8 *key,
  538. unsigned int keylen)
  539. {
  540. struct aesni_xts_ctx *ctx = crypto_tfm_ctx(tfm);
  541. int err;
  542. err = xts_check_key(tfm, key, keylen);
  543. if (err)
  544. return err;
  545. /* first half of xts-key is for crypt */
  546. err = aes_set_key_common(tfm, ctx->raw_crypt_ctx, key, keylen / 2);
  547. if (err)
  548. return err;
  549. /* second half of xts-key is for tweak */
  550. return aes_set_key_common(tfm, ctx->raw_tweak_ctx, key + keylen / 2,
  551. keylen / 2);
  552. }
  553. static void aesni_xts_tweak(void *ctx, u8 *out, const u8 *in)
  554. {
  555. aesni_enc(ctx, out, in);
  556. }
  557. #ifdef CONFIG_X86_64
  558. static void aesni_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv)
  559. {
  560. glue_xts_crypt_128bit_one(ctx, dst, src, iv, GLUE_FUNC_CAST(aesni_enc));
  561. }
  562. static void aesni_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv)
  563. {
  564. glue_xts_crypt_128bit_one(ctx, dst, src, iv, GLUE_FUNC_CAST(aesni_dec));
  565. }
  566. static void aesni_xts_enc8(void *ctx, u128 *dst, const u128 *src, le128 *iv)
  567. {
  568. aesni_xts_crypt8(ctx, (u8 *)dst, (const u8 *)src, true, (u8 *)iv);
  569. }
  570. static void aesni_xts_dec8(void *ctx, u128 *dst, const u128 *src, le128 *iv)
  571. {
  572. aesni_xts_crypt8(ctx, (u8 *)dst, (const u8 *)src, false, (u8 *)iv);
  573. }
  574. static const struct common_glue_ctx aesni_enc_xts = {
  575. .num_funcs = 2,
  576. .fpu_blocks_limit = 1,
  577. .funcs = { {
  578. .num_blocks = 8,
  579. .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_enc8) }
  580. }, {
  581. .num_blocks = 1,
  582. .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_enc) }
  583. } }
  584. };
  585. static const struct common_glue_ctx aesni_dec_xts = {
  586. .num_funcs = 2,
  587. .fpu_blocks_limit = 1,
  588. .funcs = { {
  589. .num_blocks = 8,
  590. .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_dec8) }
  591. }, {
  592. .num_blocks = 1,
  593. .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_dec) }
  594. } }
  595. };
  596. static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  597. struct scatterlist *src, unsigned int nbytes)
  598. {
  599. struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  600. return glue_xts_crypt_128bit(&aesni_enc_xts, desc, dst, src, nbytes,
  601. XTS_TWEAK_CAST(aesni_xts_tweak),
  602. aes_ctx(ctx->raw_tweak_ctx),
  603. aes_ctx(ctx->raw_crypt_ctx));
  604. }
  605. static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  606. struct scatterlist *src, unsigned int nbytes)
  607. {
  608. struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  609. return glue_xts_crypt_128bit(&aesni_dec_xts, desc, dst, src, nbytes,
  610. XTS_TWEAK_CAST(aesni_xts_tweak),
  611. aes_ctx(ctx->raw_tweak_ctx),
  612. aes_ctx(ctx->raw_crypt_ctx));
  613. }
  614. #else
  615. static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  616. struct scatterlist *src, unsigned int nbytes)
  617. {
  618. struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  619. be128 buf[8];
  620. struct xts_crypt_req req = {
  621. .tbuf = buf,
  622. .tbuflen = sizeof(buf),
  623. .tweak_ctx = aes_ctx(ctx->raw_tweak_ctx),
  624. .tweak_fn = aesni_xts_tweak,
  625. .crypt_ctx = aes_ctx(ctx->raw_crypt_ctx),
  626. .crypt_fn = lrw_xts_encrypt_callback,
  627. };
  628. int ret;
  629. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  630. kernel_fpu_begin();
  631. ret = xts_crypt(desc, dst, src, nbytes, &req);
  632. kernel_fpu_end();
  633. return ret;
  634. }
  635. static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  636. struct scatterlist *src, unsigned int nbytes)
  637. {
  638. struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  639. be128 buf[8];
  640. struct xts_crypt_req req = {
  641. .tbuf = buf,
  642. .tbuflen = sizeof(buf),
  643. .tweak_ctx = aes_ctx(ctx->raw_tweak_ctx),
  644. .tweak_fn = aesni_xts_tweak,
  645. .crypt_ctx = aes_ctx(ctx->raw_crypt_ctx),
  646. .crypt_fn = lrw_xts_decrypt_callback,
  647. };
  648. int ret;
  649. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  650. kernel_fpu_begin();
  651. ret = xts_crypt(desc, dst, src, nbytes, &req);
  652. kernel_fpu_end();
  653. return ret;
  654. }
  655. #endif
  656. #ifdef CONFIG_X86_64
  657. static int rfc4106_init(struct crypto_aead *aead)
  658. {
  659. struct cryptd_aead *cryptd_tfm;
  660. struct cryptd_aead **ctx = crypto_aead_ctx(aead);
  661. cryptd_tfm = cryptd_alloc_aead("__driver-gcm-aes-aesni",
  662. CRYPTO_ALG_INTERNAL,
  663. CRYPTO_ALG_INTERNAL);
  664. if (IS_ERR(cryptd_tfm))
  665. return PTR_ERR(cryptd_tfm);
  666. *ctx = cryptd_tfm;
  667. crypto_aead_set_reqsize(aead, crypto_aead_reqsize(&cryptd_tfm->base));
  668. return 0;
  669. }
  670. static void rfc4106_exit(struct crypto_aead *aead)
  671. {
  672. struct cryptd_aead **ctx = crypto_aead_ctx(aead);
  673. cryptd_free_aead(*ctx);
  674. }
  675. static int
  676. rfc4106_set_hash_subkey(u8 *hash_subkey, const u8 *key, unsigned int key_len)
  677. {
  678. struct crypto_cipher *tfm;
  679. int ret;
  680. tfm = crypto_alloc_cipher("aes", 0, 0);
  681. if (IS_ERR(tfm))
  682. return PTR_ERR(tfm);
  683. ret = crypto_cipher_setkey(tfm, key, key_len);
  684. if (ret)
  685. goto out_free_cipher;
  686. /* Clear the data in the hash sub key container to zero.*/
  687. /* We want to cipher all zeros to create the hash sub key. */
  688. memset(hash_subkey, 0, RFC4106_HASH_SUBKEY_SIZE);
  689. crypto_cipher_encrypt_one(tfm, hash_subkey, hash_subkey);
  690. out_free_cipher:
  691. crypto_free_cipher(tfm);
  692. return ret;
  693. }
  694. static int common_rfc4106_set_key(struct crypto_aead *aead, const u8 *key,
  695. unsigned int key_len)
  696. {
  697. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(aead);
  698. if (key_len < 4) {
  699. crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
  700. return -EINVAL;
  701. }
  702. /*Account for 4 byte nonce at the end.*/
  703. key_len -= 4;
  704. memcpy(ctx->nonce, key + key_len, sizeof(ctx->nonce));
  705. return aes_set_key_common(crypto_aead_tfm(aead),
  706. &ctx->aes_key_expanded, key, key_len) ?:
  707. rfc4106_set_hash_subkey(ctx->hash_subkey, key, key_len);
  708. }
  709. static int rfc4106_set_key(struct crypto_aead *parent, const u8 *key,
  710. unsigned int key_len)
  711. {
  712. struct cryptd_aead **ctx = crypto_aead_ctx(parent);
  713. struct cryptd_aead *cryptd_tfm = *ctx;
  714. return crypto_aead_setkey(&cryptd_tfm->base, key, key_len);
  715. }
  716. static int common_rfc4106_set_authsize(struct crypto_aead *aead,
  717. unsigned int authsize)
  718. {
  719. switch (authsize) {
  720. case 8:
  721. case 12:
  722. case 16:
  723. break;
  724. default:
  725. return -EINVAL;
  726. }
  727. return 0;
  728. }
  729. /* This is the Integrity Check Value (aka the authentication tag length and can
  730. * be 8, 12 or 16 bytes long. */
  731. static int rfc4106_set_authsize(struct crypto_aead *parent,
  732. unsigned int authsize)
  733. {
  734. struct cryptd_aead **ctx = crypto_aead_ctx(parent);
  735. struct cryptd_aead *cryptd_tfm = *ctx;
  736. return crypto_aead_setauthsize(&cryptd_tfm->base, authsize);
  737. }
  738. static int helper_rfc4106_encrypt(struct aead_request *req)
  739. {
  740. u8 one_entry_in_sg = 0;
  741. u8 *src, *dst, *assoc;
  742. __be32 counter = cpu_to_be32(1);
  743. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  744. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm);
  745. void *aes_ctx = &(ctx->aes_key_expanded);
  746. unsigned long auth_tag_len = crypto_aead_authsize(tfm);
  747. u8 iv[16] __attribute__ ((__aligned__(AESNI_ALIGN)));
  748. struct scatter_walk src_sg_walk;
  749. struct scatter_walk dst_sg_walk = {};
  750. unsigned int i;
  751. /* Assuming we are supporting rfc4106 64-bit extended */
  752. /* sequence numbers We need to have the AAD length equal */
  753. /* to 16 or 20 bytes */
  754. if (unlikely(req->assoclen != 16 && req->assoclen != 20))
  755. return -EINVAL;
  756. /* IV below built */
  757. for (i = 0; i < 4; i++)
  758. *(iv+i) = ctx->nonce[i];
  759. for (i = 0; i < 8; i++)
  760. *(iv+4+i) = req->iv[i];
  761. *((__be32 *)(iv+12)) = counter;
  762. if (sg_is_last(req->src) &&
  763. req->src->offset + req->src->length <= PAGE_SIZE &&
  764. + sg_is_last(req->dst) && req->dst->length &&
  765. req->dst->offset + req->dst->length <= PAGE_SIZE) {
  766. one_entry_in_sg = 1;
  767. scatterwalk_start(&src_sg_walk, req->src);
  768. assoc = scatterwalk_map(&src_sg_walk);
  769. src = assoc + req->assoclen;
  770. dst = src;
  771. if (unlikely(req->src != req->dst)) {
  772. scatterwalk_start(&dst_sg_walk, req->dst);
  773. dst = scatterwalk_map(&dst_sg_walk) + req->assoclen;
  774. }
  775. } else {
  776. /* Allocate memory for src, dst, assoc */
  777. assoc = kmalloc(req->cryptlen + auth_tag_len + req->assoclen,
  778. GFP_ATOMIC);
  779. if (unlikely(!assoc))
  780. return -ENOMEM;
  781. scatterwalk_map_and_copy(assoc, req->src, 0,
  782. req->assoclen + req->cryptlen, 0);
  783. src = assoc + req->assoclen;
  784. dst = src;
  785. }
  786. kernel_fpu_begin();
  787. aesni_gcm_enc_tfm(aes_ctx, dst, src, req->cryptlen, iv,
  788. ctx->hash_subkey, assoc, req->assoclen - 8,
  789. dst + req->cryptlen, auth_tag_len);
  790. kernel_fpu_end();
  791. /* The authTag (aka the Integrity Check Value) needs to be written
  792. * back to the packet. */
  793. if (one_entry_in_sg) {
  794. if (unlikely(req->src != req->dst)) {
  795. scatterwalk_unmap(dst - req->assoclen);
  796. scatterwalk_advance(&dst_sg_walk, req->dst->length);
  797. scatterwalk_done(&dst_sg_walk, 1, 0);
  798. }
  799. scatterwalk_unmap(assoc);
  800. scatterwalk_advance(&src_sg_walk, req->src->length);
  801. scatterwalk_done(&src_sg_walk, req->src == req->dst, 0);
  802. } else {
  803. scatterwalk_map_and_copy(dst, req->dst, req->assoclen,
  804. req->cryptlen + auth_tag_len, 1);
  805. kfree(assoc);
  806. }
  807. return 0;
  808. }
  809. static int helper_rfc4106_decrypt(struct aead_request *req)
  810. {
  811. u8 one_entry_in_sg = 0;
  812. u8 *src, *dst, *assoc;
  813. unsigned long tempCipherLen = 0;
  814. __be32 counter = cpu_to_be32(1);
  815. int retval = 0;
  816. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  817. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm);
  818. void *aes_ctx = &(ctx->aes_key_expanded);
  819. unsigned long auth_tag_len = crypto_aead_authsize(tfm);
  820. u8 iv[16] __attribute__ ((__aligned__(AESNI_ALIGN)));
  821. u8 authTag[16];
  822. struct scatter_walk src_sg_walk;
  823. struct scatter_walk dst_sg_walk = {};
  824. unsigned int i;
  825. if (unlikely(req->assoclen != 16 && req->assoclen != 20))
  826. return -EINVAL;
  827. /* Assuming we are supporting rfc4106 64-bit extended */
  828. /* sequence numbers We need to have the AAD length */
  829. /* equal to 16 or 20 bytes */
  830. tempCipherLen = (unsigned long)(req->cryptlen - auth_tag_len);
  831. /* IV below built */
  832. for (i = 0; i < 4; i++)
  833. *(iv+i) = ctx->nonce[i];
  834. for (i = 0; i < 8; i++)
  835. *(iv+4+i) = req->iv[i];
  836. *((__be32 *)(iv+12)) = counter;
  837. if (sg_is_last(req->src) &&
  838. req->src->offset + req->src->length <= PAGE_SIZE &&
  839. sg_is_last(req->dst) &&
  840. req->dst->offset + req->dst->length <= PAGE_SIZE) {
  841. one_entry_in_sg = 1;
  842. scatterwalk_start(&src_sg_walk, req->src);
  843. assoc = scatterwalk_map(&src_sg_walk);
  844. src = assoc + req->assoclen;
  845. dst = src;
  846. if (unlikely(req->src != req->dst)) {
  847. scatterwalk_start(&dst_sg_walk, req->dst);
  848. dst = scatterwalk_map(&dst_sg_walk) + req->assoclen;
  849. }
  850. } else {
  851. /* Allocate memory for src, dst, assoc */
  852. assoc = kmalloc(req->cryptlen + req->assoclen, GFP_ATOMIC);
  853. if (!assoc)
  854. return -ENOMEM;
  855. scatterwalk_map_and_copy(assoc, req->src, 0,
  856. req->assoclen + req->cryptlen, 0);
  857. src = assoc + req->assoclen;
  858. dst = src;
  859. }
  860. kernel_fpu_begin();
  861. aesni_gcm_dec_tfm(aes_ctx, dst, src, tempCipherLen, iv,
  862. ctx->hash_subkey, assoc, req->assoclen - 8,
  863. authTag, auth_tag_len);
  864. kernel_fpu_end();
  865. /* Compare generated tag with passed in tag. */
  866. retval = crypto_memneq(src + tempCipherLen, authTag, auth_tag_len) ?
  867. -EBADMSG : 0;
  868. if (one_entry_in_sg) {
  869. if (unlikely(req->src != req->dst)) {
  870. scatterwalk_unmap(dst - req->assoclen);
  871. scatterwalk_advance(&dst_sg_walk, req->dst->length);
  872. scatterwalk_done(&dst_sg_walk, 1, 0);
  873. }
  874. scatterwalk_unmap(assoc);
  875. scatterwalk_advance(&src_sg_walk, req->src->length);
  876. scatterwalk_done(&src_sg_walk, req->src == req->dst, 0);
  877. } else {
  878. scatterwalk_map_and_copy(dst, req->dst, req->assoclen,
  879. tempCipherLen, 1);
  880. kfree(assoc);
  881. }
  882. return retval;
  883. }
  884. static int rfc4106_encrypt(struct aead_request *req)
  885. {
  886. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  887. struct cryptd_aead **ctx = crypto_aead_ctx(tfm);
  888. struct cryptd_aead *cryptd_tfm = *ctx;
  889. tfm = &cryptd_tfm->base;
  890. if (irq_fpu_usable() && (!in_atomic() ||
  891. !cryptd_aead_queued(cryptd_tfm)))
  892. tfm = cryptd_aead_child(cryptd_tfm);
  893. aead_request_set_tfm(req, tfm);
  894. return crypto_aead_encrypt(req);
  895. }
  896. static int rfc4106_decrypt(struct aead_request *req)
  897. {
  898. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  899. struct cryptd_aead **ctx = crypto_aead_ctx(tfm);
  900. struct cryptd_aead *cryptd_tfm = *ctx;
  901. tfm = &cryptd_tfm->base;
  902. if (irq_fpu_usable() && (!in_atomic() ||
  903. !cryptd_aead_queued(cryptd_tfm)))
  904. tfm = cryptd_aead_child(cryptd_tfm);
  905. aead_request_set_tfm(req, tfm);
  906. return crypto_aead_decrypt(req);
  907. }
  908. #endif
  909. static struct crypto_alg aesni_algs[] = { {
  910. .cra_name = "aes",
  911. .cra_driver_name = "aes-aesni",
  912. .cra_priority = 300,
  913. .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
  914. .cra_blocksize = AES_BLOCK_SIZE,
  915. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  916. AESNI_ALIGN - 1,
  917. .cra_alignmask = 0,
  918. .cra_module = THIS_MODULE,
  919. .cra_u = {
  920. .cipher = {
  921. .cia_min_keysize = AES_MIN_KEY_SIZE,
  922. .cia_max_keysize = AES_MAX_KEY_SIZE,
  923. .cia_setkey = aes_set_key,
  924. .cia_encrypt = aes_encrypt,
  925. .cia_decrypt = aes_decrypt
  926. }
  927. }
  928. }, {
  929. .cra_name = "__aes-aesni",
  930. .cra_driver_name = "__driver-aes-aesni",
  931. .cra_priority = 0,
  932. .cra_flags = CRYPTO_ALG_TYPE_CIPHER | CRYPTO_ALG_INTERNAL,
  933. .cra_blocksize = AES_BLOCK_SIZE,
  934. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  935. AESNI_ALIGN - 1,
  936. .cra_alignmask = 0,
  937. .cra_module = THIS_MODULE,
  938. .cra_u = {
  939. .cipher = {
  940. .cia_min_keysize = AES_MIN_KEY_SIZE,
  941. .cia_max_keysize = AES_MAX_KEY_SIZE,
  942. .cia_setkey = aes_set_key,
  943. .cia_encrypt = __aes_encrypt,
  944. .cia_decrypt = __aes_decrypt
  945. }
  946. }
  947. }, {
  948. .cra_name = "__ecb-aes-aesni",
  949. .cra_driver_name = "__driver-ecb-aes-aesni",
  950. .cra_priority = 0,
  951. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
  952. CRYPTO_ALG_INTERNAL,
  953. .cra_blocksize = AES_BLOCK_SIZE,
  954. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  955. AESNI_ALIGN - 1,
  956. .cra_alignmask = 0,
  957. .cra_type = &crypto_blkcipher_type,
  958. .cra_module = THIS_MODULE,
  959. .cra_u = {
  960. .blkcipher = {
  961. .min_keysize = AES_MIN_KEY_SIZE,
  962. .max_keysize = AES_MAX_KEY_SIZE,
  963. .setkey = aes_set_key,
  964. .encrypt = ecb_encrypt,
  965. .decrypt = ecb_decrypt,
  966. },
  967. },
  968. }, {
  969. .cra_name = "__cbc-aes-aesni",
  970. .cra_driver_name = "__driver-cbc-aes-aesni",
  971. .cra_priority = 0,
  972. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
  973. CRYPTO_ALG_INTERNAL,
  974. .cra_blocksize = AES_BLOCK_SIZE,
  975. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  976. AESNI_ALIGN - 1,
  977. .cra_alignmask = 0,
  978. .cra_type = &crypto_blkcipher_type,
  979. .cra_module = THIS_MODULE,
  980. .cra_u = {
  981. .blkcipher = {
  982. .min_keysize = AES_MIN_KEY_SIZE,
  983. .max_keysize = AES_MAX_KEY_SIZE,
  984. .setkey = aes_set_key,
  985. .encrypt = cbc_encrypt,
  986. .decrypt = cbc_decrypt,
  987. },
  988. },
  989. }, {
  990. .cra_name = "ecb(aes)",
  991. .cra_driver_name = "ecb-aes-aesni",
  992. .cra_priority = 400,
  993. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  994. .cra_blocksize = AES_BLOCK_SIZE,
  995. .cra_ctxsize = sizeof(struct async_helper_ctx),
  996. .cra_alignmask = 0,
  997. .cra_type = &crypto_ablkcipher_type,
  998. .cra_module = THIS_MODULE,
  999. .cra_init = ablk_ecb_init,
  1000. .cra_exit = ablk_exit,
  1001. .cra_u = {
  1002. .ablkcipher = {
  1003. .min_keysize = AES_MIN_KEY_SIZE,
  1004. .max_keysize = AES_MAX_KEY_SIZE,
  1005. .setkey = ablk_set_key,
  1006. .encrypt = ablk_encrypt,
  1007. .decrypt = ablk_decrypt,
  1008. },
  1009. },
  1010. }, {
  1011. .cra_name = "cbc(aes)",
  1012. .cra_driver_name = "cbc-aes-aesni",
  1013. .cra_priority = 400,
  1014. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1015. .cra_blocksize = AES_BLOCK_SIZE,
  1016. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1017. .cra_alignmask = 0,
  1018. .cra_type = &crypto_ablkcipher_type,
  1019. .cra_module = THIS_MODULE,
  1020. .cra_init = ablk_cbc_init,
  1021. .cra_exit = ablk_exit,
  1022. .cra_u = {
  1023. .ablkcipher = {
  1024. .min_keysize = AES_MIN_KEY_SIZE,
  1025. .max_keysize = AES_MAX_KEY_SIZE,
  1026. .ivsize = AES_BLOCK_SIZE,
  1027. .setkey = ablk_set_key,
  1028. .encrypt = ablk_encrypt,
  1029. .decrypt = ablk_decrypt,
  1030. },
  1031. },
  1032. #ifdef CONFIG_X86_64
  1033. }, {
  1034. .cra_name = "__ctr-aes-aesni",
  1035. .cra_driver_name = "__driver-ctr-aes-aesni",
  1036. .cra_priority = 0,
  1037. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
  1038. CRYPTO_ALG_INTERNAL,
  1039. .cra_blocksize = 1,
  1040. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  1041. AESNI_ALIGN - 1,
  1042. .cra_alignmask = 0,
  1043. .cra_type = &crypto_blkcipher_type,
  1044. .cra_module = THIS_MODULE,
  1045. .cra_u = {
  1046. .blkcipher = {
  1047. .min_keysize = AES_MIN_KEY_SIZE,
  1048. .max_keysize = AES_MAX_KEY_SIZE,
  1049. .ivsize = AES_BLOCK_SIZE,
  1050. .setkey = aes_set_key,
  1051. .encrypt = ctr_crypt,
  1052. .decrypt = ctr_crypt,
  1053. },
  1054. },
  1055. }, {
  1056. .cra_name = "ctr(aes)",
  1057. .cra_driver_name = "ctr-aes-aesni",
  1058. .cra_priority = 400,
  1059. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1060. .cra_blocksize = 1,
  1061. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1062. .cra_alignmask = 0,
  1063. .cra_type = &crypto_ablkcipher_type,
  1064. .cra_module = THIS_MODULE,
  1065. .cra_init = ablk_ctr_init,
  1066. .cra_exit = ablk_exit,
  1067. .cra_u = {
  1068. .ablkcipher = {
  1069. .min_keysize = AES_MIN_KEY_SIZE,
  1070. .max_keysize = AES_MAX_KEY_SIZE,
  1071. .ivsize = AES_BLOCK_SIZE,
  1072. .setkey = ablk_set_key,
  1073. .encrypt = ablk_encrypt,
  1074. .decrypt = ablk_encrypt,
  1075. .geniv = "chainiv",
  1076. },
  1077. },
  1078. #endif
  1079. #if IS_ENABLED(CONFIG_CRYPTO_PCBC)
  1080. }, {
  1081. .cra_name = "pcbc(aes)",
  1082. .cra_driver_name = "pcbc-aes-aesni",
  1083. .cra_priority = 400,
  1084. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1085. .cra_blocksize = AES_BLOCK_SIZE,
  1086. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1087. .cra_alignmask = 0,
  1088. .cra_type = &crypto_ablkcipher_type,
  1089. .cra_module = THIS_MODULE,
  1090. .cra_init = ablk_pcbc_init,
  1091. .cra_exit = ablk_exit,
  1092. .cra_u = {
  1093. .ablkcipher = {
  1094. .min_keysize = AES_MIN_KEY_SIZE,
  1095. .max_keysize = AES_MAX_KEY_SIZE,
  1096. .ivsize = AES_BLOCK_SIZE,
  1097. .setkey = ablk_set_key,
  1098. .encrypt = ablk_encrypt,
  1099. .decrypt = ablk_decrypt,
  1100. },
  1101. },
  1102. #endif
  1103. }, {
  1104. .cra_name = "__lrw-aes-aesni",
  1105. .cra_driver_name = "__driver-lrw-aes-aesni",
  1106. .cra_priority = 0,
  1107. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
  1108. CRYPTO_ALG_INTERNAL,
  1109. .cra_blocksize = AES_BLOCK_SIZE,
  1110. .cra_ctxsize = sizeof(struct aesni_lrw_ctx),
  1111. .cra_alignmask = 0,
  1112. .cra_type = &crypto_blkcipher_type,
  1113. .cra_module = THIS_MODULE,
  1114. .cra_exit = lrw_aesni_exit_tfm,
  1115. .cra_u = {
  1116. .blkcipher = {
  1117. .min_keysize = AES_MIN_KEY_SIZE + AES_BLOCK_SIZE,
  1118. .max_keysize = AES_MAX_KEY_SIZE + AES_BLOCK_SIZE,
  1119. .ivsize = AES_BLOCK_SIZE,
  1120. .setkey = lrw_aesni_setkey,
  1121. .encrypt = lrw_encrypt,
  1122. .decrypt = lrw_decrypt,
  1123. },
  1124. },
  1125. }, {
  1126. .cra_name = "__xts-aes-aesni",
  1127. .cra_driver_name = "__driver-xts-aes-aesni",
  1128. .cra_priority = 0,
  1129. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
  1130. CRYPTO_ALG_INTERNAL,
  1131. .cra_blocksize = AES_BLOCK_SIZE,
  1132. .cra_ctxsize = sizeof(struct aesni_xts_ctx),
  1133. .cra_alignmask = 0,
  1134. .cra_type = &crypto_blkcipher_type,
  1135. .cra_module = THIS_MODULE,
  1136. .cra_u = {
  1137. .blkcipher = {
  1138. .min_keysize = 2 * AES_MIN_KEY_SIZE,
  1139. .max_keysize = 2 * AES_MAX_KEY_SIZE,
  1140. .ivsize = AES_BLOCK_SIZE,
  1141. .setkey = xts_aesni_setkey,
  1142. .encrypt = xts_encrypt,
  1143. .decrypt = xts_decrypt,
  1144. },
  1145. },
  1146. }, {
  1147. .cra_name = "lrw(aes)",
  1148. .cra_driver_name = "lrw-aes-aesni",
  1149. .cra_priority = 400,
  1150. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1151. .cra_blocksize = AES_BLOCK_SIZE,
  1152. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1153. .cra_alignmask = 0,
  1154. .cra_type = &crypto_ablkcipher_type,
  1155. .cra_module = THIS_MODULE,
  1156. .cra_init = ablk_init,
  1157. .cra_exit = ablk_exit,
  1158. .cra_u = {
  1159. .ablkcipher = {
  1160. .min_keysize = AES_MIN_KEY_SIZE + AES_BLOCK_SIZE,
  1161. .max_keysize = AES_MAX_KEY_SIZE + AES_BLOCK_SIZE,
  1162. .ivsize = AES_BLOCK_SIZE,
  1163. .setkey = ablk_set_key,
  1164. .encrypt = ablk_encrypt,
  1165. .decrypt = ablk_decrypt,
  1166. },
  1167. },
  1168. }, {
  1169. .cra_name = "xts(aes)",
  1170. .cra_driver_name = "xts-aes-aesni",
  1171. .cra_priority = 400,
  1172. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1173. .cra_blocksize = AES_BLOCK_SIZE,
  1174. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1175. .cra_alignmask = 0,
  1176. .cra_type = &crypto_ablkcipher_type,
  1177. .cra_module = THIS_MODULE,
  1178. .cra_init = ablk_init,
  1179. .cra_exit = ablk_exit,
  1180. .cra_u = {
  1181. .ablkcipher = {
  1182. .min_keysize = 2 * AES_MIN_KEY_SIZE,
  1183. .max_keysize = 2 * AES_MAX_KEY_SIZE,
  1184. .ivsize = AES_BLOCK_SIZE,
  1185. .setkey = ablk_set_key,
  1186. .encrypt = ablk_encrypt,
  1187. .decrypt = ablk_decrypt,
  1188. },
  1189. },
  1190. } };
  1191. #ifdef CONFIG_X86_64
  1192. static struct aead_alg aesni_aead_algs[] = { {
  1193. .setkey = common_rfc4106_set_key,
  1194. .setauthsize = common_rfc4106_set_authsize,
  1195. .encrypt = helper_rfc4106_encrypt,
  1196. .decrypt = helper_rfc4106_decrypt,
  1197. .ivsize = 8,
  1198. .maxauthsize = 16,
  1199. .base = {
  1200. .cra_name = "__gcm-aes-aesni",
  1201. .cra_driver_name = "__driver-gcm-aes-aesni",
  1202. .cra_flags = CRYPTO_ALG_INTERNAL,
  1203. .cra_blocksize = 1,
  1204. .cra_ctxsize = sizeof(struct aesni_rfc4106_gcm_ctx),
  1205. .cra_alignmask = AESNI_ALIGN - 1,
  1206. .cra_module = THIS_MODULE,
  1207. },
  1208. }, {
  1209. .init = rfc4106_init,
  1210. .exit = rfc4106_exit,
  1211. .setkey = rfc4106_set_key,
  1212. .setauthsize = rfc4106_set_authsize,
  1213. .encrypt = rfc4106_encrypt,
  1214. .decrypt = rfc4106_decrypt,
  1215. .ivsize = 8,
  1216. .maxauthsize = 16,
  1217. .base = {
  1218. .cra_name = "rfc4106(gcm(aes))",
  1219. .cra_driver_name = "rfc4106-gcm-aesni",
  1220. .cra_priority = 400,
  1221. .cra_flags = CRYPTO_ALG_ASYNC,
  1222. .cra_blocksize = 1,
  1223. .cra_ctxsize = sizeof(struct cryptd_aead *),
  1224. .cra_module = THIS_MODULE,
  1225. },
  1226. } };
  1227. #else
  1228. static struct aead_alg aesni_aead_algs[0];
  1229. #endif
  1230. static const struct x86_cpu_id aesni_cpu_id[] = {
  1231. X86_FEATURE_MATCH(X86_FEATURE_AES),
  1232. {}
  1233. };
  1234. MODULE_DEVICE_TABLE(x86cpu, aesni_cpu_id);
  1235. static int __init aesni_init(void)
  1236. {
  1237. int err;
  1238. if (!x86_match_cpu(aesni_cpu_id))
  1239. return -ENODEV;
  1240. #ifdef CONFIG_X86_64
  1241. #ifdef CONFIG_AS_AVX2
  1242. if (boot_cpu_has(X86_FEATURE_AVX2)) {
  1243. pr_info("AVX2 version of gcm_enc/dec engaged.\n");
  1244. aesni_gcm_enc_tfm = aesni_gcm_enc_avx2;
  1245. aesni_gcm_dec_tfm = aesni_gcm_dec_avx2;
  1246. } else
  1247. #endif
  1248. #ifdef CONFIG_AS_AVX
  1249. if (boot_cpu_has(X86_FEATURE_AVX)) {
  1250. pr_info("AVX version of gcm_enc/dec engaged.\n");
  1251. aesni_gcm_enc_tfm = aesni_gcm_enc_avx;
  1252. aesni_gcm_dec_tfm = aesni_gcm_dec_avx;
  1253. } else
  1254. #endif
  1255. {
  1256. pr_info("SSE version of gcm_enc/dec engaged.\n");
  1257. aesni_gcm_enc_tfm = aesni_gcm_enc;
  1258. aesni_gcm_dec_tfm = aesni_gcm_dec;
  1259. }
  1260. aesni_ctr_enc_tfm = aesni_ctr_enc;
  1261. #ifdef CONFIG_AS_AVX
  1262. if (boot_cpu_has(X86_FEATURE_AVX)) {
  1263. /* optimize performance of ctr mode encryption transform */
  1264. aesni_ctr_enc_tfm = aesni_ctr_enc_avx_tfm;
  1265. pr_info("AES CTR mode by8 optimization enabled\n");
  1266. }
  1267. #endif
  1268. #endif
  1269. err = crypto_fpu_init();
  1270. if (err)
  1271. return err;
  1272. err = crypto_register_algs(aesni_algs, ARRAY_SIZE(aesni_algs));
  1273. if (err)
  1274. goto fpu_exit;
  1275. err = crypto_register_aeads(aesni_aead_algs,
  1276. ARRAY_SIZE(aesni_aead_algs));
  1277. if (err)
  1278. goto unregister_algs;
  1279. return err;
  1280. unregister_algs:
  1281. crypto_unregister_algs(aesni_algs, ARRAY_SIZE(aesni_algs));
  1282. fpu_exit:
  1283. crypto_fpu_exit();
  1284. return err;
  1285. }
  1286. static void __exit aesni_exit(void)
  1287. {
  1288. crypto_unregister_aeads(aesni_aead_algs, ARRAY_SIZE(aesni_aead_algs));
  1289. crypto_unregister_algs(aesni_algs, ARRAY_SIZE(aesni_algs));
  1290. crypto_fpu_exit();
  1291. }
  1292. late_initcall(aesni_init);
  1293. module_exit(aesni_exit);
  1294. MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm, Intel AES-NI instructions optimized");
  1295. MODULE_LICENSE("GPL");
  1296. MODULE_ALIAS_CRYPTO("aes");