pci_msi.c 9.7 KB

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  1. /* pci_msi.c: Sparc64 MSI support common layer.
  2. *
  3. * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/slab.h>
  8. #include <linux/irq.h>
  9. #include "pci_impl.h"
  10. static irqreturn_t sparc64_msiq_interrupt(int irq, void *cookie)
  11. {
  12. struct sparc64_msiq_cookie *msiq_cookie = cookie;
  13. struct pci_pbm_info *pbm = msiq_cookie->pbm;
  14. unsigned long msiqid = msiq_cookie->msiqid;
  15. const struct sparc64_msiq_ops *ops;
  16. unsigned long orig_head, head;
  17. int err;
  18. ops = pbm->msi_ops;
  19. err = ops->get_head(pbm, msiqid, &head);
  20. if (unlikely(err < 0))
  21. goto err_get_head;
  22. orig_head = head;
  23. for (;;) {
  24. unsigned long msi;
  25. err = ops->dequeue_msi(pbm, msiqid, &head, &msi);
  26. if (likely(err > 0)) {
  27. unsigned int irq;
  28. irq = pbm->msi_irq_table[msi - pbm->msi_first];
  29. generic_handle_irq(irq);
  30. }
  31. if (unlikely(err < 0))
  32. goto err_dequeue;
  33. if (err == 0)
  34. break;
  35. }
  36. if (likely(head != orig_head)) {
  37. err = ops->set_head(pbm, msiqid, head);
  38. if (unlikely(err < 0))
  39. goto err_set_head;
  40. }
  41. return IRQ_HANDLED;
  42. err_get_head:
  43. printk(KERN_EMERG "MSI: Get head on msiqid[%lu] gives error %d\n",
  44. msiqid, err);
  45. goto err_out;
  46. err_dequeue:
  47. printk(KERN_EMERG "MSI: Dequeue head[%lu] from msiqid[%lu] "
  48. "gives error %d\n",
  49. head, msiqid, err);
  50. goto err_out;
  51. err_set_head:
  52. printk(KERN_EMERG "MSI: Set head[%lu] on msiqid[%lu] "
  53. "gives error %d\n",
  54. head, msiqid, err);
  55. goto err_out;
  56. err_out:
  57. return IRQ_NONE;
  58. }
  59. static u32 pick_msiq(struct pci_pbm_info *pbm)
  60. {
  61. static DEFINE_SPINLOCK(rotor_lock);
  62. unsigned long flags;
  63. u32 ret, rotor;
  64. spin_lock_irqsave(&rotor_lock, flags);
  65. rotor = pbm->msiq_rotor;
  66. ret = pbm->msiq_first + rotor;
  67. if (++rotor >= pbm->msiq_num)
  68. rotor = 0;
  69. pbm->msiq_rotor = rotor;
  70. spin_unlock_irqrestore(&rotor_lock, flags);
  71. return ret;
  72. }
  73. static int alloc_msi(struct pci_pbm_info *pbm)
  74. {
  75. int i;
  76. for (i = 0; i < pbm->msi_num; i++) {
  77. if (!test_and_set_bit(i, pbm->msi_bitmap))
  78. return i + pbm->msi_first;
  79. }
  80. return -ENOENT;
  81. }
  82. static void free_msi(struct pci_pbm_info *pbm, int msi_num)
  83. {
  84. msi_num -= pbm->msi_first;
  85. clear_bit(msi_num, pbm->msi_bitmap);
  86. }
  87. static struct irq_chip msi_irq = {
  88. .name = "PCI-MSI",
  89. .irq_mask = pci_msi_mask_irq,
  90. .irq_unmask = pci_msi_unmask_irq,
  91. .irq_enable = pci_msi_unmask_irq,
  92. .irq_disable = pci_msi_mask_irq,
  93. /* XXX affinity XXX */
  94. };
  95. static int sparc64_setup_msi_irq(unsigned int *irq_p,
  96. struct pci_dev *pdev,
  97. struct msi_desc *entry)
  98. {
  99. struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
  100. const struct sparc64_msiq_ops *ops = pbm->msi_ops;
  101. struct msi_msg msg;
  102. int msi, err;
  103. u32 msiqid;
  104. *irq_p = irq_alloc(0, 0);
  105. err = -ENOMEM;
  106. if (!*irq_p)
  107. goto out_err;
  108. irq_set_chip_and_handler_name(*irq_p, &msi_irq, handle_simple_irq,
  109. "MSI");
  110. err = alloc_msi(pbm);
  111. if (unlikely(err < 0))
  112. goto out_irq_free;
  113. msi = err;
  114. msiqid = pick_msiq(pbm);
  115. err = ops->msi_setup(pbm, msiqid, msi,
  116. (entry->msi_attrib.is_64 ? 1 : 0));
  117. if (err)
  118. goto out_msi_free;
  119. pbm->msi_irq_table[msi - pbm->msi_first] = *irq_p;
  120. if (entry->msi_attrib.is_64) {
  121. msg.address_hi = pbm->msi64_start >> 32;
  122. msg.address_lo = pbm->msi64_start & 0xffffffff;
  123. } else {
  124. msg.address_hi = 0;
  125. msg.address_lo = pbm->msi32_start;
  126. }
  127. msg.data = msi;
  128. irq_set_msi_desc(*irq_p, entry);
  129. pci_write_msi_msg(*irq_p, &msg);
  130. return 0;
  131. out_msi_free:
  132. free_msi(pbm, msi);
  133. out_irq_free:
  134. irq_set_chip(*irq_p, NULL);
  135. irq_free(*irq_p);
  136. *irq_p = 0;
  137. out_err:
  138. return err;
  139. }
  140. static void sparc64_teardown_msi_irq(unsigned int irq,
  141. struct pci_dev *pdev)
  142. {
  143. struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
  144. const struct sparc64_msiq_ops *ops = pbm->msi_ops;
  145. unsigned int msi_num;
  146. int i, err;
  147. for (i = 0; i < pbm->msi_num; i++) {
  148. if (pbm->msi_irq_table[i] == irq)
  149. break;
  150. }
  151. if (i >= pbm->msi_num) {
  152. printk(KERN_ERR "%s: teardown: No MSI for irq %u\n",
  153. pbm->name, irq);
  154. return;
  155. }
  156. msi_num = pbm->msi_first + i;
  157. pbm->msi_irq_table[i] = ~0U;
  158. err = ops->msi_teardown(pbm, msi_num);
  159. if (err) {
  160. printk(KERN_ERR "%s: teardown: ops->teardown() on MSI %u, "
  161. "irq %u, gives error %d\n",
  162. pbm->name, msi_num, irq, err);
  163. return;
  164. }
  165. free_msi(pbm, msi_num);
  166. irq_set_chip(irq, NULL);
  167. irq_free(irq);
  168. }
  169. static int msi_bitmap_alloc(struct pci_pbm_info *pbm)
  170. {
  171. unsigned long size, bits_per_ulong;
  172. bits_per_ulong = sizeof(unsigned long) * 8;
  173. size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1);
  174. size /= 8;
  175. BUG_ON(size % sizeof(unsigned long));
  176. pbm->msi_bitmap = kzalloc(size, GFP_KERNEL);
  177. if (!pbm->msi_bitmap)
  178. return -ENOMEM;
  179. return 0;
  180. }
  181. static void msi_bitmap_free(struct pci_pbm_info *pbm)
  182. {
  183. kfree(pbm->msi_bitmap);
  184. pbm->msi_bitmap = NULL;
  185. }
  186. static int msi_table_alloc(struct pci_pbm_info *pbm)
  187. {
  188. int size, i;
  189. size = pbm->msiq_num * sizeof(struct sparc64_msiq_cookie);
  190. pbm->msiq_irq_cookies = kzalloc(size, GFP_KERNEL);
  191. if (!pbm->msiq_irq_cookies)
  192. return -ENOMEM;
  193. for (i = 0; i < pbm->msiq_num; i++) {
  194. struct sparc64_msiq_cookie *p;
  195. p = &pbm->msiq_irq_cookies[i];
  196. p->pbm = pbm;
  197. p->msiqid = pbm->msiq_first + i;
  198. }
  199. size = pbm->msi_num * sizeof(unsigned int);
  200. pbm->msi_irq_table = kzalloc(size, GFP_KERNEL);
  201. if (!pbm->msi_irq_table) {
  202. kfree(pbm->msiq_irq_cookies);
  203. pbm->msiq_irq_cookies = NULL;
  204. return -ENOMEM;
  205. }
  206. return 0;
  207. }
  208. static void msi_table_free(struct pci_pbm_info *pbm)
  209. {
  210. kfree(pbm->msiq_irq_cookies);
  211. pbm->msiq_irq_cookies = NULL;
  212. kfree(pbm->msi_irq_table);
  213. pbm->msi_irq_table = NULL;
  214. }
  215. static int bringup_one_msi_queue(struct pci_pbm_info *pbm,
  216. const struct sparc64_msiq_ops *ops,
  217. unsigned long msiqid,
  218. unsigned long devino)
  219. {
  220. int irq = ops->msiq_build_irq(pbm, msiqid, devino);
  221. int err, nid;
  222. if (irq < 0)
  223. return irq;
  224. nid = pbm->numa_node;
  225. if (nid != -1) {
  226. cpumask_t numa_mask;
  227. cpumask_copy(&numa_mask, cpumask_of_node(nid));
  228. irq_set_affinity(irq, &numa_mask);
  229. }
  230. err = request_irq(irq, sparc64_msiq_interrupt, 0,
  231. "MSIQ",
  232. &pbm->msiq_irq_cookies[msiqid - pbm->msiq_first]);
  233. if (err)
  234. return err;
  235. return 0;
  236. }
  237. static int sparc64_bringup_msi_queues(struct pci_pbm_info *pbm,
  238. const struct sparc64_msiq_ops *ops)
  239. {
  240. int i;
  241. for (i = 0; i < pbm->msiq_num; i++) {
  242. unsigned long msiqid = i + pbm->msiq_first;
  243. unsigned long devino = i + pbm->msiq_first_devino;
  244. int err;
  245. err = bringup_one_msi_queue(pbm, ops, msiqid, devino);
  246. if (err)
  247. return err;
  248. }
  249. return 0;
  250. }
  251. void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
  252. const struct sparc64_msiq_ops *ops)
  253. {
  254. const u32 *val;
  255. int len;
  256. val = of_get_property(pbm->op->dev.of_node, "#msi-eqs", &len);
  257. if (!val || len != 4)
  258. goto no_msi;
  259. pbm->msiq_num = *val;
  260. if (pbm->msiq_num) {
  261. const struct msiq_prop {
  262. u32 first_msiq;
  263. u32 num_msiq;
  264. u32 first_devino;
  265. } *mqp;
  266. const struct msi_range_prop {
  267. u32 first_msi;
  268. u32 num_msi;
  269. } *mrng;
  270. const struct addr_range_prop {
  271. u32 msi32_high;
  272. u32 msi32_low;
  273. u32 msi32_len;
  274. u32 msi64_high;
  275. u32 msi64_low;
  276. u32 msi64_len;
  277. } *arng;
  278. val = of_get_property(pbm->op->dev.of_node, "msi-eq-size", &len);
  279. if (!val || len != 4)
  280. goto no_msi;
  281. pbm->msiq_ent_count = *val;
  282. mqp = of_get_property(pbm->op->dev.of_node,
  283. "msi-eq-to-devino", &len);
  284. if (!mqp)
  285. mqp = of_get_property(pbm->op->dev.of_node,
  286. "msi-eq-devino", &len);
  287. if (!mqp || len != sizeof(struct msiq_prop))
  288. goto no_msi;
  289. pbm->msiq_first = mqp->first_msiq;
  290. pbm->msiq_first_devino = mqp->first_devino;
  291. val = of_get_property(pbm->op->dev.of_node, "#msi", &len);
  292. if (!val || len != 4)
  293. goto no_msi;
  294. pbm->msi_num = *val;
  295. mrng = of_get_property(pbm->op->dev.of_node, "msi-ranges", &len);
  296. if (!mrng || len != sizeof(struct msi_range_prop))
  297. goto no_msi;
  298. pbm->msi_first = mrng->first_msi;
  299. val = of_get_property(pbm->op->dev.of_node, "msi-data-mask", &len);
  300. if (!val || len != 4)
  301. goto no_msi;
  302. pbm->msi_data_mask = *val;
  303. val = of_get_property(pbm->op->dev.of_node, "msix-data-width", &len);
  304. if (!val || len != 4)
  305. goto no_msi;
  306. pbm->msix_data_width = *val;
  307. arng = of_get_property(pbm->op->dev.of_node, "msi-address-ranges",
  308. &len);
  309. if (!arng || len != sizeof(struct addr_range_prop))
  310. goto no_msi;
  311. pbm->msi32_start = ((u64)arng->msi32_high << 32) |
  312. (u64) arng->msi32_low;
  313. pbm->msi64_start = ((u64)arng->msi64_high << 32) |
  314. (u64) arng->msi64_low;
  315. pbm->msi32_len = arng->msi32_len;
  316. pbm->msi64_len = arng->msi64_len;
  317. if (msi_bitmap_alloc(pbm))
  318. goto no_msi;
  319. if (msi_table_alloc(pbm)) {
  320. msi_bitmap_free(pbm);
  321. goto no_msi;
  322. }
  323. if (ops->msiq_alloc(pbm)) {
  324. msi_table_free(pbm);
  325. msi_bitmap_free(pbm);
  326. goto no_msi;
  327. }
  328. if (sparc64_bringup_msi_queues(pbm, ops)) {
  329. ops->msiq_free(pbm);
  330. msi_table_free(pbm);
  331. msi_bitmap_free(pbm);
  332. goto no_msi;
  333. }
  334. printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] "
  335. "devino[0x%x]\n",
  336. pbm->name,
  337. pbm->msiq_first, pbm->msiq_num,
  338. pbm->msiq_ent_count,
  339. pbm->msiq_first_devino);
  340. printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] "
  341. "width[%u]\n",
  342. pbm->name,
  343. pbm->msi_first, pbm->msi_num, pbm->msi_data_mask,
  344. pbm->msix_data_width);
  345. printk(KERN_INFO "%s: MSI addr32[0x%llx:0x%x] "
  346. "addr64[0x%llx:0x%x]\n",
  347. pbm->name,
  348. pbm->msi32_start, pbm->msi32_len,
  349. pbm->msi64_start, pbm->msi64_len);
  350. printk(KERN_INFO "%s: MSI queues at RA [%016lx]\n",
  351. pbm->name,
  352. __pa(pbm->msi_queues));
  353. pbm->msi_ops = ops;
  354. pbm->setup_msi_irq = sparc64_setup_msi_irq;
  355. pbm->teardown_msi_irq = sparc64_teardown_msi_irq;
  356. }
  357. return;
  358. no_msi:
  359. pbm->msiq_num = 0;
  360. printk(KERN_INFO "%s: No MSI support.\n", pbm->name);
  361. }