icp-native.c 8.1 KB

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  1. /*
  2. * Copyright 2011 IBM Corporation.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation; either version
  7. * 2 of the License, or (at your option) any later version.
  8. *
  9. */
  10. #include <linux/types.h>
  11. #include <linux/kernel.h>
  12. #include <linux/irq.h>
  13. #include <linux/smp.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/init.h>
  16. #include <linux/cpu.h>
  17. #include <linux/of.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/module.h>
  20. #include <asm/prom.h>
  21. #include <asm/io.h>
  22. #include <asm/smp.h>
  23. #include <asm/irq.h>
  24. #include <asm/errno.h>
  25. #include <asm/xics.h>
  26. #include <asm/kvm_ppc.h>
  27. #include <asm/dbell.h>
  28. struct icp_ipl {
  29. union {
  30. u32 word;
  31. u8 bytes[4];
  32. } xirr_poll;
  33. union {
  34. u32 word;
  35. u8 bytes[4];
  36. } xirr;
  37. u32 dummy;
  38. union {
  39. u32 word;
  40. u8 bytes[4];
  41. } qirr;
  42. u32 link_a;
  43. u32 link_b;
  44. u32 link_c;
  45. };
  46. static struct icp_ipl __iomem *icp_native_regs[NR_CPUS];
  47. static inline unsigned int icp_native_get_xirr(void)
  48. {
  49. int cpu = smp_processor_id();
  50. unsigned int xirr;
  51. /* Handled an interrupt latched by KVM */
  52. xirr = kvmppc_get_xics_latch();
  53. if (xirr)
  54. return xirr;
  55. return in_be32(&icp_native_regs[cpu]->xirr.word);
  56. }
  57. static inline void icp_native_set_xirr(unsigned int value)
  58. {
  59. int cpu = smp_processor_id();
  60. out_be32(&icp_native_regs[cpu]->xirr.word, value);
  61. }
  62. static inline void icp_native_set_cppr(u8 value)
  63. {
  64. int cpu = smp_processor_id();
  65. out_8(&icp_native_regs[cpu]->xirr.bytes[0], value);
  66. }
  67. static inline void icp_native_set_qirr(int n_cpu, u8 value)
  68. {
  69. out_8(&icp_native_regs[n_cpu]->qirr.bytes[0], value);
  70. }
  71. static void icp_native_set_cpu_priority(unsigned char cppr)
  72. {
  73. xics_set_base_cppr(cppr);
  74. icp_native_set_cppr(cppr);
  75. iosync();
  76. }
  77. void icp_native_eoi(struct irq_data *d)
  78. {
  79. unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
  80. iosync();
  81. icp_native_set_xirr((xics_pop_cppr() << 24) | hw_irq);
  82. }
  83. static void icp_native_teardown_cpu(void)
  84. {
  85. int cpu = smp_processor_id();
  86. /* Clear any pending IPI */
  87. icp_native_set_qirr(cpu, 0xff);
  88. }
  89. static void icp_native_flush_ipi(void)
  90. {
  91. /* We take the ipi irq but and never return so we
  92. * need to EOI the IPI, but want to leave our priority 0
  93. *
  94. * should we check all the other interrupts too?
  95. * should we be flagging idle loop instead?
  96. * or creating some task to be scheduled?
  97. */
  98. icp_native_set_xirr((0x00 << 24) | XICS_IPI);
  99. }
  100. static unsigned int icp_native_get_irq(void)
  101. {
  102. unsigned int xirr = icp_native_get_xirr();
  103. unsigned int vec = xirr & 0x00ffffff;
  104. unsigned int irq;
  105. if (vec == XICS_IRQ_SPURIOUS)
  106. return 0;
  107. irq = irq_find_mapping(xics_host, vec);
  108. if (likely(irq)) {
  109. xics_push_cppr(vec);
  110. return irq;
  111. }
  112. /* We don't have a linux mapping, so have rtas mask it. */
  113. xics_mask_unknown_vec(vec);
  114. /* We might learn about it later, so EOI it */
  115. icp_native_set_xirr(xirr);
  116. return 0;
  117. }
  118. #ifdef CONFIG_SMP
  119. static void icp_native_cause_ipi(int cpu, unsigned long data)
  120. {
  121. kvmppc_set_host_ipi(cpu, 1);
  122. #ifdef CONFIG_PPC_DOORBELL
  123. if (cpu_has_feature(CPU_FTR_DBELL)) {
  124. if (cpumask_test_cpu(cpu, cpu_sibling_mask(get_cpu()))) {
  125. doorbell_cause_ipi(cpu, data);
  126. put_cpu();
  127. return;
  128. }
  129. put_cpu();
  130. }
  131. #endif
  132. icp_native_set_qirr(cpu, IPI_PRIORITY);
  133. }
  134. #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
  135. void icp_native_cause_ipi_rm(int cpu)
  136. {
  137. /*
  138. * Currently not used to send IPIs to another CPU
  139. * on the same core. Only caller is KVM real mode.
  140. * Need the physical address of the XICS to be
  141. * previously saved in kvm_hstate in the paca.
  142. */
  143. unsigned long xics_phys;
  144. /*
  145. * Just like the cause_ipi functions, it is required to
  146. * include a full barrier (out8 includes a sync) before
  147. * causing the IPI.
  148. */
  149. xics_phys = paca[cpu].kvm_hstate.xics_phys;
  150. out_rm8((u8 *)(xics_phys + XICS_MFRR), IPI_PRIORITY);
  151. }
  152. #endif
  153. /*
  154. * Called when an interrupt is received on an off-line CPU to
  155. * clear the interrupt, so that the CPU can go back to nap mode.
  156. */
  157. void icp_native_flush_interrupt(void)
  158. {
  159. unsigned int xirr = icp_native_get_xirr();
  160. unsigned int vec = xirr & 0x00ffffff;
  161. if (vec == XICS_IRQ_SPURIOUS)
  162. return;
  163. if (vec == XICS_IPI) {
  164. /* Clear pending IPI */
  165. int cpu = smp_processor_id();
  166. kvmppc_set_host_ipi(cpu, 0);
  167. icp_native_set_qirr(cpu, 0xff);
  168. } else {
  169. pr_err("XICS: hw interrupt 0x%x to offline cpu, disabling\n",
  170. vec);
  171. xics_mask_unknown_vec(vec);
  172. }
  173. /* EOI the interrupt */
  174. icp_native_set_xirr(xirr);
  175. }
  176. void xics_wake_cpu(int cpu)
  177. {
  178. icp_native_set_qirr(cpu, IPI_PRIORITY);
  179. }
  180. EXPORT_SYMBOL_GPL(xics_wake_cpu);
  181. static irqreturn_t icp_native_ipi_action(int irq, void *dev_id)
  182. {
  183. int cpu = smp_processor_id();
  184. kvmppc_set_host_ipi(cpu, 0);
  185. icp_native_set_qirr(cpu, 0xff);
  186. return smp_ipi_demux();
  187. }
  188. #endif /* CONFIG_SMP */
  189. static int __init icp_native_map_one_cpu(int hw_id, unsigned long addr,
  190. unsigned long size)
  191. {
  192. char *rname;
  193. int i, cpu = -1;
  194. /* This may look gross but it's good enough for now, we don't quite
  195. * have a hard -> linux processor id matching.
  196. */
  197. for_each_possible_cpu(i) {
  198. if (!cpu_present(i))
  199. continue;
  200. if (hw_id == get_hard_smp_processor_id(i)) {
  201. cpu = i;
  202. break;
  203. }
  204. }
  205. /* Fail, skip that CPU. Don't print, it's normal, some XICS come up
  206. * with way more entries in there than you have CPUs
  207. */
  208. if (cpu == -1)
  209. return 0;
  210. rname = kasprintf(GFP_KERNEL, "CPU %d [0x%x] Interrupt Presentation",
  211. cpu, hw_id);
  212. if (!request_mem_region(addr, size, rname)) {
  213. pr_warning("icp_native: Could not reserve ICP MMIO"
  214. " for CPU %d, interrupt server #0x%x\n",
  215. cpu, hw_id);
  216. return -EBUSY;
  217. }
  218. icp_native_regs[cpu] = ioremap(addr, size);
  219. kvmppc_set_xics_phys(cpu, addr);
  220. if (!icp_native_regs[cpu]) {
  221. pr_warning("icp_native: Failed ioremap for CPU %d, "
  222. "interrupt server #0x%x, addr %#lx\n",
  223. cpu, hw_id, addr);
  224. release_mem_region(addr, size);
  225. return -ENOMEM;
  226. }
  227. return 0;
  228. }
  229. static int __init icp_native_init_one_node(struct device_node *np,
  230. unsigned int *indx)
  231. {
  232. unsigned int ilen;
  233. const __be32 *ireg;
  234. int i;
  235. int reg_tuple_size;
  236. int num_servers = 0;
  237. /* This code does the theorically broken assumption that the interrupt
  238. * server numbers are the same as the hard CPU numbers.
  239. * This happens to be the case so far but we are playing with fire...
  240. * should be fixed one of these days. -BenH.
  241. */
  242. ireg = of_get_property(np, "ibm,interrupt-server-ranges", &ilen);
  243. /* Do that ever happen ? we'll know soon enough... but even good'old
  244. * f80 does have that property ..
  245. */
  246. WARN_ON((ireg == NULL) || (ilen != 2*sizeof(u32)));
  247. if (ireg) {
  248. *indx = of_read_number(ireg, 1);
  249. if (ilen >= 2*sizeof(u32))
  250. num_servers = of_read_number(ireg + 1, 1);
  251. }
  252. ireg = of_get_property(np, "reg", &ilen);
  253. if (!ireg) {
  254. pr_err("icp_native: Can't find interrupt reg property");
  255. return -1;
  256. }
  257. reg_tuple_size = (of_n_addr_cells(np) + of_n_size_cells(np)) * 4;
  258. if (((ilen % reg_tuple_size) != 0)
  259. || (num_servers && (num_servers != (ilen / reg_tuple_size)))) {
  260. pr_err("icp_native: ICP reg len (%d) != num servers (%d)",
  261. ilen / reg_tuple_size, num_servers);
  262. return -1;
  263. }
  264. for (i = 0; i < (ilen / reg_tuple_size); i++) {
  265. struct resource r;
  266. int err;
  267. err = of_address_to_resource(np, i, &r);
  268. if (err) {
  269. pr_err("icp_native: Could not translate ICP MMIO"
  270. " for interrupt server 0x%x (%d)\n", *indx, err);
  271. return -1;
  272. }
  273. if (icp_native_map_one_cpu(*indx, r.start, resource_size(&r)))
  274. return -1;
  275. (*indx)++;
  276. }
  277. return 0;
  278. }
  279. static const struct icp_ops icp_native_ops = {
  280. .get_irq = icp_native_get_irq,
  281. .eoi = icp_native_eoi,
  282. .set_priority = icp_native_set_cpu_priority,
  283. .teardown_cpu = icp_native_teardown_cpu,
  284. .flush_ipi = icp_native_flush_ipi,
  285. #ifdef CONFIG_SMP
  286. .ipi_action = icp_native_ipi_action,
  287. .cause_ipi = icp_native_cause_ipi,
  288. #endif
  289. };
  290. int __init icp_native_init(void)
  291. {
  292. struct device_node *np;
  293. u32 indx = 0;
  294. int found = 0;
  295. for_each_compatible_node(np, NULL, "ibm,ppc-xicp")
  296. if (icp_native_init_one_node(np, &indx) == 0)
  297. found = 1;
  298. if (!found) {
  299. for_each_node_by_type(np,
  300. "PowerPC-External-Interrupt-Presentation") {
  301. if (icp_native_init_one_node(np, &indx) == 0)
  302. found = 1;
  303. }
  304. }
  305. if (found == 0)
  306. return -ENODEV;
  307. icp_ops = &icp_native_ops;
  308. return 0;
  309. }