mce_power.c 9.8 KB

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  1. /*
  2. * Machine check exception handling CPU-side for power7 and power8
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * Copyright 2013 IBM Corporation
  19. * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
  20. */
  21. #undef DEBUG
  22. #define pr_fmt(fmt) "mce_power: " fmt
  23. #include <linux/types.h>
  24. #include <linux/ptrace.h>
  25. #include <asm/mmu.h>
  26. #include <asm/mce.h>
  27. #include <asm/machdep.h>
  28. static void flush_tlb_206(unsigned int num_sets, unsigned int action)
  29. {
  30. unsigned long rb;
  31. unsigned int i;
  32. switch (action) {
  33. case TLB_INVAL_SCOPE_GLOBAL:
  34. rb = TLBIEL_INVAL_SET;
  35. break;
  36. case TLB_INVAL_SCOPE_LPID:
  37. rb = TLBIEL_INVAL_SET_LPID;
  38. break;
  39. default:
  40. BUG();
  41. break;
  42. }
  43. asm volatile("ptesync" : : : "memory");
  44. for (i = 0; i < num_sets; i++) {
  45. asm volatile("tlbiel %0" : : "r" (rb));
  46. rb += 1 << TLBIEL_INVAL_SET_SHIFT;
  47. }
  48. asm volatile("ptesync" : : : "memory");
  49. }
  50. /*
  51. * Generic routines to flush TLB on POWER processors. These routines
  52. * are used as flush_tlb hook in the cpu_spec.
  53. *
  54. * action => TLB_INVAL_SCOPE_GLOBAL: Invalidate all TLBs.
  55. * TLB_INVAL_SCOPE_LPID: Invalidate TLB for current LPID.
  56. */
  57. void __flush_tlb_power7(unsigned int action)
  58. {
  59. flush_tlb_206(POWER7_TLB_SETS, action);
  60. }
  61. void __flush_tlb_power8(unsigned int action)
  62. {
  63. flush_tlb_206(POWER8_TLB_SETS, action);
  64. }
  65. void __flush_tlb_power9(unsigned int action)
  66. {
  67. if (radix_enabled())
  68. flush_tlb_206(POWER9_TLB_SETS_RADIX, action);
  69. flush_tlb_206(POWER9_TLB_SETS_HASH, action);
  70. }
  71. /* flush SLBs and reload */
  72. #ifdef CONFIG_PPC_STD_MMU_64
  73. static void flush_and_reload_slb(void)
  74. {
  75. struct slb_shadow *slb;
  76. unsigned long i, n;
  77. /* Invalidate all SLBs */
  78. asm volatile("slbmte %0,%0; slbia" : : "r" (0));
  79. #ifdef CONFIG_KVM_BOOK3S_HANDLER
  80. /*
  81. * If machine check is hit when in guest or in transition, we will
  82. * only flush the SLBs and continue.
  83. */
  84. if (get_paca()->kvm_hstate.in_guest)
  85. return;
  86. #endif
  87. /* For host kernel, reload the SLBs from shadow SLB buffer. */
  88. slb = get_slb_shadow();
  89. if (!slb)
  90. return;
  91. n = min_t(u32, be32_to_cpu(slb->persistent), SLB_MIN_SIZE);
  92. /* Load up the SLB entries from shadow SLB */
  93. for (i = 0; i < n; i++) {
  94. unsigned long rb = be64_to_cpu(slb->save_area[i].esid);
  95. unsigned long rs = be64_to_cpu(slb->save_area[i].vsid);
  96. rb = (rb & ~0xFFFul) | i;
  97. asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb));
  98. }
  99. }
  100. #endif
  101. static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
  102. {
  103. long handled = 1;
  104. /*
  105. * flush and reload SLBs for SLB errors and flush TLBs for TLB errors.
  106. * reset the error bits whenever we handle them so that at the end
  107. * we can check whether we handled all of them or not.
  108. * */
  109. #ifdef CONFIG_PPC_STD_MMU_64
  110. if (dsisr & slb_error_bits) {
  111. flush_and_reload_slb();
  112. /* reset error bits */
  113. dsisr &= ~(slb_error_bits);
  114. }
  115. if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) {
  116. if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
  117. cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL);
  118. /* reset error bits */
  119. dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB;
  120. }
  121. #endif
  122. /* Any other errors we don't understand? */
  123. if (dsisr & 0xffffffffUL)
  124. handled = 0;
  125. return handled;
  126. }
  127. static long mce_handle_derror_p7(uint64_t dsisr)
  128. {
  129. return mce_handle_derror(dsisr, P7_DSISR_MC_SLB_ERRORS);
  130. }
  131. static long mce_handle_common_ierror(uint64_t srr1)
  132. {
  133. long handled = 0;
  134. switch (P7_SRR1_MC_IFETCH(srr1)) {
  135. case 0:
  136. break;
  137. #ifdef CONFIG_PPC_STD_MMU_64
  138. case P7_SRR1_MC_IFETCH_SLB_PARITY:
  139. case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:
  140. /* flush and reload SLBs for SLB errors. */
  141. flush_and_reload_slb();
  142. handled = 1;
  143. break;
  144. case P7_SRR1_MC_IFETCH_TLB_MULTIHIT:
  145. if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {
  146. cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL);
  147. handled = 1;
  148. }
  149. break;
  150. #endif
  151. default:
  152. break;
  153. }
  154. return handled;
  155. }
  156. static long mce_handle_ierror_p7(uint64_t srr1)
  157. {
  158. long handled = 0;
  159. handled = mce_handle_common_ierror(srr1);
  160. #ifdef CONFIG_PPC_STD_MMU_64
  161. if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) {
  162. flush_and_reload_slb();
  163. handled = 1;
  164. }
  165. #endif
  166. return handled;
  167. }
  168. static void mce_get_common_ierror(struct mce_error_info *mce_err, uint64_t srr1)
  169. {
  170. switch (P7_SRR1_MC_IFETCH(srr1)) {
  171. case P7_SRR1_MC_IFETCH_SLB_PARITY:
  172. mce_err->error_type = MCE_ERROR_TYPE_SLB;
  173. mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
  174. break;
  175. case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:
  176. mce_err->error_type = MCE_ERROR_TYPE_SLB;
  177. mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
  178. break;
  179. case P7_SRR1_MC_IFETCH_TLB_MULTIHIT:
  180. mce_err->error_type = MCE_ERROR_TYPE_TLB;
  181. mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
  182. break;
  183. case P7_SRR1_MC_IFETCH_UE:
  184. case P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL:
  185. mce_err->error_type = MCE_ERROR_TYPE_UE;
  186. mce_err->u.ue_error_type = MCE_UE_ERROR_IFETCH;
  187. break;
  188. case P7_SRR1_MC_IFETCH_UE_TLB_RELOAD:
  189. mce_err->error_type = MCE_ERROR_TYPE_UE;
  190. mce_err->u.ue_error_type =
  191. MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH;
  192. break;
  193. }
  194. }
  195. static void mce_get_ierror_p7(struct mce_error_info *mce_err, uint64_t srr1)
  196. {
  197. mce_get_common_ierror(mce_err, srr1);
  198. if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) {
  199. mce_err->error_type = MCE_ERROR_TYPE_SLB;
  200. mce_err->u.slb_error_type = MCE_SLB_ERROR_INDETERMINATE;
  201. }
  202. }
  203. static void mce_get_derror_p7(struct mce_error_info *mce_err, uint64_t dsisr)
  204. {
  205. if (dsisr & P7_DSISR_MC_UE) {
  206. mce_err->error_type = MCE_ERROR_TYPE_UE;
  207. mce_err->u.ue_error_type = MCE_UE_ERROR_LOAD_STORE;
  208. } else if (dsisr & P7_DSISR_MC_UE_TABLEWALK) {
  209. mce_err->error_type = MCE_ERROR_TYPE_UE;
  210. mce_err->u.ue_error_type =
  211. MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
  212. } else if (dsisr & P7_DSISR_MC_ERAT_MULTIHIT) {
  213. mce_err->error_type = MCE_ERROR_TYPE_ERAT;
  214. mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
  215. } else if (dsisr & P7_DSISR_MC_SLB_MULTIHIT) {
  216. mce_err->error_type = MCE_ERROR_TYPE_SLB;
  217. mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
  218. } else if (dsisr & P7_DSISR_MC_SLB_PARITY_MFSLB) {
  219. mce_err->error_type = MCE_ERROR_TYPE_SLB;
  220. mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
  221. } else if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) {
  222. mce_err->error_type = MCE_ERROR_TYPE_TLB;
  223. mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
  224. } else if (dsisr & P7_DSISR_MC_SLB_MULTIHIT_PARITY) {
  225. mce_err->error_type = MCE_ERROR_TYPE_SLB;
  226. mce_err->u.slb_error_type = MCE_SLB_ERROR_INDETERMINATE;
  227. }
  228. }
  229. static long mce_handle_ue_error(struct pt_regs *regs)
  230. {
  231. long handled = 0;
  232. /*
  233. * On specific SCOM read via MMIO we may get a machine check
  234. * exception with SRR0 pointing inside opal. If that is the
  235. * case OPAL may have recovery address to re-read SCOM data in
  236. * different way and hence we can recover from this MC.
  237. */
  238. if (ppc_md.mce_check_early_recovery) {
  239. if (ppc_md.mce_check_early_recovery(regs))
  240. handled = 1;
  241. }
  242. return handled;
  243. }
  244. long __machine_check_early_realmode_p7(struct pt_regs *regs)
  245. {
  246. uint64_t srr1, nip, addr;
  247. long handled = 1;
  248. struct mce_error_info mce_error_info = { 0 };
  249. srr1 = regs->msr;
  250. nip = regs->nip;
  251. /*
  252. * Handle memory errors depending whether this was a load/store or
  253. * ifetch exception. Also, populate the mce error_type and
  254. * type-specific error_type from either SRR1 or DSISR, depending
  255. * whether this was a load/store or ifetch exception
  256. */
  257. if (P7_SRR1_MC_LOADSTORE(srr1)) {
  258. handled = mce_handle_derror_p7(regs->dsisr);
  259. mce_get_derror_p7(&mce_error_info, regs->dsisr);
  260. addr = regs->dar;
  261. } else {
  262. handled = mce_handle_ierror_p7(srr1);
  263. mce_get_ierror_p7(&mce_error_info, srr1);
  264. addr = regs->nip;
  265. }
  266. /* Handle UE error. */
  267. if (mce_error_info.error_type == MCE_ERROR_TYPE_UE)
  268. handled = mce_handle_ue_error(regs);
  269. save_mce_event(regs, handled, &mce_error_info, nip, addr);
  270. return handled;
  271. }
  272. static void mce_get_ierror_p8(struct mce_error_info *mce_err, uint64_t srr1)
  273. {
  274. mce_get_common_ierror(mce_err, srr1);
  275. if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) {
  276. mce_err->error_type = MCE_ERROR_TYPE_ERAT;
  277. mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
  278. }
  279. }
  280. static void mce_get_derror_p8(struct mce_error_info *mce_err, uint64_t dsisr)
  281. {
  282. mce_get_derror_p7(mce_err, dsisr);
  283. if (dsisr & P8_DSISR_MC_ERAT_MULTIHIT_SEC) {
  284. mce_err->error_type = MCE_ERROR_TYPE_ERAT;
  285. mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
  286. }
  287. }
  288. static long mce_handle_ierror_p8(uint64_t srr1)
  289. {
  290. long handled = 0;
  291. handled = mce_handle_common_ierror(srr1);
  292. #ifdef CONFIG_PPC_STD_MMU_64
  293. if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) {
  294. flush_and_reload_slb();
  295. handled = 1;
  296. }
  297. #endif
  298. return handled;
  299. }
  300. static long mce_handle_derror_p8(uint64_t dsisr)
  301. {
  302. return mce_handle_derror(dsisr, P8_DSISR_MC_SLB_ERRORS);
  303. }
  304. long __machine_check_early_realmode_p8(struct pt_regs *regs)
  305. {
  306. uint64_t srr1, nip, addr;
  307. long handled = 1;
  308. struct mce_error_info mce_error_info = { 0 };
  309. srr1 = regs->msr;
  310. nip = regs->nip;
  311. if (P7_SRR1_MC_LOADSTORE(srr1)) {
  312. handled = mce_handle_derror_p8(regs->dsisr);
  313. mce_get_derror_p8(&mce_error_info, regs->dsisr);
  314. addr = regs->dar;
  315. } else {
  316. handled = mce_handle_ierror_p8(srr1);
  317. mce_get_ierror_p8(&mce_error_info, srr1);
  318. addr = regs->nip;
  319. }
  320. /* Handle UE error. */
  321. if (mce_error_info.error_type == MCE_ERROR_TYPE_UE)
  322. handled = mce_handle_ue_error(regs);
  323. save_mce_event(regs, handled, &mce_error_info, nip, addr);
  324. return handled;
  325. }