mce.h 5.8 KB

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  1. /*
  2. * Machine check exception header file.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * Copyright 2013 IBM Corporation
  19. * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
  20. */
  21. #ifndef __ASM_PPC64_MCE_H__
  22. #define __ASM_PPC64_MCE_H__
  23. #include <linux/bitops.h>
  24. /*
  25. * Machine Check bits on power7 and power8
  26. */
  27. #define P7_SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) /* P8 too */
  28. /* SRR1 bits for machine check (On Power7 and Power8) */
  29. #define P7_SRR1_MC_IFETCH(srr1) ((srr1) & PPC_BITMASK(43, 45)) /* P8 too */
  30. #define P7_SRR1_MC_IFETCH_UE (0x1 << PPC_BITLSHIFT(45)) /* P8 too */
  31. #define P7_SRR1_MC_IFETCH_SLB_PARITY (0x2 << PPC_BITLSHIFT(45)) /* P8 too */
  32. #define P7_SRR1_MC_IFETCH_SLB_MULTIHIT (0x3 << PPC_BITLSHIFT(45)) /* P8 too */
  33. #define P7_SRR1_MC_IFETCH_SLB_BOTH (0x4 << PPC_BITLSHIFT(45))
  34. #define P7_SRR1_MC_IFETCH_TLB_MULTIHIT (0x5 << PPC_BITLSHIFT(45)) /* P8 too */
  35. #define P7_SRR1_MC_IFETCH_UE_TLB_RELOAD (0x6 << PPC_BITLSHIFT(45)) /* P8 too */
  36. #define P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL (0x7 << PPC_BITLSHIFT(45))
  37. /* SRR1 bits for machine check (On Power8) */
  38. #define P8_SRR1_MC_IFETCH_ERAT_MULTIHIT (0x4 << PPC_BITLSHIFT(45))
  39. /* DSISR bits for machine check (On Power7 and Power8) */
  40. #define P7_DSISR_MC_UE (PPC_BIT(48)) /* P8 too */
  41. #define P7_DSISR_MC_UE_TABLEWALK (PPC_BIT(49)) /* P8 too */
  42. #define P7_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52)) /* P8 too */
  43. #define P7_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53)) /* P8 too */
  44. #define P7_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55)) /* P8 too */
  45. #define P7_DSISR_MC_SLB_MULTIHIT (PPC_BIT(56)) /* P8 too */
  46. #define P7_DSISR_MC_SLB_MULTIHIT_PARITY (PPC_BIT(57)) /* P8 too */
  47. /*
  48. * DSISR bits for machine check (Power8) in addition to above.
  49. * Secondary DERAT Multihit
  50. */
  51. #define P8_DSISR_MC_ERAT_MULTIHIT_SEC (PPC_BIT(54))
  52. /* SLB error bits */
  53. #define P7_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_ERAT_MULTIHIT | \
  54. P7_DSISR_MC_SLB_PARITY_MFSLB | \
  55. P7_DSISR_MC_SLB_MULTIHIT | \
  56. P7_DSISR_MC_SLB_MULTIHIT_PARITY)
  57. #define P8_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_SLB_ERRORS | \
  58. P8_DSISR_MC_ERAT_MULTIHIT_SEC)
  59. enum MCE_Version {
  60. MCE_V1 = 1,
  61. };
  62. enum MCE_Severity {
  63. MCE_SEV_NO_ERROR = 0,
  64. MCE_SEV_WARNING = 1,
  65. MCE_SEV_ERROR_SYNC = 2,
  66. MCE_SEV_FATAL = 3,
  67. };
  68. enum MCE_Disposition {
  69. MCE_DISPOSITION_RECOVERED = 0,
  70. MCE_DISPOSITION_NOT_RECOVERED = 1,
  71. };
  72. enum MCE_Initiator {
  73. MCE_INITIATOR_UNKNOWN = 0,
  74. MCE_INITIATOR_CPU = 1,
  75. };
  76. enum MCE_ErrorType {
  77. MCE_ERROR_TYPE_UNKNOWN = 0,
  78. MCE_ERROR_TYPE_UE = 1,
  79. MCE_ERROR_TYPE_SLB = 2,
  80. MCE_ERROR_TYPE_ERAT = 3,
  81. MCE_ERROR_TYPE_TLB = 4,
  82. };
  83. enum MCE_UeErrorType {
  84. MCE_UE_ERROR_INDETERMINATE = 0,
  85. MCE_UE_ERROR_IFETCH = 1,
  86. MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
  87. MCE_UE_ERROR_LOAD_STORE = 3,
  88. MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
  89. };
  90. enum MCE_SlbErrorType {
  91. MCE_SLB_ERROR_INDETERMINATE = 0,
  92. MCE_SLB_ERROR_PARITY = 1,
  93. MCE_SLB_ERROR_MULTIHIT = 2,
  94. };
  95. enum MCE_EratErrorType {
  96. MCE_ERAT_ERROR_INDETERMINATE = 0,
  97. MCE_ERAT_ERROR_PARITY = 1,
  98. MCE_ERAT_ERROR_MULTIHIT = 2,
  99. };
  100. enum MCE_TlbErrorType {
  101. MCE_TLB_ERROR_INDETERMINATE = 0,
  102. MCE_TLB_ERROR_PARITY = 1,
  103. MCE_TLB_ERROR_MULTIHIT = 2,
  104. };
  105. struct machine_check_event {
  106. enum MCE_Version version:8; /* 0x00 */
  107. uint8_t in_use; /* 0x01 */
  108. enum MCE_Severity severity:8; /* 0x02 */
  109. enum MCE_Initiator initiator:8; /* 0x03 */
  110. enum MCE_ErrorType error_type:8; /* 0x04 */
  111. enum MCE_Disposition disposition:8; /* 0x05 */
  112. uint8_t reserved_1[2]; /* 0x06 */
  113. uint64_t gpr3; /* 0x08 */
  114. uint64_t srr0; /* 0x10 */
  115. uint64_t srr1; /* 0x18 */
  116. union { /* 0x20 */
  117. struct {
  118. enum MCE_UeErrorType ue_error_type:8;
  119. uint8_t effective_address_provided;
  120. uint8_t physical_address_provided;
  121. uint8_t reserved_1[5];
  122. uint64_t effective_address;
  123. uint64_t physical_address;
  124. uint8_t reserved_2[8];
  125. } ue_error;
  126. struct {
  127. enum MCE_SlbErrorType slb_error_type:8;
  128. uint8_t effective_address_provided;
  129. uint8_t reserved_1[6];
  130. uint64_t effective_address;
  131. uint8_t reserved_2[16];
  132. } slb_error;
  133. struct {
  134. enum MCE_EratErrorType erat_error_type:8;
  135. uint8_t effective_address_provided;
  136. uint8_t reserved_1[6];
  137. uint64_t effective_address;
  138. uint8_t reserved_2[16];
  139. } erat_error;
  140. struct {
  141. enum MCE_TlbErrorType tlb_error_type:8;
  142. uint8_t effective_address_provided;
  143. uint8_t reserved_1[6];
  144. uint64_t effective_address;
  145. uint8_t reserved_2[16];
  146. } tlb_error;
  147. } u;
  148. };
  149. struct mce_error_info {
  150. enum MCE_ErrorType error_type:8;
  151. union {
  152. enum MCE_UeErrorType ue_error_type:8;
  153. enum MCE_SlbErrorType slb_error_type:8;
  154. enum MCE_EratErrorType erat_error_type:8;
  155. enum MCE_TlbErrorType tlb_error_type:8;
  156. } u;
  157. uint8_t reserved[2];
  158. };
  159. #define MAX_MC_EVT 100
  160. /* Release flags for get_mce_event() */
  161. #define MCE_EVENT_RELEASE true
  162. #define MCE_EVENT_DONTRELEASE false
  163. extern void save_mce_event(struct pt_regs *regs, long handled,
  164. struct mce_error_info *mce_err, uint64_t nip,
  165. uint64_t addr);
  166. extern int get_mce_event(struct machine_check_event *mce, bool release);
  167. extern void release_mce_event(void);
  168. extern void machine_check_queue_event(void);
  169. extern void machine_check_print_event_info(struct machine_check_event *evt);
  170. extern uint64_t get_mce_fault_addr(struct machine_check_event *evt);
  171. #endif /* __ASM_PPC64_MCE_H__ */