intc.c 5.0 KB

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  1. /*
  2. * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
  3. * Copyright (C) 2012-2013 Xilinx, Inc.
  4. * Copyright (C) 2007-2009 PetaLogix
  5. * Copyright (C) 2006 Atmark Techno, Inc.
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <linux/irqdomain.h>
  12. #include <linux/irq.h>
  13. #include <linux/irqchip.h>
  14. #include <linux/of_address.h>
  15. #include <linux/io.h>
  16. #include <linux/bug.h>
  17. static void __iomem *intc_baseaddr;
  18. /* No one else should require these constants, so define them locally here. */
  19. #define ISR 0x00 /* Interrupt Status Register */
  20. #define IPR 0x04 /* Interrupt Pending Register */
  21. #define IER 0x08 /* Interrupt Enable Register */
  22. #define IAR 0x0c /* Interrupt Acknowledge Register */
  23. #define SIE 0x10 /* Set Interrupt Enable bits */
  24. #define CIE 0x14 /* Clear Interrupt Enable bits */
  25. #define IVR 0x18 /* Interrupt Vector Register */
  26. #define MER 0x1c /* Master Enable Register */
  27. #define MER_ME (1<<0)
  28. #define MER_HIE (1<<1)
  29. static unsigned int (*read_fn)(void __iomem *);
  30. static void (*write_fn)(u32, void __iomem *);
  31. static void intc_write32(u32 val, void __iomem *addr)
  32. {
  33. iowrite32(val, addr);
  34. }
  35. static unsigned int intc_read32(void __iomem *addr)
  36. {
  37. return ioread32(addr);
  38. }
  39. static void intc_write32_be(u32 val, void __iomem *addr)
  40. {
  41. iowrite32be(val, addr);
  42. }
  43. static unsigned int intc_read32_be(void __iomem *addr)
  44. {
  45. return ioread32be(addr);
  46. }
  47. static void intc_enable_or_unmask(struct irq_data *d)
  48. {
  49. unsigned long mask = 1 << d->hwirq;
  50. pr_debug("enable_or_unmask: %ld\n", d->hwirq);
  51. /* ack level irqs because they can't be acked during
  52. * ack function since the handle_level_irq function
  53. * acks the irq before calling the interrupt handler
  54. */
  55. if (irqd_is_level_type(d))
  56. write_fn(mask, intc_baseaddr + IAR);
  57. write_fn(mask, intc_baseaddr + SIE);
  58. }
  59. static void intc_disable_or_mask(struct irq_data *d)
  60. {
  61. pr_debug("disable: %ld\n", d->hwirq);
  62. write_fn(1 << d->hwirq, intc_baseaddr + CIE);
  63. }
  64. static void intc_ack(struct irq_data *d)
  65. {
  66. pr_debug("ack: %ld\n", d->hwirq);
  67. write_fn(1 << d->hwirq, intc_baseaddr + IAR);
  68. }
  69. static void intc_mask_ack(struct irq_data *d)
  70. {
  71. unsigned long mask = 1 << d->hwirq;
  72. pr_debug("disable_and_ack: %ld\n", d->hwirq);
  73. write_fn(mask, intc_baseaddr + CIE);
  74. write_fn(mask, intc_baseaddr + IAR);
  75. }
  76. static struct irq_chip intc_dev = {
  77. .name = "Xilinx INTC",
  78. .irq_unmask = intc_enable_or_unmask,
  79. .irq_mask = intc_disable_or_mask,
  80. .irq_ack = intc_ack,
  81. .irq_mask_ack = intc_mask_ack,
  82. };
  83. static struct irq_domain *root_domain;
  84. unsigned int get_irq(void)
  85. {
  86. unsigned int hwirq, irq = -1;
  87. hwirq = read_fn(intc_baseaddr + IVR);
  88. if (hwirq != -1U)
  89. irq = irq_find_mapping(root_domain, hwirq);
  90. pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq);
  91. return irq;
  92. }
  93. static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
  94. {
  95. u32 intr_mask = (u32)d->host_data;
  96. if (intr_mask & (1 << hw)) {
  97. irq_set_chip_and_handler_name(irq, &intc_dev,
  98. handle_edge_irq, "edge");
  99. irq_clear_status_flags(irq, IRQ_LEVEL);
  100. } else {
  101. irq_set_chip_and_handler_name(irq, &intc_dev,
  102. handle_level_irq, "level");
  103. irq_set_status_flags(irq, IRQ_LEVEL);
  104. }
  105. return 0;
  106. }
  107. static const struct irq_domain_ops xintc_irq_domain_ops = {
  108. .xlate = irq_domain_xlate_onetwocell,
  109. .map = xintc_map,
  110. };
  111. static int __init xilinx_intc_of_init(struct device_node *intc,
  112. struct device_node *parent)
  113. {
  114. u32 nr_irq, intr_mask;
  115. int ret;
  116. intc_baseaddr = of_iomap(intc, 0);
  117. BUG_ON(!intc_baseaddr);
  118. ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq);
  119. if (ret < 0) {
  120. pr_err("%s: unable to read xlnx,num-intr-inputs\n", __func__);
  121. return ret;
  122. }
  123. ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask);
  124. if (ret < 0) {
  125. pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__);
  126. return ret;
  127. }
  128. if (intr_mask >> nr_irq)
  129. pr_warn("%s: mismatch in kind-of-intr param\n", __func__);
  130. pr_info("%s: num_irq=%d, edge=0x%x\n",
  131. intc->full_name, nr_irq, intr_mask);
  132. write_fn = intc_write32;
  133. read_fn = intc_read32;
  134. /*
  135. * Disable all external interrupts until they are
  136. * explicity requested.
  137. */
  138. write_fn(0, intc_baseaddr + IER);
  139. /* Acknowledge any pending interrupts just in case. */
  140. write_fn(0xffffffff, intc_baseaddr + IAR);
  141. /* Turn on the Master Enable. */
  142. write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
  143. if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) {
  144. write_fn = intc_write32_be;
  145. read_fn = intc_read32_be;
  146. write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
  147. }
  148. /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
  149. * lazy and Michal can clean it up to something nicer when he tests
  150. * and commits this patch. ~~gcl */
  151. root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops,
  152. (void *)intr_mask);
  153. irq_set_default_host(root_domain);
  154. return 0;
  155. }
  156. IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);