simulate-insn.c 4.9 KB

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  1. /*
  2. * arch/arm64/kernel/probes/simulate-insn.c
  3. *
  4. * Copyright (C) 2013 Linaro Limited.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/kprobes.h>
  17. #include "simulate-insn.h"
  18. #define sign_extend(x, signbit) \
  19. ((x) | (0 - ((x) & (1 << (signbit)))))
  20. #define bbl_displacement(insn) \
  21. sign_extend(((insn) & 0x3ffffff) << 2, 27)
  22. #define bcond_displacement(insn) \
  23. sign_extend(((insn >> 5) & 0x7ffff) << 2, 20)
  24. #define cbz_displacement(insn) \
  25. sign_extend(((insn >> 5) & 0x7ffff) << 2, 20)
  26. #define tbz_displacement(insn) \
  27. sign_extend(((insn >> 5) & 0x3fff) << 2, 15)
  28. #define ldr_displacement(insn) \
  29. sign_extend(((insn >> 5) & 0x7ffff) << 2, 20)
  30. static inline void set_x_reg(struct pt_regs *regs, int reg, u64 val)
  31. {
  32. if (reg < 31)
  33. regs->regs[reg] = val;
  34. }
  35. static inline void set_w_reg(struct pt_regs *regs, int reg, u64 val)
  36. {
  37. if (reg < 31)
  38. regs->regs[reg] = lower_32_bits(val);
  39. }
  40. static inline u64 get_x_reg(struct pt_regs *regs, int reg)
  41. {
  42. if (reg < 31)
  43. return regs->regs[reg];
  44. else
  45. return 0;
  46. }
  47. static inline u32 get_w_reg(struct pt_regs *regs, int reg)
  48. {
  49. if (reg < 31)
  50. return lower_32_bits(regs->regs[reg]);
  51. else
  52. return 0;
  53. }
  54. static bool __kprobes check_cbz(u32 opcode, struct pt_regs *regs)
  55. {
  56. int xn = opcode & 0x1f;
  57. return (opcode & (1 << 31)) ?
  58. (get_x_reg(regs, xn) == 0) : (get_w_reg(regs, xn) == 0);
  59. }
  60. static bool __kprobes check_cbnz(u32 opcode, struct pt_regs *regs)
  61. {
  62. int xn = opcode & 0x1f;
  63. return (opcode & (1 << 31)) ?
  64. (get_x_reg(regs, xn) != 0) : (get_w_reg(regs, xn) != 0);
  65. }
  66. static bool __kprobes check_tbz(u32 opcode, struct pt_regs *regs)
  67. {
  68. int xn = opcode & 0x1f;
  69. int bit_pos = ((opcode & (1 << 31)) >> 26) | ((opcode >> 19) & 0x1f);
  70. return ((get_x_reg(regs, xn) >> bit_pos) & 0x1) == 0;
  71. }
  72. static bool __kprobes check_tbnz(u32 opcode, struct pt_regs *regs)
  73. {
  74. int xn = opcode & 0x1f;
  75. int bit_pos = ((opcode & (1 << 31)) >> 26) | ((opcode >> 19) & 0x1f);
  76. return ((get_x_reg(regs, xn) >> bit_pos) & 0x1) != 0;
  77. }
  78. /*
  79. * instruction simulation functions
  80. */
  81. void __kprobes
  82. simulate_adr_adrp(u32 opcode, long addr, struct pt_regs *regs)
  83. {
  84. long imm, xn, val;
  85. xn = opcode & 0x1f;
  86. imm = ((opcode >> 3) & 0x1ffffc) | ((opcode >> 29) & 0x3);
  87. imm = sign_extend(imm, 20);
  88. if (opcode & 0x80000000)
  89. val = (imm<<12) + (addr & 0xfffffffffffff000);
  90. else
  91. val = imm + addr;
  92. set_x_reg(regs, xn, val);
  93. instruction_pointer_set(regs, instruction_pointer(regs) + 4);
  94. }
  95. void __kprobes
  96. simulate_b_bl(u32 opcode, long addr, struct pt_regs *regs)
  97. {
  98. int disp = bbl_displacement(opcode);
  99. /* Link register is x30 */
  100. if (opcode & (1 << 31))
  101. set_x_reg(regs, 30, addr + 4);
  102. instruction_pointer_set(regs, addr + disp);
  103. }
  104. void __kprobes
  105. simulate_b_cond(u32 opcode, long addr, struct pt_regs *regs)
  106. {
  107. int disp = 4;
  108. if (aarch32_opcode_cond_checks[opcode & 0xf](regs->pstate & 0xffffffff))
  109. disp = bcond_displacement(opcode);
  110. instruction_pointer_set(regs, addr + disp);
  111. }
  112. void __kprobes
  113. simulate_br_blr_ret(u32 opcode, long addr, struct pt_regs *regs)
  114. {
  115. int xn = (opcode >> 5) & 0x1f;
  116. /* update pc first in case we're doing a "blr lr" */
  117. instruction_pointer_set(regs, get_x_reg(regs, xn));
  118. /* Link register is x30 */
  119. if (((opcode >> 21) & 0x3) == 1)
  120. set_x_reg(regs, 30, addr + 4);
  121. }
  122. void __kprobes
  123. simulate_cbz_cbnz(u32 opcode, long addr, struct pt_regs *regs)
  124. {
  125. int disp = 4;
  126. if (opcode & (1 << 24)) {
  127. if (check_cbnz(opcode, regs))
  128. disp = cbz_displacement(opcode);
  129. } else {
  130. if (check_cbz(opcode, regs))
  131. disp = cbz_displacement(opcode);
  132. }
  133. instruction_pointer_set(regs, addr + disp);
  134. }
  135. void __kprobes
  136. simulate_tbz_tbnz(u32 opcode, long addr, struct pt_regs *regs)
  137. {
  138. int disp = 4;
  139. if (opcode & (1 << 24)) {
  140. if (check_tbnz(opcode, regs))
  141. disp = tbz_displacement(opcode);
  142. } else {
  143. if (check_tbz(opcode, regs))
  144. disp = tbz_displacement(opcode);
  145. }
  146. instruction_pointer_set(regs, addr + disp);
  147. }
  148. void __kprobes
  149. simulate_ldr_literal(u32 opcode, long addr, struct pt_regs *regs)
  150. {
  151. u64 *load_addr;
  152. int xn = opcode & 0x1f;
  153. int disp;
  154. disp = ldr_displacement(opcode);
  155. load_addr = (u64 *) (addr + disp);
  156. if (opcode & (1 << 30)) /* x0-x30 */
  157. set_x_reg(regs, xn, *load_addr);
  158. else /* w0-w30 */
  159. set_w_reg(regs, xn, *load_addr);
  160. instruction_pointer_set(regs, instruction_pointer(regs) + 4);
  161. }
  162. void __kprobes
  163. simulate_ldrsw_literal(u32 opcode, long addr, struct pt_regs *regs)
  164. {
  165. s32 *load_addr;
  166. int xn = opcode & 0x1f;
  167. int disp;
  168. disp = ldr_displacement(opcode);
  169. load_addr = (s32 *) (addr + disp);
  170. set_x_reg(regs, xn, *load_addr);
  171. instruction_pointer_set(regs, instruction_pointer(regs) + 4);
  172. }