sdrc.c 4.0 KB

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  1. /*
  2. * SMS/SDRC (SDRAM controller) common code for OMAP2/3
  3. *
  4. * Copyright (C) 2005, 2008 Texas Instruments Inc.
  5. * Copyright (C) 2005, 2008 Nokia Corporation
  6. *
  7. * Tony Lindgren <tony@atomide.com>
  8. * Paul Walmsley
  9. * Richard Woodruff <r-woodruff2@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #undef DEBUG
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/device.h>
  19. #include <linux/list.h>
  20. #include <linux/errno.h>
  21. #include <linux/delay.h>
  22. #include <linux/clk.h>
  23. #include <linux/io.h>
  24. #include "common.h"
  25. #include "clock.h"
  26. #include "sdrc.h"
  27. static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
  28. void __iomem *omap2_sdrc_base;
  29. void __iomem *omap2_sms_base;
  30. struct omap2_sms_regs {
  31. u32 sms_sysconfig;
  32. };
  33. static struct omap2_sms_regs sms_context;
  34. /* SDRC_POWER register bits */
  35. #define SDRC_POWER_EXTCLKDIS_SHIFT 3
  36. #define SDRC_POWER_PWDENA_SHIFT 2
  37. #define SDRC_POWER_PAGEPOLICY_SHIFT 0
  38. /**
  39. * omap2_sms_save_context - Save SMS registers
  40. *
  41. * Save SMS registers that need to be restored after off mode.
  42. */
  43. void omap2_sms_save_context(void)
  44. {
  45. sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
  46. }
  47. /**
  48. * omap2_sms_restore_context - Restore SMS registers
  49. *
  50. * Restore SMS registers that need to be Restored after off mode.
  51. */
  52. void omap2_sms_restore_context(void)
  53. {
  54. sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
  55. }
  56. /**
  57. * omap2_sdrc_get_params - return SDRC register values for a given clock rate
  58. * @r: SDRC clock rate (in Hz)
  59. * @sdrc_cs0: chip select 0 ram timings **
  60. * @sdrc_cs1: chip select 1 ram timings **
  61. *
  62. * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
  63. * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
  64. * structs,for a given SDRC clock rate 'r'.
  65. * These parameters control various timing delays in the SDRAM controller
  66. * that are expressed in terms of the number of SDRC clock cycles to
  67. * wait; hence the clock rate dependency.
  68. *
  69. * Supports 2 different timing parameters for both chip selects.
  70. *
  71. * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
  72. * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
  73. * as sdrc_init_params_cs_0.
  74. *
  75. * Fills in the struct omap_sdrc_params * for each chip select.
  76. * Returns 0 upon success or -1 upon failure.
  77. */
  78. int omap2_sdrc_get_params(unsigned long r,
  79. struct omap_sdrc_params **sdrc_cs0,
  80. struct omap_sdrc_params **sdrc_cs1)
  81. {
  82. struct omap_sdrc_params *sp0, *sp1;
  83. if (!sdrc_init_params_cs0)
  84. return -1;
  85. sp0 = sdrc_init_params_cs0;
  86. sp1 = sdrc_init_params_cs1;
  87. while (sp0->rate && sp0->rate != r) {
  88. sp0++;
  89. if (sdrc_init_params_cs1)
  90. sp1++;
  91. }
  92. if (!sp0->rate)
  93. return -1;
  94. *sdrc_cs0 = sp0;
  95. *sdrc_cs1 = sp1;
  96. return 0;
  97. }
  98. void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms)
  99. {
  100. omap2_sdrc_base = sdrc;
  101. omap2_sms_base = sms;
  102. }
  103. /**
  104. * omap2_sdrc_init - initialize SMS, SDRC devices on boot
  105. * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
  106. * Support for 2 chip selects timings
  107. *
  108. * Turn on smart idle modes for SDRAM scheduler and controller.
  109. * Program a known-good configuration for the SDRC to deal with buggy
  110. * bootloaders.
  111. */
  112. void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
  113. struct omap_sdrc_params *sdrc_cs1)
  114. {
  115. u32 l;
  116. l = sms_read_reg(SMS_SYSCONFIG);
  117. l &= ~(0x3 << 3);
  118. l |= (0x2 << 3);
  119. sms_write_reg(l, SMS_SYSCONFIG);
  120. l = sdrc_read_reg(SDRC_SYSCONFIG);
  121. l &= ~(0x3 << 3);
  122. l |= (0x2 << 3);
  123. sdrc_write_reg(l, SDRC_SYSCONFIG);
  124. sdrc_init_params_cs0 = sdrc_cs0;
  125. sdrc_init_params_cs1 = sdrc_cs1;
  126. /* XXX Enable SRFRONIDLEREQ here also? */
  127. /*
  128. * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
  129. * can cause random memory corruption
  130. */
  131. l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
  132. (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
  133. sdrc_write_reg(l, SDRC_POWER);
  134. omap2_sms_save_context();
  135. }