clock.h 2.5 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/clock.h
  3. *
  4. * Copyright (C) 2005-2009 Texas Instruments, Inc.
  5. * Copyright (C) 2004-2011 Nokia Corporation
  6. *
  7. * Contacts:
  8. * Richard Woodruff <r-woodruff2@ti.com>
  9. * Paul Walmsley
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  16. #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  17. #include <linux/kernel.h>
  18. #include <linux/list.h>
  19. #include <linux/clkdev.h>
  20. #include <linux/clk-provider.h>
  21. #include <linux/clk/ti.h>
  22. /* struct clksel_rate.flags possibilities */
  23. #define RATE_IN_242X (1 << 0)
  24. #define RATE_IN_243X (1 << 1)
  25. #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
  26. #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
  27. #define RATE_IN_36XX (1 << 4)
  28. #define RATE_IN_4430 (1 << 5)
  29. #define RATE_IN_TI816X (1 << 6)
  30. #define RATE_IN_4460 (1 << 7)
  31. #define RATE_IN_AM33XX (1 << 8)
  32. #define RATE_IN_TI814X (1 << 9)
  33. #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
  34. #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
  35. #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
  36. #define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
  37. /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
  38. #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
  39. /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
  40. #define CORE_CLK_SRC_32K 0x0
  41. #define CORE_CLK_SRC_DPLL 0x1
  42. #define CORE_CLK_SRC_DPLL_X2 0x2
  43. /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
  44. #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
  45. #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
  46. #define OMAP2XXX_EN_DPLL_LOCKED 0x3
  47. /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
  48. #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
  49. #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
  50. #define OMAP3XXX_EN_DPLL_LOCKED 0x7
  51. /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
  52. #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
  53. #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
  54. #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
  55. #define OMAP4XXX_EN_DPLL_LOCKED 0x7
  56. void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
  57. const char *core_ck_name,
  58. const char *mpu_ck_name);
  59. extern u16 cpu_mask;
  60. extern const struct clkops clkops_omap2_dflt_wait;
  61. extern const struct clkops clkops_omap2_dflt;
  62. extern struct clk_functions omap2_clk_functions;
  63. int __init omap2_clk_setup_ll_ops(void);
  64. void __init ti_clk_init_features(void);
  65. #endif