sha1-ce-core.S 2.6 KB

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  1. /*
  2. * sha1-ce-core.S - SHA-1 secure hash using ARMv8 Crypto Extensions
  3. *
  4. * Copyright (C) 2015 Linaro Ltd.
  5. * Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/linkage.h>
  12. #include <asm/assembler.h>
  13. .text
  14. .fpu crypto-neon-fp-armv8
  15. k0 .req q0
  16. k1 .req q1
  17. k2 .req q2
  18. k3 .req q3
  19. ta0 .req q4
  20. ta1 .req q5
  21. tb0 .req q5
  22. tb1 .req q4
  23. dga .req q6
  24. dgb .req q7
  25. dgbs .req s28
  26. dg0 .req q12
  27. dg1a0 .req q13
  28. dg1a1 .req q14
  29. dg1b0 .req q14
  30. dg1b1 .req q13
  31. .macro add_only, op, ev, rc, s0, dg1
  32. .ifnb \s0
  33. vadd.u32 tb\ev, q\s0, \rc
  34. .endif
  35. sha1h.32 dg1b\ev, dg0
  36. .ifb \dg1
  37. sha1\op\().32 dg0, dg1a\ev, ta\ev
  38. .else
  39. sha1\op\().32 dg0, \dg1, ta\ev
  40. .endif
  41. .endm
  42. .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1
  43. sha1su0.32 q\s0, q\s1, q\s2
  44. add_only \op, \ev, \rc, \s1, \dg1
  45. sha1su1.32 q\s0, q\s3
  46. .endm
  47. .align 6
  48. .Lsha1_rcon:
  49. .word 0x5a827999, 0x5a827999, 0x5a827999, 0x5a827999
  50. .word 0x6ed9eba1, 0x6ed9eba1, 0x6ed9eba1, 0x6ed9eba1
  51. .word 0x8f1bbcdc, 0x8f1bbcdc, 0x8f1bbcdc, 0x8f1bbcdc
  52. .word 0xca62c1d6, 0xca62c1d6, 0xca62c1d6, 0xca62c1d6
  53. /*
  54. * void sha1_ce_transform(struct sha1_state *sst, u8 const *src,
  55. * int blocks);
  56. */
  57. ENTRY(sha1_ce_transform)
  58. /* load round constants */
  59. adr ip, .Lsha1_rcon
  60. vld1.32 {k0-k1}, [ip, :128]!
  61. vld1.32 {k2-k3}, [ip, :128]
  62. /* load state */
  63. vld1.32 {dga}, [r0]
  64. vldr dgbs, [r0, #16]
  65. /* load input */
  66. 0: vld1.32 {q8-q9}, [r1]!
  67. vld1.32 {q10-q11}, [r1]!
  68. subs r2, r2, #1
  69. #ifndef CONFIG_CPU_BIG_ENDIAN
  70. vrev32.8 q8, q8
  71. vrev32.8 q9, q9
  72. vrev32.8 q10, q10
  73. vrev32.8 q11, q11
  74. #endif
  75. vadd.u32 ta0, q8, k0
  76. vmov dg0, dga
  77. add_update c, 0, k0, 8, 9, 10, 11, dgb
  78. add_update c, 1, k0, 9, 10, 11, 8
  79. add_update c, 0, k0, 10, 11, 8, 9
  80. add_update c, 1, k0, 11, 8, 9, 10
  81. add_update c, 0, k1, 8, 9, 10, 11
  82. add_update p, 1, k1, 9, 10, 11, 8
  83. add_update p, 0, k1, 10, 11, 8, 9
  84. add_update p, 1, k1, 11, 8, 9, 10
  85. add_update p, 0, k1, 8, 9, 10, 11
  86. add_update p, 1, k2, 9, 10, 11, 8
  87. add_update m, 0, k2, 10, 11, 8, 9
  88. add_update m, 1, k2, 11, 8, 9, 10
  89. add_update m, 0, k2, 8, 9, 10, 11
  90. add_update m, 1, k2, 9, 10, 11, 8
  91. add_update m, 0, k3, 10, 11, 8, 9
  92. add_update p, 1, k3, 11, 8, 9, 10
  93. add_only p, 0, k3, 9
  94. add_only p, 1, k3, 10
  95. add_only p, 0, k3, 11
  96. add_only p, 1
  97. /* update state */
  98. vadd.u32 dga, dga, dg0
  99. vadd.u32 dgb, dgb, dg1a0
  100. bne 0b
  101. /* store new state */
  102. vst1.32 {dga}, [r0]
  103. vstr dgbs, [r0, #16]
  104. bx lr
  105. ENDPROC(sha1_ce_transform)