vdptest/RESULTS.txt

1. Interpretation of results

  The test program syncs with the 9918 (or similar) vertical interrupt. It
  does not consider any of the other interrupts in the V9938 or later.

  The results will probably be meaningless in any machine with separate clocks
  for the CPU and the VDP. Even in machines with a shared clock, there seem
  to be six possible phases between CPU and VDP, as demonstrated by the three
  different results obtained in the VG-8020/40 and the NMS-8250.

  All measurements are taken from the CPU (no hardware probes), therefore
  they all use the CPU clock as a basis.

  The program reports a screen with this layout:

    Screen mode: S
    Error code (0=no error): E
    Cycles/frame: F
    ACK works A cyc. after INT
    Bit 7 set B cyc. after INT
    ACK takes C to D cycles
    1st fast wr. failure cycles:
    12T: G12  14T: G14
    17T: G17  18T: G18
    19T: G19  20T: G20
    21T: G21  22T: G22
    23T: G23  24T: G24

  Where:
    F: total CPU cycles per frame.
    E: exit error code; a value of 0 means no error.
    Note: The value of F has been found to be stable in all tested computers,
    even in those with separate clocks. Cause is unknown.

    A: Number of ticks at which an interrupt may be acknowledged by reading
       the Status Register, relative to the interrupt, causing the interrupt
       line to go inactive. Negative means before the interrupt. It was
       negative in every tested VDP, but note that a positive value of up to
       19 cycles would allow any interrupt service routine to acknowledge it,
       due to the delay for the interrupt to trigger and for the fastest IN
       instruction to execute.
    B: Number of ticks, relative to the interrupt, at which the Status
       Register bit 7 starts being set. Negative means before the interrupt.
    C, D: Minimum and maximum number of cycles for interrupt acknowledgement,
       that is, from the I/O read of the Status Register to an INT being
       no longer triggered. D=-1 means from C up. Possible values of C,D are:
          0,2;  3,5;  6,10;  11,12;  13,13;  14,14;  15,15;  16,-1.
       I don't think software can distinguish finer results. Suggestions for
       how to perform a more fine-grained test are welcome.
    G12: Number of ticks, relative to the interrupt, at which writing to VRAM
       with a 12 cycle separation between OUTs causes a write failure. A value
       equal to F (total CPU cycles per frame) means that every fast write
       succeeds.
    G14: Like G12 but with a 14 cycle separation.
    G17: Like G12 but with a 17 cycle separation.
    G18: Like G12 but with a 18 cycle separation.
    G19: Like G12 but with a 19 cycle separation.
    G20: Like G12 but with a 20 cycle separation.
    G21: Like G12 but with a 21 cycle separation.
    G22: Like G12 but with a 22 cycle separation.
    G23: Like G12 but with a 23 cycle separation.
    G24: Like G12 but with a 24 cycle separation.

  Example using one set of values obtained in the Philips VG-8020/40:

  E: 0
  - Error code: 0, meaning no error.
  F: 71364
  - 71364 cycles (T-states) per frame (typical in PAL machines).
  A: -5
  B: -3
  - If the status register is read 5 cycles before the interrupt, the
    interrupt is not triggered. This counts the exact cycle at which the
    I/O operation takes place, not the start of the instruction.
  - Bit 7 of the status register is set 3 cycles before the interrupt.
  - Note that when A < B, that leaves a gap in which, if the status port
    is read at a cycle >= A and < B, neither bit 7 of the Status Register
    will be set, nor will the interrupt trigger.
  C: 3
  D: 5
  - Once the int line goes low (active), it takes between 3 and 5 cycles
    inclusive (but we don't know how many exactly) for the interrupt to be
    blocked after being acknowledged. Note: Since the /INT line is sampled
    at the last cycle of each instruction, this probably means that at the
    hardware level, it takes between 2 and 4 cycles for this line to go high
    again.
  G12: 27130
  - Writing to the VRAM with a 12 cycle separation (faster than the VDP
    can handle) is guaranteed to succeed if performed during cycles 0 to
    27129 inclusive after the interrupt; the first time it will fail is
    27130 cycles after the interrupt. A value equal to F (71364 in this
    example) means that every fast write succeeds, no matter how many
    cycles after the interrupt.
  G14: 27130
  - When writing to VRAM with a 14 cycle separation, the first failure
    appears at cycle 27130 (just like with a 12 cycle separation).
  G17: 27130
  - When writing to VRAM with a 17 cycle separation, the first failure
    appears at cycle 27130.
  [and so on]


2. Results for MSX1 machines with synced clocks

  Philips VG-8020/40 (VDP: TMS9129NL):
    E: 0
    F: 71364
    C, D: 3, 5 always
    A, B, G12, G14, G17, G18, G19, G20, G21, G22, G23, G24:
      For SCREEN 0: 71364
      For SCREEN 1-2, and for SCREEN 3 except when A, B = -5, -4:
        Three possible tuples:
        -5 -4 27130 27130 27130 27130 27143 27143 27143 27143 27143 27143
        -5 -3 27130 27130 27130 27130 27144 27144 27144 27144 27144 27144
        -4 -3 27131 27131 27131 27144 27144 27144 27144 27144 27144 27144
      For SCREEN 3, G18 is different when A, B = -5, -4:
        -5 -4 27130 27130 27130 27143 27143 27143 27143 27143 27143 27143
    The values of A, B, G are consistent between runs or soft resets
    (DEFUSR=0); they only vary between hard resets (RESET button) or power
    cycles.

    Two possible explanations for the different A,B,G values are:
    - Variation in the phase between VDP and CPU.
    - Randomness in the initialization of the internal 2-bit "CPU" counter
      in the VDP (see US Patent 4,243,984).

  Casio PV-7 (VDP: TMS9118NL):
    E: 0
    F: 59736
    A, B, C, D: -4, -3, 3, 5
    G12, G14, G17, G18, G19, G20, G21, G22, G23, G24:
      For SCREEN 0: 59736
      For SCREEN 1-3:
        15503 15503 15503 15517 15517 15517 15517 15517 15517 15517

  Yamaha/Sakhr AX-150 (VDP: YM2220):
    A, B, C, D, E, F: -5 -3 3 5 0 71364
    G12, G14, G17, G18, G19, G20, G21, G22, G23, G24:
    For SCREEN 0: 71364
    For SCREEN 1-3:
      27131 27131 27131 27144 27144 27144 27144 27144 27144 27144


3. Results for MSX2/2+/TR machines with synced clocks

  Philips NMS-8250 (VDP: V9938):
    E: 0
    F: 71364 (59736 after entering VDP(10)=0).
    A, B, C, D values observed:
      -6, -3, 3, 5
      -6, -2, 3, 5
      -6, -3, 6, 10
      -6, -2, 6, 10
    G12, G14, G17, G18, G19, G20, G21, G22, G23, G24:
      In SCREEN 0:
        4, 4, 4, 4, 4, 4, 19, 71364/59736
        3, 3, 3, 3, 3, 3, 18, 71364/59736
      In SCREEN 1-3:
        8, 8, 71364/59736 x 6
        9, 9, 71364/59736 x 6

    Generally consistent between runs but not always. Not consistent
    between hard boots (reset or power cycle).


  Panasonic FS-A1ST (VDP:V9958):
    The results don't make sense in this machine, varying wildly between runs,
    probably due to the automatically inserted wait states. A tailor-made test
    would be needed.


4. Results for machines with separate clocks

  Sony HB-10P (VDP: T6950, separate clocks):
    E: 0
    F: 71745
    A, B: Variable. Minimum A observed was -15; maximum -1. Minimum B observed
          was -16; maximum -1. abs(A-B) was always 0 or 1, with both A<B and
          A>B observed. They are tested separately, therefore it's possible
          that they always occur at the same cycle.
          The values became smaller with longer power-on times, suggesting
          that the cause is clock drift due to temperature.
    C, D: 3, 5
    G: not tested yet


5. Results for openMSX (current master as of Feb 10 2020)

  All machines:
     E: 0
     F: 71364/59736 (PAL/NTSC)
     A, B: 0, 0
     C, D: 0, 2
     Gxx: 71364/59736 (PAL/NTSC) in screen 0
   Screens 1-3:
     G12, G14, G17, G18, G19, G20, G21, G22, G23:  27588/15960 (PAL/NTSC)
     G24: 27608/15980 (PAL/NTSC)