Cronologia Commit

Autore SHA1 Messaggio Data
  Pedro Gimeno 4e745657ac Add write loops for gaps of 19 to 24 cycles between writes 4 anni fa
  Pedro Gimeno c8083b50a0 Add 3 more write loops with different separations, with results 4 anni fa
  Pedro Gimeno 242c6dd8be Prepare the code for write loops of other lengths (1/2) 4 anni fa
  Pedro Gimeno 58b596792c Drop the Bit Array and change strategy 4 anni fa
  Pedro Gimeno 0642fa84c8 Find the first cycle at which a fast write fails and report it 4 anni fa
  Pedro Gimeno 799d19f4ba Use memory to store the division result, and IY for error reporting 4 anni fa
  Pedro Gimeno d801ff33a6 Progress on formalizing the VRAM timing measurement 4 anni fa