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microchip16
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configWords.py

configWords.py 12 KB
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  1. """
    2. 

  2. #    TOP2049 Open Source programming suite
    3. 

  3. #
    4. 

  4. #    configWordsSet - configWord specification for 16bit PIC MCUs
    5. 

  5. #
    6. 

  6. #    Copyright (c) 2014 Pavel Stemberk <stemberk@gmail.com>
    7. 

  7. #
    8. 

  8. #    This program is free software; you can redistribute it and/or modify
    9. 

  9. #    it under the terms of the GNU General Public License as published by
    10. 

  10. #    the Free Software Foundation; either version 2 of the License, or
    11. 

  11. #    (at your option) any later version.
    12. 

  12. #
    13. 

  13. #    This program is distributed in the hope that it will be useful,
    14. 

  14. #    but WITHOUT ANY WARRANTY; without even the implied warranty of
    15. 

  15. #    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16. 

  16. #    GNU General Public License for more details.
    17. 

  17. #
    18. 

  18. #    You should have received a copy of the GNU General Public License along
    19. 

  19. #    with this program; if not, write to the Free Software Foundation, Inc.,
    20. 

  20. #    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
    21. 

  21. """
    22. 

  22. 

  23. from  libtoprammer.chip import BitDescription
    24. 

  24. 

  25. ka200_fuseDesc = (
    26. 

  26. 	BitDescription(0o00, "NA"),
    27. 

  27. 	BitDescription(0o01, "NA"),
    28. 

  28. 	BitDescription(0o02, "NA"),
    29. 

  29. 	BitDescription(0o03, "NA"),
    30. 

  30. 	BitDescription(0o04, "NA"),
    31. 

  31. 	BitDescription(0o05, "NA"),
    32. 

  32. 	BitDescription(0o06, "NA"),
    33. 

  33. 	BitDescription(0o07, "NA"),
    34. 

  34. 	BitDescription(0o10, "NA"),
    35. 

  35. 	BitDescription(0o11, "NA"),
    36. 

  36. 	BitDescription(0o12, "NA"),
    37. 

  37. 	BitDescription(0o13, "NA"),
    38. 

  38. 	BitDescription(0o14, "NA"),
    39. 

  39. 	BitDescription(0o15, "NA"),
    40. 

  40. 	BitDescription(0o16, "NA"),
    41. 

  41. 	BitDescription(0o17, "NA"),
    42. 

  42. 	
    43. 

  43. 	BitDescription(0o20, "NA"),
    44. 

  44. 	BitDescription(0o21, "NA"),
    45. 

  45. 	BitDescription(0o22, "NA"),
    46. 

  46. 	BitDescription(0o23, "NA"),
    47. 

  47. 	BitDescription(0o24, "NA"),
    48. 

  48. 	BitDescription(0o25, "NA"),
    49. 

  49. 	BitDescription(0o26, "NA"),
    50. 

  50. 	BitDescription(0o27, "NA"),
    51. 

  51. 	BitDescription(0o30, "NA"),
    52. 

  52. 	BitDescription(0o31, "NA"),
    53. 

  53. 	BitDescription(0o32, "NA"),
    54. 

  54. 	BitDescription(0o33, "NA"),
    55. 

  55. 	BitDescription(0o34, "NA"),
    56. 

  56. 	BitDescription(0o35, "NA"),
    57. 

  57. 	BitDescription(0o36, "NA"),
    58. 

  58. 	BitDescription(0o37, "NA"),
    59. 

  59. 	
    60. 

  60. 	BitDescription(0o40, "FGS:GWRP: General Segment Code Flash Write Protection bit, 1 = General segment may be written"),
    61. 

  61. 	BitDescription(0o41, "FGS:GSS0 General Segment Code Flash Code Protection bit, 1 = no protection"),
    62. 

  62. 	BitDescription(0o42, "NA"),
    63. 

  63. 	BitDescription(0o43, "NA"),
    64. 

  64. 	BitDescription(0o44, "NA"),
    65. 

  65. 	BitDescription(0o45, "NA"),
    66. 

  66. 	BitDescription(0o46, "NA"),
    67. 

  67. 	BitDescription(0o47, "NA"),
    68. 

  68. 	BitDescription(0o50, "NA"),
    69. 

  69. 	BitDescription(0o51, "NA"),
    70. 

  70. 	BitDescription(0o52, "NA"),
    71. 

  71. 	BitDescription(0o53, "NA"),
    72. 

  72. 	BitDescription(0o54, "NA"),
    73. 

  73. 	BitDescription(0o55, "NA"),
    74. 

  74. 	BitDescription(0o56, "NA"),
    75. 

  75. 	BitDescription(0o57, "NA"),
    76. 

  76. 	
    77. 

  77. 	BitDescription(0o60, "FOSCSEL: FNOSC[0] 101 = 500 kHz Low-Power FRC oscillato"),
    78. 

  78. 	BitDescription(0o61, "FOSCSEL: FNOSC[1] 110 = 500 kHz Low-Power FRC oscillator with divide-by-N (LPFRCDIV)"),
    79. 

  79. 	BitDescription(0o62, "FOSCSEL: FNOSC[2] 111 = 8 MHz FRC oscillator with divide-by-N (FRCDIV)"),
    80. 

  80. 	BitDescription(0o63, "NA"),
    81. 

  81. 	BitDescription(0o64, "NA"),
    82. 

  82. 	BitDescription(0o65, "NA"),
    83. 

  83. 	BitDescription(0o66, "NA"),
    84. 

  84. 	BitDescription(0o67, "FOSCSEL: IESO: Internal External Switchover bit, 1 = enabled"),
    85. 

  85. 	BitDescription(0o70, "NA"),
    86. 

  86. 	BitDescription(0o71, "NA"),
    87. 

  87. 	BitDescription(0o72, "NA"),
    88. 

  88. 	BitDescription(0o73, "NA"),
    89. 

  89. 	BitDescription(0o74, "NA"),
    90. 

  90. 	BitDescription(0o75, "NA"),
    91. 

  91. 	BitDescription(0o76, "NA"),
    92. 

  92. 	BitDescription(0o77, "NA"),
    93. 

  93. 	
    94. 

  94. 	BitDescription(0o100, "FOSC: POSCMD[0] 11 = Primary oscillator disabled = HS Oscillator mode selected"),
    95. 

  95. 	BitDescription(0o101, "FOSC: POSCMD[1]"),
    96. 

  96. 	BitDescription(0o102, "FOSC: OSCIOFNC 1 = CLKO output signal active on the OSCO pin"),
    97. 

  97. 	BitDescription(0o103, "FOSC: POSCFREQ[0] 00 = Reserved; do not use"),
    98. 

  98. 	BitDescription(0o104, "FOSC: POSCFREQ[1] 11 = Primary oscillator/external clock input frequency greater than 8 MHz"),
    99. 

  99. 	BitDescription(0o105, "FOSC: SOSCSEL 1 = Secondary oscillator configured for high-power operation"),
    100. 

  100. 	BitDescription(0o106, "FOSC: FCKSM[0] 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled"),
    101. 

  101. 	BitDescription(0o107, "FOSC: FCKSM[1] 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled"),
    102. 

  102. 	BitDescription(0o110, "NA"),
    103. 

  103. 	BitDescription(0o111, "NA"),
    104. 

  104. 	BitDescription(0o112, "NA"),
    105. 

  105. 	BitDescription(0o113, "NA"),
    106. 

  106. 	BitDescription(0o114, "NA"),
    107. 

  107. 	BitDescription(0o115, "NA"),
    108. 

  108. 	BitDescription(0o116, "NA"),
    109. 

  109. 	BitDescription(0o117, "NA"), 	
    110. 

  110.     
    111. 

  111. 	BitDescription(0o120, "FWDT: WDTPS[0] 0000 = 1:1"),
    112. 

  112. 	BitDescription(0o121, "FWDT: WDTPS[1] 0001 = 1:2"),
    113. 

  113. 	BitDescription(0o122, "FWDT: WDTPS[2] 0010 = 1:4"),
    114. 

  114. 	BitDescription(0o123, "FWDT: WDTPS[3] 1111 = 1:32768"),
    115. 

  115. 	BitDescription(0o124, "FWDT: FWPSA 1 = WDT prescaler ratio of 1:128"),
    116. 

  116. 	BitDescription(0o125, "NA"),
    117. 

  117. 	BitDescription(0o126, "FWDT: WINDIS: 1 = Standard WDT selected; windowed WDT disabled"),
    118. 

  118. 	BitDescription(0o127, "FWDT: FWDTEN: 1 = WDT enabled"),
    119. 

  119. 	BitDescription(0o130, "NA"),
    120. 

  120. 	BitDescription(0o131, "NA"),
    121. 

  121. 	BitDescription(0o132, "NA"),
    122. 

  122. 	BitDescription(0o133, "NA"),
    123. 

  123. 	BitDescription(0o134, "NA"),
    124. 

  124. 	BitDescription(0o135, "NA"),
    125. 

  125. 	BitDescription(0o136, "NA"),
    126. 

  126. 	BitDescription(0o137, "NA"),
    127. 

  127. 	
    128. 

  128. 	BitDescription(0o140, "FPOR: BOREN[0] 00 = Brown-out Reset disabled in hardware; SBOREN bit disabled"),
    129. 

  129. 	BitDescription(0o141, "FPOR: BOREN[1] 11 = Brown-out Reset enabled in hardware; SBOREN bit disabled"),
    130. 

  130. 	BitDescription(0o142, "NA"),
    131. 

  131. 	BitDescription(0o143, "FPOR: PWRTEN: 1 = Power-up Timer Enable bit enabled"),
    132. 

  132. 	BitDescription(0o144, "NA"),
    133. 

  133. 	BitDescription(0o145, "FPOR: BORV[0] 00 = Low-power Brown-out Reset occurs around 2.0V"),
    134. 

  134. 	BitDescription(0o146, "FPOR: BORV[1] 11 = Brown-out Reset set to lowest voltage"),
    135. 

  135. 	BitDescription(0o147, "FPOR: MCLRE: 1 = MCLR pin enabled; RA5 input pin disabled"),
    136. 

  136. 	BitDescription(0o150, "NA"),
    137. 

  137. 	BitDescription(0o151, "NA"),
    138. 

  138. 	BitDescription(0o152, "NA"),
    139. 

  139. 	BitDescription(0o153, "NA"),
    140. 

  140. 	BitDescription(0o154, "NA"),
    141. 

  141. 	BitDescription(0o155, "NA"),
    142. 

  142. 	BitDescription(0o156, "NA"),
    143. 

  143. 	BitDescription(0o157, "NA"), 	
    144. 

  144. 	
    145. 

  145. 	BitDescription(0o160, "FICD[0] 10 = PGC2/PGD2 are used for programming the device"),
    146. 

  146. 	BitDescription(0o161, "FICD[1] 00, 11 = Reserved; do not use"),
    147. 

  147. 	BitDescription(0o162, "NA"),
    148. 

  148. 	BitDescription(0o163, "NA"),
    149. 

  149. 	BitDescription(0o164, "NA"),
    150. 

  150. 	BitDescription(0o165, "NA"),
    151. 

  151. 	BitDescription(0o166, "NA"),
    152. 

  152. 	BitDescription(0o167, "NA"),
    153. 

  153. 	BitDescription(0o170, "NA"),
    154. 

  154. 	BitDescription(0o171, "NA"),
    155. 

  155. 	BitDescription(0o172, "NA"),
    156. 

  156. 	BitDescription(0o173, "NA"),
    157. 

  157. 	BitDescription(0o174, "NA"),
    158. 

  158. 	BitDescription(0o175, "NA"),
    159. 

  159. 	BitDescription(0o176, "NA"),
    160. 

  160. 	BitDescription(0o137, "NA"),
    161. 

  161. )
    162. 

  162. klx0x_fuseDesc = (
    163. 

  163. 	BitDescription(0o00, "FBS:BWRP 1 = Boot Segment may be written"),
    164. 

  164. 	BitDescription(0o01, "FBS:BSS[0] 001 = High-security Boot Segment starts at 0200h, ends at 15FEh"),
    165. 

  165. 	BitDescription(0o02, "FBS:BSS[1] 101 = Standard security Boot Segment starts at 0200h, ends at 15FEh"),
    166. 

  166. 	BitDescription(0o03, "FBS:BSS[2] 111 = No Boot Segment; all program memory space is General Segment"),
    167. 

  167. 	BitDescription(0o04, "NA"),
    168. 

  168. 	BitDescription(0o05, "NA"),
    169. 

  169. 	BitDescription(0o06, "NA"),
    170. 

  170. 	BitDescription(0o07, "NA"),
    171. 

  171. 	BitDescription(0o10, "NA"),
    172. 

  172. 	BitDescription(0o11, "NA"),
    173. 

  173. 	BitDescription(0o12, "NA"),
    174. 

  174. 	BitDescription(0o13, "NA"),
    175. 

  175. 	BitDescription(0o14, "NA"),
    176. 

  176. 	BitDescription(0o15, "NA"),
    177. 

  177. 	BitDescription(0o16, "NA"),
    178. 

  178. 	BitDescription(0o17, "NA"),
    179. 

  179. 	
    180. 

  180. 	BitDescription(0o20, "NA"),
    181. 

  181. 	BitDescription(0o21, "NA"),
    182. 

  182. 	BitDescription(0o22, "NA"),
    183. 

  183. 	BitDescription(0o23, "NA"),
    184. 

  184. 	BitDescription(0o24, "NA"),
    185. 

  185. 	BitDescription(0o25, "NA"),
    186. 

  186. 	BitDescription(0o26, "NA"),
    187. 

  187. 	BitDescription(0o27, "NA"),
    188. 

  188. 	BitDescription(0o30, "NA"),
    189. 

  189. 	BitDescription(0o31, "NA"),
    190. 

  190. 	BitDescription(0o32, "NA"),
    191. 

  191. 	BitDescription(0o33, "NA"),
    192. 

  192. 	BitDescription(0o34, "NA"),
    193. 

  193. 	BitDescription(0o35, "NA"),
    194. 

  194. 	BitDescription(0o36, "NA"),
    195. 

  195. 	BitDescription(0o37, "NA"),
    196. 

  196. 	
    197. 

  197. 	BitDescription(0o40, "FGS:GWRP: General Segment Code Flash Write Protection bit, 1 = General segment may be written"),
    198. 

  198. 	BitDescription(0o41, "FGS:GSS0 General Segment Code Flash Code Protection bit, 1 = no protection"),
    199. 

  199. 	BitDescription(0o42, "NA"),
    200. 

  200. 	BitDescription(0o43, "NA"),
    201. 

  201. 	BitDescription(0o44, "NA"),
    202. 

  202. 	BitDescription(0o45, "NA"),
    203. 

  203. 	BitDescription(0o46, "NA"),
    204. 

  204. 	BitDescription(0o47, "NA"),
    205. 

  205. 	BitDescription(0o50, "NA"),
    206. 

  206. 	BitDescription(0o51, "NA"),
    207. 

  207. 	BitDescription(0o52, "NA"),
    208. 

  208. 	BitDescription(0o53, "NA"),
    209. 

  209. 	BitDescription(0o54, "NA"),
    210. 

  210. 	BitDescription(0o55, "NA"),
    211. 

  211. 	BitDescription(0o56, "NA"),
    212. 

  212. 	BitDescription(0o57, "NA"),
    213. 

  213. 	
    214. 

  214. 	BitDescription(0o60, "FOSCSEL: FNOSC[0] 101 = 000 = 8 MHz FRC Oscillator (FRC)"),
    215. 

  215. 	BitDescription(0o61, "FOSCSEL: FNOSC[1] 110 = 500 kHz Low-Power FRC oscillator with divide-by-N (LPFRCDIV)"),
    216. 

  216. 	BitDescription(0o62, "FOSCSEL: FNOSC[2] 111 = 8 MHz FRC oscillator with divide-by-N (FRCDIV)"),
    217. 

  217. 	BitDescription(0o63, "NA"),
    218. 

  218. 	BitDescription(0o64, "NA"),
    219. 

  219. 	BitDescription(0o65, "FOSCSEL: SOSCSRC 1 = SOSC analog crystal function is available on the SOSCI/SOSCO pins"),
    220. 

  220. 	BitDescription(0o66, "FOSCSEL: LPRCSEL 1 = High-Power/High-Accuracy mode"),
    221. 

  221. 	BitDescription(0o67, "FOSCSEL: IESO: Internal External Switchover bit, 1 = enabled"),
    222. 

  222. 	BitDescription(0o70, "NA"),
    223. 

  223. 	BitDescription(0o71, "NA"),
    224. 

  224. 	BitDescription(0o72, "NA"),
    225. 

  225. 	BitDescription(0o73, "NA"),
    226. 

  226. 	BitDescription(0o74, "NA"),
    227. 

  227. 	BitDescription(0o75, "NA"),
    228. 

  228. 	BitDescription(0o76, "NA"),
    229. 

  229. 	BitDescription(0o77, "NA"),
    230. 

  230. 	
    231. 

  231. 	BitDescription(0o100, "FOSC: POSCMD[0] 11 = Primary oscillator disabled = HS Oscillator mode selected"),
    232. 

  232. 	BitDescription(0o101, "FOSC: POSCMD[1]"),
    233. 

  233. 	BitDescription(0o102, "FOSC: OSCIOFNC 1 = CLKO output signal active on the OSCO pin"),
    234. 

  234. 	BitDescription(0o103, "FOSC: POSCFREQ[0] 00 = Reserved; do not use"),
    235. 

  235. 	BitDescription(0o104, "FOSC: POSCFREQ[1] 11 = Primary oscillator/external clock input frequency greater than 8 MHz"),
    236. 

  236. 	BitDescription(0o105, "FOSC: SOSCSEL 1 = Secondary oscillator configured for high-power operation"),
    237. 

  237. 	BitDescription(0o106, "FOSC: FCKSM[0] 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled"),
    238. 

  238. 	BitDescription(0o107, "FOSC: FCKSM[1] 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled"),
    239. 

  239. 	BitDescription(0o110, "NA"),
    240. 

  240. 	BitDescription(0o111, "NA"),
    241. 

  241. 	BitDescription(0o112, "NA"),
    242. 

  242. 	BitDescription(0o113, "NA"),
    243. 

  243. 	BitDescription(0o114, "NA"),
    244. 

  244. 	BitDescription(0o115, "NA"),
    245. 

  245. 	BitDescription(0o116, "NA"),
    246. 

  246. 	BitDescription(0o117, "NA"), 	
    247. 

  247.     
    248. 

  248. 	BitDescription(0o120, "FWDT: WDTPS[0] 0000 = 1:1"),
    249. 

  249. 	BitDescription(0o121, "FWDT: WDTPS[1] 0001 = 1:2"),
    250. 

  250. 	BitDescription(0o122, "FWDT: WDTPS[2] 0010 = 1:4"),
    251. 

  251. 	BitDescription(0o123, "FWDT: WDTPS[3] 1111 = 1:32768"),
    252. 

  252. 	BitDescription(0o124, "FWDT: FWPSA 1 = WDT prescaler ratio of 1:128"),
    253. 

  253. 	BitDescription(0o125, "FWDT: FWDTEN[0]: 00 = WDT is disabled in hardware; SWDTEN bit is disabled"),
    254. 

  254. 	BitDescription(0o126, "FWDT: WINDIS: 1 = Standard WDT selected; windowed WDT disabled"),
    255. 

  255. 	BitDescription(0o127, "FWDT: FWDTEN[1]: 11 = WDT is enabled in hardware"),
    256. 

  256. 	BitDescription(0o130, "NA"),
    257. 

  257. 	BitDescription(0o131, "NA"),
    258. 

  258. 	BitDescription(0o132, "NA"),
    259. 

  259. 	BitDescription(0o133, "NA"),
    260. 

  260. 	BitDescription(0o134, "NA"),
    261. 

  261. 	BitDescription(0o135, "NA"),
    262. 

  262. 	BitDescription(0o136, "NA"),
    263. 

  263. 	BitDescription(0o137, "NA"),
    264. 

  264. 	
    265. 

  265. 	BitDescription(0o140, "FPOR: BOREN[0] 00 = Brown-out Reset disabled in hardware; SBOREN bit disabled"),
    266. 

  266. 	BitDescription(0o141, "FPOR: BOREN[1] 11 = Brown-out Reset enabled in hardware; SBOREN bit disabled"),
    267. 

  267. 	BitDescription(0o142, "NA"),
    268. 

  268. 	BitDescription(0o143, "FPOR: PWRTEN: 1 = Power-up Timer Enable bit enabled"),
    269. 

  269. 	BitDescription(0o144, "FPOR: I2C1SEL: Alternate MSSP1 I2CTM Pin Mapping bit 1 = default loc."),
    270. 

  270. 	BitDescription(0o145, "FPOR: BORV[0] 00 = Low-power Brown-out Reset occurs around 2.0V"),
    271. 

  271. 	BitDescription(0o146, "FPOR: BORV[1] 11 = Brown-out Reset set to lowest voltage"),
    272. 

  272. 	BitDescription(0o147, "FPOR: MCLRE: 1 = MCLR pin enabled; RA5 input pin disabled"),
    273. 

  273. 	BitDescription(0o150, "NA"),
    274. 

  274. 	BitDescription(0o151, "NA"),
    275. 

  275. 	BitDescription(0o152, "NA"),
    276. 

  276. 	BitDescription(0o153, "NA"),
    277. 

  277. 	BitDescription(0o154, "NA"),
    278. 

  278. 	BitDescription(0o155, "NA"),
    279. 

  279. 	BitDescription(0o156, "NA"),
    280. 

  280. 	BitDescription(0o157, "NA"), 	
    281. 

  281. 	
    282. 

  282. 	BitDescription(0o160, "FICD: ICS[0] 11 = PGEC1/PGED1 are used for programming and debugging the device"),
    283. 

  283. 	BitDescription(0o161, "FICD: ICS[1] 00, 11 = Reserved; do not use"),
    284. 

  284. 	BitDescription(0o162, "NA"),
    285. 

  285. 	BitDescription(0o163, "NA"),
    286. 

  286. 	BitDescription(0o164, "NA"),
    287. 

  287. 	BitDescription(0o165, "NA"),
    288. 

  288. 	BitDescription(0o166, "NA"),
    289. 

  289. 	BitDescription(0o167, "FICD: DEBUG 1 = Background debugger is disabled"),
    290. 

  290. 	BitDescription(0o170, "NA"),
    291. 

  291. 	BitDescription(0o171, "NA"),
    292. 

  292. 	BitDescription(0o172, "NA"),
    293. 

  293. 	BitDescription(0o173, "NA"),
    294. 

  294. 	BitDescription(0o174, "NA"),
    295. 

  295. 	BitDescription(0o175, "NA"),
    296. 

  296. 	BitDescription(0o176, "NA"),
    297. 

  297. 	BitDescription(0o137, "NA"),
    298. 

  298. )
    299. 

  299.