tinyfpga_bx.pcf 3.3 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495
  1. ###############################################################################
  2. #
  3. # TinyFPGA BX constraint file (.pcf)
  4. #
  5. ###############################################################################
  6. #
  7. # Copyright (c) 2018, Luke Valenty
  8. # All rights reserved.
  9. #
  10. # Redistribution and use in source and binary forms, with or without
  11. # modification, are permitted provided that the following conditions are met:
  12. #
  13. # 1. Redistributions of source code must retain the above copyright notice, this
  14. # list of conditions and the following disclaimer.
  15. # 2. Redistributions in binary form must reproduce the above copyright notice,
  16. # this list of conditions and the following disclaimer in the documentation
  17. # and/or other materials provided with the distribution.
  18. #
  19. # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  20. # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21. # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22. # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  23. # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24. # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25. # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26. # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27. # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28. # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29. #
  30. # The views and conclusions contained in the software and documentation are those
  31. # of the authors and should not be interpreted as representing official policies,
  32. # either expressed or implied, of the <project name> project.
  33. #
  34. ###############################################################################
  35. ####
  36. # TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/
  37. ####
  38. # Left side of board
  39. set_io --warn-no-port PIN_1 A2
  40. set_io --warn-no-port PIN_2 A1
  41. set_io --warn-no-port PIN_3 B1
  42. set_io --warn-no-port PIN_4 C2
  43. set_io --warn-no-port PIN_5 C1
  44. set_io --warn-no-port PIN_6 D2
  45. set_io --warn-no-port PIN_7 D1
  46. set_io --warn-no-port PIN_8 E2
  47. set_io --warn-no-port PIN_9 E1
  48. set_io --warn-no-port PIN_10 G2
  49. set_io --warn-no-port PIN_11 H1
  50. set_io --warn-no-port PIN_12 J1
  51. set_io --warn-no-port PIN_13 H2
  52. # Right side of board
  53. set_io --warn-no-port PIN_14 H9
  54. set_io --warn-no-port PIN_15 D9
  55. set_io --warn-no-port PIN_16 D8
  56. set_io --warn-no-port PIN_17 C9
  57. set_io --warn-no-port PIN_18 A9
  58. set_io --warn-no-port PIN_19 B8
  59. set_io --warn-no-port PIN_20 A8
  60. set_io --warn-no-port PIN_21 B7
  61. set_io --warn-no-port PIN_22 A7
  62. set_io --warn-no-port PIN_23 B6
  63. set_io --warn-no-port PIN_24 A6
  64. # SPI flash interface on bottom of board
  65. set_io --warn-no-port SPI_SS F7
  66. set_io --warn-no-port SPI_SCK G7
  67. set_io --warn-no-port SPI_IO0 G6
  68. set_io --warn-no-port SPI_IO1 H7
  69. set_io --warn-no-port SPI_IO2 H4
  70. set_io --warn-no-port SPI_IO3 J8
  71. # General purpose pins on bottom of board
  72. set_io --warn-no-port PIN_25 G1
  73. set_io --warn-no-port PIN_26 J3
  74. set_io --warn-no-port PIN_27 J4
  75. set_io --warn-no-port PIN_28 G9
  76. set_io --warn-no-port PIN_29 J9
  77. set_io --warn-no-port PIN_30 E8
  78. set_io --warn-no-port PIN_31 J2
  79. # LED
  80. set_io --warn-no-port LED B3
  81. # USB
  82. set_io --warn-no-port USBP B4
  83. set_io --warn-no-port USBN A4
  84. set_io --warn-no-port USBPU A3
  85. # 16MHz clock
  86. set_io --warn-no-port CLK B2 # input