Michael Buesch efa9f177f8 crcgen: Fix make rule 5 gadi atpakaļ
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crcgen @ 1e8118161a fe465a179c Update crcgen 5 gadi atpakaļ
.gitignore fe465a179c Update crcgen 5 gadi atpakaļ
Makefile efa9f177f8 crcgen: Fix make rule 5 gadi atpakaļ
block_ram_mod.v e2542fed3c Add FPGA PHY source code 5 gadi atpakaļ
build_toolchain.sh fd7746c459 build-toolchain: Do not override PYTHONPATH 5 gadi atpakaļ
edge_detect_mod.v e2542fed3c Add FPGA PHY source code 5 gadi atpakaļ
led_blink_mod.v 2a97e0444f fpga: Add LED blinker 5 gadi atpakaļ
main.v 0e4226eb30 phy-fpha: Declare miso as inout 5 gadi atpakaļ
parity_func.v e2542fed3c Add FPGA PHY source code 5 gadi atpakaļ
profibus_phy_mod.v 4db238f9ef phy-fpga: Set CRC error flag 5 gadi atpakaļ
spi_slave_mod.v bf2afdb4e8 fpga: re-arrange pins 5 gadi atpakaļ
sync_signal_mod.v e2542fed3c Add FPGA PHY source code 5 gadi atpakaļ
tinyfpga_bx.pcf e2542fed3c Add FPGA PHY source code 5 gadi atpakaļ
tinyfpga_bx_program.sh 0835c8771e tinyfpga_bx_program: Update bootloader, if required 5 gadi atpakaļ
uart_mod.v 1eabd5e26d uart: Limit sym timer 5 gadi atpakaļ