Michael Buesch b8098b9b5a phy-fpha: Declare miso as inout 5 rokov pred
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.gitignore d51bbe5ae2 Add FPGA PHY source code 5 rokov pred
Makefile 9280b86c0e phy-fpha: Use PLL 5 rokov pred
block_ram_mod.v d51bbe5ae2 Add FPGA PHY source code 5 rokov pred
crcgen.py 582596891f crcgen: Move all tests to test module 5 rokov pred
crcgen_test.py aaeac12a95 crcgen: Run tests in parallel 5 rokov pred
edge_detect_mod.v d51bbe5ae2 Add FPGA PHY source code 5 rokov pred
led_blink_mod.v e7254d162d fpga: Add LED blinker 5 rokov pred
main.v b8098b9b5a phy-fpha: Declare miso as inout 5 rokov pred
parity_func.v d51bbe5ae2 Add FPGA PHY source code 5 rokov pred
profibus_phy_mod.v 46bfec6f56 phy-fpga: Set CRC error flag 5 rokov pred
spi_slave_mod.v 4b4d67b430 fpga: re-arrange pins 5 rokov pred
sync_signal_mod.v d51bbe5ae2 Add FPGA PHY source code 5 rokov pred
tinyfpga_bx.pcf d51bbe5ae2 Add FPGA PHY source code 5 rokov pred
uart_mod.v fb07d30621 uart: Limit sym timer 5 rokov pred