Project home: https://bues.ch Original repository at: https://git.bues.ch/git/crcgen.git
Michael Buesch
754c08730e
generator: Add VHDL support
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README.rst
CRC algorithm code generator
============================
This tool generates synthesizable Verilog code for use in FPGAs to calculate CRC (Cyclic Redundancy Check) checksums.
License
=======
Copyright (c) 2019 Michael Buesch
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
============================
This tool generates synthesizable Verilog code for use in FPGAs to calculate CRC (Cyclic Redundancy Check) checksums.
License
=======
Copyright (c) 2019 Michael Buesch
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.