lbmk/config/coreboot/default/patches/0039-fix-sata-ports-on-dell-9020-sff-and-mt.patch

From 4889f08306f1530211dcc6f6a4e999c6cc72f3ac Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 30 Mar 2024 05:57:54 +0000
Subject: [PATCH 1/1] fix sata ports on dell 9020 sff and mt

mate kukri has a patch under review on coreboot that sets
sata port map to 0x7 on sff and 0xf on mt.

see: intel 8 series pch datasheet, section 13.1.35

basically, the 6 least significant bits enable the sata
slots; 1 for enable and 0 for disable. there can be up
to 6 ports. least significant bit is port 0, then next
is port 1, and so on.

coreboot currently enables ports 0, 1, 4 and 5, making this
value 0x33 (converted to binary: 00110011). sff has ports
0, 1 and 2 wired, so mate changed that to 0x7 (00000111).

on mt, the blue ports are ports 0 and 1, but the two white
ports don't work, but coreboot enables 4 and 5; it is
likely that the blue ports are in fact 0 and 1, and the
white ports are 2 and 3, but we've not tested this!

it could be that the blue ports are ports 4 and 5, and
the white ports are 2 and 3! we have not yet determined
this, but mate set it to 0xf, meaning ports 0 1 2 and 3
are enabled, in his patch under review. the chance that
it's 2, 3, 4 and 5 on the board is unlikely, but it is
theoretically possible and has not been confirmed.

therefore, for now, i will set the value to 0x3f, which
in binary is 00111111, thus enabling all 6 slots. the two
that aren't physically wired don't really matter. enabling
ports (from the pch) that electrically aren't there and
then powering on is electrically equivalent to those ports
being actually being wired, but with no devices plugged
into them. therefore, 0x3f is an effective shotgun fix.

i'll remove this patch and use mate's fix when the latter
has been tested on MT; it has already been tested on SFF.

this patch fixes the 3rd sata slot on 9020 sff, and the 3rd
and 4th sata slots on 9020 MT

Signed-off-by: Leah Rowe <info@minifree.org>
---
 src/mainboard/dell/optiplex_9020/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
index c0b17a15ff..7bfa6736a6 100644
--- a/src/mainboard/dell/optiplex_9020/devicetree.cb
+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
@@ -23,7 +23,7 @@ chip northbridge/intel/haswell
 			register "gen2_dec" = "0x007c0901"
 			register "gen3_dec" = "0x003c07e1"
 			register "gen4_dec" = "0x001c0901"
-			register "sata_port_map" = "0x33"
+			register "sata_port_map" = "0x3f"
 
 			device pci 14.0 on  end				# xHCI controller
 			device pci 16.0 on  end				# Management Engine interface 1
-- 
2.39.2