0034-mb-hp-Add-Elitebook-8560w-as-an-HP-Sandy-Ivy-Bridge-.patch 83 KB

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  1. From dac71d8ed89f1f1d295157aa62c678e35a320222 Mon Sep 17 00:00:00 2001
  2. From: Iru Cai <mytbk920423@gmail.com>
  3. Date: Tue, 5 Mar 2019 16:27:36 +0800
  4. Subject: [PATCH] mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop
  5. variant
  6. Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950
  7. Signed-off-by: Iru Cai <mytbk920423@gmail.com>
  8. ---
  9. Documentation/mainboard/hp/8560w.md | 82 +++++++
  10. Documentation/mainboard/hp/8560w_flash.webp | Bin 0 -> 51432 bytes
  11. Documentation/mainboard/index.md | 1 +
  12. src/mainboard/hp/snb_ivb_laptops/Kconfig | 10 +-
  13. src/mainboard/hp/snb_ivb_laptops/Kconfig.name | 3 +
  14. .../variants/8560w/board_info.txt | 7 +
  15. .../variants/8560w/early_init.c | 36 +++
  16. .../hp/snb_ivb_laptops/variants/8560w/gpio.c | 224 ++++++++++++++++++
  17. .../snb_ivb_laptops/variants/8560w/hda_verb.c | 25 ++
  18. .../variants/8560w/overridetree.cb | 51 ++++
  19. 10 files changed, 438 insertions(+), 1 deletion(-)
  20. create mode 100644 Documentation/mainboard/hp/8560w.md
  21. create mode 100644 Documentation/mainboard/hp/8560w_flash.webp
  22. create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt
  23. create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c
  24. create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c
  25. create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c
  26. create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb
  27. diff --git a/Documentation/mainboard/hp/8560w.md b/Documentation/mainboard/hp/8560w.md
  28. new file mode 100644
  29. index 0000000000..cc35a0be1f
  30. --- /dev/null
  31. +++ b/Documentation/mainboard/hp/8560w.md
  32. @@ -0,0 +1,82 @@
  33. +# HP EliteBook 8560w
  34. +
  35. +This page describes how to run coreboot on the [HP EliteBook 8560w].
  36. +
  37. +## Required proprietary blobs
  38. +
  39. +- Intel Firmware Descriptor, ME and GbE firmware
  40. +- EC: please read [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops)
  41. +
  42. +## Flashing instructions
  43. +
  44. +HP EliteBook 8560w has an 8MiB SOIC-8 flash chip on the bottom of the
  45. +mainboard. You just need to remove the service cover, and use an SOIC-8
  46. +clip to read and flash the chip.
  47. +
  48. +![8560w_chip_location](8560w_flash.webp)
  49. +
  50. +```eval_rst
  51. ++---------------------+------------+
  52. +| Type | Value |
  53. ++=====================+============+
  54. +| Socketed flash | no |
  55. ++---------------------+------------+
  56. +| Model | MX25L6406E |
  57. ++---------------------+------------+
  58. +| Size | 8 MiB |
  59. ++---------------------+------------+
  60. +| Package | SOIC-8 |
  61. ++---------------------+------------+
  62. +| Write protection | no |
  63. ++---------------------+------------+
  64. +| Dual BIOS feature | no |
  65. ++---------------------+------------+
  66. +| In circuit flashing | yes |
  67. ++---------------------+------------+
  68. +| Internal flashing | yes |
  69. ++---------------------+------------+
  70. +```
  71. +
  72. +## Untested
  73. +
  74. +- mainboards with 4 memory slots
  75. +
  76. +## Working
  77. +
  78. +- i7-2720QM, 8G+8G
  79. +- Arch Linux boot from SeaBIOS payload
  80. +- EHCI debug: the port is beside the eSATA port
  81. +- SATA
  82. +- eSATA
  83. +- USB2 and USB3
  84. +- keyboard
  85. +- Gigabit Ethernet
  86. +- WLAN
  87. +- WWAN
  88. +- VGA and DisplayPort
  89. +- audio
  90. +- EC ACPI
  91. +- Using `me_cleaner`
  92. +- dock: PS/2 keyboard, USB, DisplayPort
  93. +- TPM
  94. +- S3 suspend/resume
  95. +
  96. +## Technology
  97. +
  98. +```eval_rst
  99. ++------------------+--------------------------------------------------+
  100. +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
  101. ++------------------+--------------------------------------------------+
  102. +| Southbridge | bd82x6x |
  103. ++------------------+--------------------------------------------------+
  104. +| CPU | model_206ax |
  105. ++------------------+--------------------------------------------------+
  106. +| Super I/O | SMSC LPC47n217 |
  107. ++------------------+--------------------------------------------------+
  108. +| EC | SMSC KBC1126 |
  109. ++------------------+--------------------------------------------------+
  110. +| Coprocessor | Intel Management Engine |
  111. ++------------------+--------------------------------------------------+
  112. +```
  113. +
  114. +[HP EliteBook 8560w]: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/5071171
  115. diff --git a/Documentation/mainboard/hp/8560w_flash.webp b/Documentation/mainboard/hp/8560w_flash.webp
  116. new file mode 100644
  117. index 0000000000000000000000000000000000000000..b8295bc6e920a4c59c4282e419200569672e8267
  118. GIT binary patch
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  1106. G|JeY!zvB4-
  1107. literal 0
  1108. HcmV?d00001
  1109. diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
  1110. index 519d88873c..a6be27ae09 100644
  1111. --- a/Documentation/mainboard/index.md
  1112. +++ b/Documentation/mainboard/index.md
  1113. @@ -84,6 +84,7 @@ The boards in this section are not real mainboards, but emulators.
  1114. - [HP Sure Start](hp/hp_sure_start.md)
  1115. - [EliteBook 2170p](hp/2170p.md)
  1116. - [EliteBook 2560p](hp/2560p.md)
  1117. +- [EliteBook 8560w](hp/8560w.md)
  1118. - [EliteBook 8760w](hp/8760w.md)
  1119. - [EliteBook Folio 9480m](hp/folio_9480m.md)
  1120. - [EliteBook 820 G2](hp/elitebook_820_g2.md)
  1121. diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig
  1122. index f0bd55f64f..f180bca87f 100644
  1123. --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig
  1124. +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig
  1125. @@ -69,6 +69,12 @@ config BOARD_HP_8470P
  1126. select SOUTHBRIDGE_INTEL_C216
  1127. select SUPERIO_SMSC_LPC47N217
  1128. +config BOARD_HP_8560W
  1129. + select BOARD_HP_SNB_IVB_LAPTOPS_COMMON
  1130. + select BOARD_ROMSIZE_KB_8192
  1131. + select SOUTHBRIDGE_INTEL_BD82X6X
  1132. + select SUPERIO_SMSC_LPC47N217
  1133. +
  1134. config BOARD_HP_8770W
  1135. select BOARD_HP_SNB_IVB_LAPTOPS_COMMON
  1136. select BOARD_ROMSIZE_KB_16384
  1137. @@ -118,6 +124,7 @@ config VARIANT_DIR
  1138. default "2760p" if BOARD_HP_2760P
  1139. default "8460p" if BOARD_HP_8460P
  1140. default "8470p" if BOARD_HP_8470P
  1141. + default "8560w" if BOARD_HP_8560W
  1142. default "8770w" if BOARD_HP_8770W
  1143. default "folio_9470m" if BOARD_HP_FOLIO_9470M
  1144. default "probook_6360b" if BOARD_HP_PROBOOK_6360B
  1145. @@ -130,6 +137,7 @@ config MAINBOARD_PART_NUMBER
  1146. default "EliteBook 2760p" if BOARD_HP_2760P
  1147. default "EliteBook 8460p" if BOARD_HP_8460P
  1148. default "EliteBook 8470p" if BOARD_HP_8470P
  1149. + default "EliteBook 8560w" if BOARD_HP_8560W
  1150. default "EliteBook 8770w" if BOARD_HP_8770W
  1151. default "EliteBook Folio 9470m" if BOARD_HP_FOLIO_9470M
  1152. default "ProBook 6360b" if BOARD_HP_PROBOOK_6360B
  1153. @@ -146,7 +154,7 @@ config VGA_BIOS_ID
  1154. config USBDEBUG_HCD_INDEX
  1155. int
  1156. default 0 if BOARD_HP_2170P || BOARD_HP_FOLIO_9470M
  1157. - default 1 if BOARD_HP_2560P || BOARD_HP_2760P || BOARD_HP_8460P
  1158. + default 1 if BOARD_HP_2560P || BOARD_HP_2760P || BOARD_HP_8460P || BOARD_HP_8560W
  1159. default 2 if BOARD_HP_2570P || BOARD_HP_8470P || BOARD_HP_8770W
  1160. default 1 if BOARD_HP_PROBOOK_6360B # FIXME: check this
  1161. default 2 if BOARD_HP_REVOLVE_810_G1 # FIXME: check this
  1162. diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name
  1163. index f72e0f622a..fdd1b93bd7 100644
  1164. --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name
  1165. +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name
  1166. @@ -18,6 +18,9 @@ config BOARD_HP_8460P
  1167. config BOARD_HP_8470P
  1168. bool "EliteBook 8470p"
  1169. +config BOARD_HP_8560W
  1170. + bool "EliteBook 8560w"
  1171. +
  1172. config BOARD_HP_8770W
  1173. bool "EliteBook 8770w"
  1174. diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt
  1175. new file mode 100644
  1176. index 0000000000..558e904a94
  1177. --- /dev/null
  1178. +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt
  1179. @@ -0,0 +1,7 @@
  1180. +Category: laptop
  1181. +Board URL: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/5071171
  1182. +ROM package: SOIC-8
  1183. +ROM protocol: SPI
  1184. +ROM socketed: n
  1185. +Flashrom support: y
  1186. +Release year: 2011
  1187. diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c
  1188. new file mode 100644
  1189. index 0000000000..20c4b68911
  1190. --- /dev/null
  1191. +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c
  1192. @@ -0,0 +1,36 @@
  1193. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  1194. +
  1195. +#include <bootblock_common.h>
  1196. +#include <southbridge/intel/bd82x6x/pch.h>
  1197. +#include <superio/smsc/lpc47n217/lpc47n217.h>
  1198. +#include <ec/hp/kbc1126/ec.h>
  1199. +
  1200. +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
  1201. +
  1202. +const struct southbridge_usb_port mainboard_usb_ports[] = {
  1203. + { 1, 1, 0 }, /* USB0 */
  1204. + { 1, 1, 0 }, /* USB1 */
  1205. + { 1, 1, 1 }, /* eSATA */
  1206. + { 1, 1, 1 }, /* camera */
  1207. + { 0, 0, 2 },
  1208. + { 1, 0, 2 }, /* bluetooth */
  1209. + { 0, 0, 3 },
  1210. + { 1, 0, 3 },
  1211. + { 0, 1, 4 },
  1212. + { 1, 1, 4 }, /* WWAN */
  1213. + { 1, 0, 5 },
  1214. + { 1, 0, 5 }, /* dock */
  1215. + { 1, 0, 6 },
  1216. + { 1, 0, 6 },
  1217. +};
  1218. +
  1219. +void bootblock_mainboard_early_init(void)
  1220. +{
  1221. + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  1222. + kbc1126_enter_conf();
  1223. + kbc1126_mailbox_init();
  1224. + kbc1126_kbc_init();
  1225. + kbc1126_ec_init();
  1226. + kbc1126_pm1_init();
  1227. + kbc1126_exit_conf();
  1228. +}
  1229. diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c
  1230. new file mode 100644
  1231. index 0000000000..560d668d6f
  1232. --- /dev/null
  1233. +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c
  1234. @@ -0,0 +1,224 @@
  1235. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  1236. +
  1237. +#include <southbridge/intel/common/gpio.h>
  1238. +
  1239. +static const struct pch_gpio_set1 pch_gpio_set1_mode = {
  1240. + .gpio0 = GPIO_MODE_GPIO,
  1241. + .gpio1 = GPIO_MODE_GPIO,
  1242. + .gpio2 = GPIO_MODE_GPIO,
  1243. + .gpio3 = GPIO_MODE_GPIO,
  1244. + .gpio4 = GPIO_MODE_GPIO,
  1245. + .gpio5 = GPIO_MODE_NATIVE,
  1246. + .gpio6 = GPIO_MODE_GPIO,
  1247. + .gpio7 = GPIO_MODE_GPIO,
  1248. + .gpio8 = GPIO_MODE_GPIO,
  1249. + .gpio9 = GPIO_MODE_NATIVE,
  1250. + .gpio10 = GPIO_MODE_GPIO,
  1251. + .gpio11 = GPIO_MODE_GPIO,
  1252. + .gpio12 = GPIO_MODE_NATIVE,
  1253. + .gpio13 = GPIO_MODE_GPIO,
  1254. + .gpio14 = GPIO_MODE_GPIO,
  1255. + .gpio15 = GPIO_MODE_GPIO,
  1256. + .gpio16 = GPIO_MODE_GPIO,
  1257. + .gpio17 = GPIO_MODE_GPIO,
  1258. + .gpio18 = GPIO_MODE_NATIVE,
  1259. + .gpio19 = GPIO_MODE_GPIO,
  1260. + .gpio20 = GPIO_MODE_NATIVE,
  1261. + .gpio21 = GPIO_MODE_GPIO,
  1262. + .gpio22 = GPIO_MODE_GPIO,
  1263. + .gpio23 = GPIO_MODE_GPIO,
  1264. + .gpio24 = GPIO_MODE_GPIO,
  1265. + .gpio25 = GPIO_MODE_NATIVE,
  1266. + .gpio26 = GPIO_MODE_NATIVE,
  1267. + .gpio27 = GPIO_MODE_GPIO,
  1268. + .gpio28 = GPIO_MODE_GPIO,
  1269. + .gpio29 = GPIO_MODE_GPIO,
  1270. + .gpio30 = GPIO_MODE_NATIVE,
  1271. + .gpio31 = GPIO_MODE_NATIVE,
  1272. +};
  1273. +
  1274. +static const struct pch_gpio_set1 pch_gpio_set1_direction = {
  1275. + .gpio0 = GPIO_DIR_OUTPUT,
  1276. + .gpio1 = GPIO_DIR_INPUT,
  1277. + .gpio2 = GPIO_DIR_INPUT,
  1278. + .gpio3 = GPIO_DIR_INPUT,
  1279. + .gpio4 = GPIO_DIR_INPUT,
  1280. + .gpio6 = GPIO_DIR_INPUT,
  1281. + .gpio7 = GPIO_DIR_INPUT,
  1282. + .gpio8 = GPIO_DIR_INPUT,
  1283. + .gpio10 = GPIO_DIR_INPUT,
  1284. + .gpio11 = GPIO_DIR_OUTPUT,
  1285. + .gpio13 = GPIO_DIR_INPUT,
  1286. + .gpio14 = GPIO_DIR_INPUT,
  1287. + .gpio15 = GPIO_DIR_INPUT,
  1288. + .gpio16 = GPIO_DIR_INPUT,
  1289. + .gpio17 = GPIO_DIR_OUTPUT,
  1290. + .gpio19 = GPIO_DIR_INPUT,
  1291. + .gpio21 = GPIO_DIR_INPUT,
  1292. + .gpio22 = GPIO_DIR_OUTPUT,
  1293. + .gpio23 = GPIO_DIR_INPUT,
  1294. + .gpio24 = GPIO_DIR_OUTPUT,
  1295. + .gpio27 = GPIO_DIR_OUTPUT,
  1296. + .gpio28 = GPIO_DIR_OUTPUT,
  1297. + .gpio29 = GPIO_DIR_OUTPUT,
  1298. +};
  1299. +
  1300. +static const struct pch_gpio_set1 pch_gpio_set1_level = {
  1301. + .gpio0 = GPIO_LEVEL_LOW,
  1302. + .gpio11 = GPIO_LEVEL_LOW,
  1303. + .gpio17 = GPIO_LEVEL_HIGH,
  1304. + .gpio22 = GPIO_LEVEL_HIGH,
  1305. + .gpio24 = GPIO_LEVEL_HIGH,
  1306. + .gpio27 = GPIO_LEVEL_LOW,
  1307. + .gpio28 = GPIO_LEVEL_LOW,
  1308. + .gpio29 = GPIO_LEVEL_HIGH,
  1309. +};
  1310. +
  1311. +static const struct pch_gpio_set1 pch_gpio_set1_reset = {
  1312. + .gpio24 = GPIO_RESET_RSMRST,
  1313. + .gpio30 = GPIO_RESET_RSMRST,
  1314. +};
  1315. +
  1316. +static const struct pch_gpio_set1 pch_gpio_set1_invert = {
  1317. + .gpio1 = GPIO_INVERT,
  1318. + .gpio3 = GPIO_INVERT,
  1319. + .gpio6 = GPIO_INVERT,
  1320. + .gpio7 = GPIO_INVERT,
  1321. + .gpio10 = GPIO_INVERT,
  1322. + .gpio13 = GPIO_INVERT,
  1323. + .gpio14 = GPIO_INVERT,
  1324. +};
  1325. +
  1326. +static const struct pch_gpio_set1 pch_gpio_set1_blink = {
  1327. +};
  1328. +
  1329. +static const struct pch_gpio_set2 pch_gpio_set2_mode = {
  1330. + .gpio32 = GPIO_MODE_NATIVE,
  1331. + .gpio33 = GPIO_MODE_GPIO,
  1332. + .gpio34 = GPIO_MODE_GPIO,
  1333. + .gpio35 = GPIO_MODE_GPIO,
  1334. + .gpio36 = GPIO_MODE_NATIVE,
  1335. + .gpio37 = GPIO_MODE_GPIO,
  1336. + .gpio38 = GPIO_MODE_GPIO,
  1337. + .gpio39 = GPIO_MODE_GPIO,
  1338. + .gpio40 = GPIO_MODE_NATIVE,
  1339. + .gpio41 = GPIO_MODE_NATIVE,
  1340. + .gpio42 = GPIO_MODE_NATIVE,
  1341. + .gpio43 = GPIO_MODE_NATIVE,
  1342. + .gpio44 = GPIO_MODE_GPIO,
  1343. + .gpio45 = GPIO_MODE_NATIVE,
  1344. + .gpio46 = GPIO_MODE_GPIO,
  1345. + .gpio47 = GPIO_MODE_NATIVE,
  1346. + .gpio48 = GPIO_MODE_GPIO,
  1347. + .gpio49 = GPIO_MODE_GPIO,
  1348. + .gpio50 = GPIO_MODE_GPIO,
  1349. + .gpio51 = GPIO_MODE_GPIO,
  1350. + .gpio52 = GPIO_MODE_GPIO,
  1351. + .gpio53 = GPIO_MODE_GPIO,
  1352. + .gpio54 = GPIO_MODE_GPIO,
  1353. + .gpio55 = GPIO_MODE_GPIO,
  1354. + .gpio56 = GPIO_MODE_NATIVE,
  1355. + .gpio57 = GPIO_MODE_GPIO,
  1356. + .gpio58 = GPIO_MODE_NATIVE,
  1357. + .gpio59 = GPIO_MODE_NATIVE,
  1358. + .gpio60 = GPIO_MODE_GPIO,
  1359. + .gpio61 = GPIO_MODE_GPIO,
  1360. + .gpio62 = GPIO_MODE_NATIVE,
  1361. + .gpio63 = GPIO_MODE_NATIVE,
  1362. +};
  1363. +
  1364. +static const struct pch_gpio_set2 pch_gpio_set2_direction = {
  1365. + .gpio33 = GPIO_DIR_OUTPUT,
  1366. + .gpio34 = GPIO_DIR_INPUT,
  1367. + .gpio35 = GPIO_DIR_OUTPUT,
  1368. + .gpio37 = GPIO_DIR_OUTPUT,
  1369. + .gpio38 = GPIO_DIR_INPUT,
  1370. + .gpio39 = GPIO_DIR_INPUT,
  1371. + .gpio44 = GPIO_DIR_INPUT,
  1372. + .gpio46 = GPIO_DIR_INPUT,
  1373. + .gpio48 = GPIO_DIR_INPUT,
  1374. + .gpio49 = GPIO_DIR_OUTPUT,
  1375. + .gpio50 = GPIO_DIR_INPUT,
  1376. + .gpio51 = GPIO_DIR_INPUT,
  1377. + .gpio52 = GPIO_DIR_INPUT,
  1378. + .gpio53 = GPIO_DIR_OUTPUT,
  1379. + .gpio54 = GPIO_DIR_INPUT,
  1380. + .gpio55 = GPIO_DIR_INPUT,
  1381. + .gpio57 = GPIO_DIR_OUTPUT,
  1382. + .gpio60 = GPIO_DIR_OUTPUT,
  1383. + .gpio61 = GPIO_DIR_OUTPUT,
  1384. +};
  1385. +
  1386. +static const struct pch_gpio_set2 pch_gpio_set2_level = {
  1387. + .gpio33 = GPIO_LEVEL_LOW,
  1388. + .gpio35 = GPIO_LEVEL_LOW,
  1389. + .gpio37 = GPIO_LEVEL_LOW,
  1390. + .gpio49 = GPIO_LEVEL_LOW,
  1391. + .gpio53 = GPIO_LEVEL_HIGH,
  1392. + .gpio57 = GPIO_LEVEL_LOW,
  1393. + .gpio60 = GPIO_LEVEL_HIGH,
  1394. + .gpio61 = GPIO_LEVEL_HIGH,
  1395. +};
  1396. +
  1397. +static const struct pch_gpio_set2 pch_gpio_set2_reset = {
  1398. +};
  1399. +
  1400. +static const struct pch_gpio_set3 pch_gpio_set3_mode = {
  1401. + .gpio64 = GPIO_MODE_NATIVE,
  1402. + .gpio65 = GPIO_MODE_NATIVE,
  1403. + .gpio66 = GPIO_MODE_NATIVE,
  1404. + .gpio67 = GPIO_MODE_NATIVE,
  1405. + .gpio68 = GPIO_MODE_GPIO,
  1406. + .gpio69 = GPIO_MODE_GPIO,
  1407. + .gpio70 = GPIO_MODE_GPIO,
  1408. + .gpio71 = GPIO_MODE_GPIO,
  1409. + .gpio72 = GPIO_MODE_GPIO,
  1410. + .gpio73 = GPIO_MODE_GPIO,
  1411. + .gpio74 = GPIO_MODE_GPIO,
  1412. + .gpio75 = GPIO_MODE_NATIVE,
  1413. +};
  1414. +
  1415. +static const struct pch_gpio_set3 pch_gpio_set3_direction = {
  1416. + .gpio68 = GPIO_DIR_OUTPUT,
  1417. + .gpio69 = GPIO_DIR_INPUT,
  1418. + .gpio70 = GPIO_DIR_OUTPUT,
  1419. + .gpio71 = GPIO_DIR_OUTPUT,
  1420. + .gpio72 = GPIO_DIR_OUTPUT,
  1421. + .gpio73 = GPIO_DIR_OUTPUT,
  1422. + .gpio74 = GPIO_DIR_OUTPUT,
  1423. +};
  1424. +
  1425. +static const struct pch_gpio_set3 pch_gpio_set3_level = {
  1426. + .gpio68 = GPIO_LEVEL_HIGH,
  1427. + .gpio70 = GPIO_LEVEL_HIGH,
  1428. + .gpio71 = GPIO_LEVEL_HIGH,
  1429. + .gpio72 = GPIO_LEVEL_LOW,
  1430. + .gpio73 = GPIO_LEVEL_HIGH,
  1431. + .gpio74 = GPIO_LEVEL_HIGH,
  1432. +};
  1433. +
  1434. +static const struct pch_gpio_set3 pch_gpio_set3_reset = {
  1435. +};
  1436. +
  1437. +const struct pch_gpio_map mainboard_gpio_map = {
  1438. + .set1 = {
  1439. + .mode = &pch_gpio_set1_mode,
  1440. + .direction = &pch_gpio_set1_direction,
  1441. + .level = &pch_gpio_set1_level,
  1442. + .blink = &pch_gpio_set1_blink,
  1443. + .invert = &pch_gpio_set1_invert,
  1444. + .reset = &pch_gpio_set1_reset,
  1445. + },
  1446. + .set2 = {
  1447. + .mode = &pch_gpio_set2_mode,
  1448. + .direction = &pch_gpio_set2_direction,
  1449. + .level = &pch_gpio_set2_level,
  1450. + .reset = &pch_gpio_set2_reset,
  1451. + },
  1452. + .set3 = {
  1453. + .mode = &pch_gpio_set3_mode,
  1454. + .direction = &pch_gpio_set3_direction,
  1455. + .level = &pch_gpio_set3_level,
  1456. + .reset = &pch_gpio_set3_reset,
  1457. + },
  1458. +};
  1459. diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c
  1460. new file mode 100644
  1461. index 0000000000..2f5469fc84
  1462. --- /dev/null
  1463. +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c
  1464. @@ -0,0 +1,25 @@
  1465. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  1466. +
  1467. +#include <device/azalia_device.h>
  1468. +
  1469. +const u32 cim_verb_data[] = {
  1470. + 0x111d7605, /* Codec Vendor / Device ID: IDT */
  1471. + 0x103c1631, /* Subsystem ID */
  1472. +
  1473. + 11, /* Number of 4 dword sets */
  1474. + AZALIA_SUBVENDOR(0, 0x103c1631),
  1475. + AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0),
  1476. + AZALIA_PIN_CFG(0, 0x0b, 0x0421401f),
  1477. + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020),
  1478. + AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
  1479. + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0),
  1480. + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0),
  1481. + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0),
  1482. + AZALIA_PIN_CFG(0, 0x11, 0x90a60130),
  1483. + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0),
  1484. + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0),
  1485. +};
  1486. +
  1487. +const u32 pc_beep_verbs[0] = {};
  1488. +
  1489. +AZALIA_ARRAY_SIZES;
  1490. diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb
  1491. new file mode 100644
  1492. index 0000000000..4264270ad0
  1493. --- /dev/null
  1494. +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb
  1495. @@ -0,0 +1,51 @@
  1496. +# SPDX-License-Identifier: GPL-2.0-or-later
  1497. +
  1498. +chip northbridge/intel/sandybridge
  1499. + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
  1500. + device domain 0 on
  1501. + subsystemid 0x103c 0x1631 inherit
  1502. + device pci 01.0 on end # PCIe Bridge for discrete graphics
  1503. + device pci 02.0 off end # Internal graphics
  1504. +
  1505. + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
  1506. + register "docking_supported" = "0"
  1507. + register "gen1_dec" = "0x007c0201"
  1508. + register "gen2_dec" = "0x000c0101"
  1509. + register "gen3_dec" = "0x00fcfe01"
  1510. + register "gen4_dec" = "0x000402e9"
  1511. + register "gpi6_routing" = "2"
  1512. + register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
  1513. + # HDD(0), ODD(1), eSATA(4)
  1514. + register "sata_port_map" = "0x3b"
  1515. +
  1516. + device pci 1c.0 on end # PCIe Port #1, WWAN
  1517. + device pci 1c.1 on end # PCIe Port #2, ExpressCard
  1518. + device pci 1c.2 on end # PCIe Port #3, SD/MMC
  1519. + device pci 1c.3 on end # PCIe Port #4, WLAN
  1520. + device pci 1c.4 off end # PCIe Port #5
  1521. + device pci 1c.5 off end # PCIe Port #6
  1522. + device pci 1c.6 off end # PCIe Port #7
  1523. + device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller
  1524. + device pci 1f.0 on # LPC bridge
  1525. + chip ec/hp/kbc1126
  1526. + register "ec_data_port" = "0x60"
  1527. + register "ec_cmd_port" = "0x64"
  1528. + register "ec_ctrl_reg" = "0xca"
  1529. + register "ec_fan_ctrl_value" = "0x6b"
  1530. + device pnp ff.1 off end
  1531. + end
  1532. + chip superio/smsc/lpc47n217
  1533. + device pnp 4e.3 on # Parallel
  1534. + io 0x60 = 0x378
  1535. + irq 0x70 = 7
  1536. + end
  1537. + device pnp 4e.4 on # COM1
  1538. + io 0x60 = 0x3f8
  1539. + irq 0x70 = 4
  1540. + end
  1541. + device pnp 4e.5 off end # COM2
  1542. + end
  1543. + end
  1544. + end
  1545. + end
  1546. +end
  1547. --
  1548. 2.43.0