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  7. <meta name="generator" content="Asciidoctor 2.0.11">
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  8. <meta name="description" content="The perfect emulation setup to study and develop the &lt;&lt;linux-kernel&gt;&gt; v5.9.2, kernel modules, &lt;&lt;qemu-buildroot-setup,QEMU&gt;&gt;, &lt;&lt;gem5-buildroot-setup,gem5&gt;&gt; and x86_64, ARMv7 and ARMv8 &lt;&lt;userland-assembly,userland&gt;&gt; and &lt;&lt;baremetal-setup,baremetal&gt;&gt; assembly, &lt;&lt;c,ANSI C&gt;&gt;, &lt;&lt;cpp,C++&gt;&gt; and &lt;&lt;posix,POSIX&gt;&gt;. &lt;&lt;gdb&gt;&gt; and &lt;&lt;kgdb&gt;&gt; just work. Powered by &lt;&lt;about-the-qemu-buildroot-setup,Buildroot&gt;&gt; and &lt;&lt;about-the-baremetal-setup,crosstool-NG&gt;&gt;. Highly automated. Thoroughly documented. Automated &lt;&lt;test-this-repo,tests&gt;&gt;. "Tested" in an Ubuntu 20.04 host.">
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  9. <title>Linux Kernel Module Cheat</title>
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    453. 

  453. </head>
    454. 

  454. <body id="gem5-mshr" class="article">
    455. 

  455. <div id="header">
    456. 

  456. <h1>Linux Kernel Module Cheat</h1>
    457. 

  457. </div>
    458. 

  458. <div id="content">
    459. 

  459. <div class="sect3">
    460. 

  460. <h4 id="gem5-mshr"><a class="anchor" href="#gem5-mshr"></a><a class="link" href="#gem5-mshr">24.21.3. gem5 <code>MSHR</code></a></h4>
    461. 

  461. <div class="paragraph">
    462. 

  462. <p>Mentioned at: <a href="http://pages.cs.wisc.edu/~swilson/gem5-docs/gem5MemorySystem.html" class="bare">http://pages.cs.wisc.edu/~swilson/gem5-docs/gem5MemorySystem.html</a></p>
    463. 

  463. </div>
    464. 

  464. <div class="paragraph">
    465. 

  465. <p>Each cache object owns a <code>MSHRQueue</code>:</p>
    466. 

  466. </div>
    467. 

  467. <div class="literalblock">
    468. 

  468. <div class="content">
    469. 

  469. <pre>class BaseCache : public ClockedObject
    470. 

  470. {
    471. 

  471.     /** Miss status registers */
    472. 

  472.     MSHRQueue mshrQueue;</pre>
    473. 

  473. </div>
    474. 

  474. </div>
    475. 

  475. <div class="paragraph">
    476. 

  476. <p><code>BaseCache</code> is the base class of <code>Cache</code> and <code>NoncoherentCache</code>.</p>
    477. 

  477. </div>
    478. 

  478. <div class="paragraph">
    479. 

  479. <p><code>MSHRQueue</code> is a <code>Queue</code> of <code>MSHR</code>:</p>
    480. 

  480. </div>
    481. 

  481. <div class="literalblock">
    482. 

  482. <div class="content">
    483. 

  483. <pre>class MSHRQueue : public Queue&lt;MSHR&gt;</pre>
    484. 

  484. </div>
    485. 

  485. </div>
    486. 

  486. <div class="paragraph">
    487. 

  487. <p>and Queue is also a gem5 class under <code>src/mem/cache/queue.hh</code>.</p>
    488. 

  488. </div>
    489. 

  489. <div class="paragraph">
    490. 

  490. <p>The MSHR basically keeps track of all information the cache receives, and helps it take appropriate action. I&#8217;m not sure why it is separate form the cache at all, as it is basically performing essential cache bookkeeping.</p>
    491. 

  491. </div>
    492. 

  492. <div class="paragraph">
    493. 

  493. <p>A clear example of MSHR in action can be seen at: <a href="gem5-event-queue-timingsimplecpu-syscall-emulation-freestanding-example-analysis-with-caches-and-multiple-cpus.html">gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis with caches and multiple CPUs</a>. In that example what happened was:</p>
    494. 

  494. </div>
    495. 

  495. <div class="ulist">
    496. 

  496. <ul>
    497. 

  497. <li>
    498. 

  498. <p>CPU1 writes to an address and it completes</p>
    499. 

  499. </li>
    500. 

  500. <li>
    501. 

  501. <p>CPU2 sends read</p>
    502. 

  502. </li>
    503. 

  503. <li>
    504. 

  504. <p>CPU1 writes to the address again</p>
    505. 

  505. </li>
    506. 

  506. <li>
    507. 

  507. <p>CPU2 snoops the write, and notes it down in its MSHR</p>
    508. 

  508. </li>
    509. 

  509. <li>
    510. 

  510. <p>CPU2 receives a snoop reply for its read, also from CPU1 which has the data and the line becomes valid</p>
    511. 

  511. </li>
    512. 

  512. <li>
    513. 

  513. <p>CPU2 gets its data. But the MSHR remembers that it had also received a write snoop, so it also immediately invalidates that line</p>
    514. 

  514. </li>
    515. 

  515. </ul>
    516. 

  516. </div>
    517. 

  517. <div class="paragraph">
    518. 

  518. <p>From this we understand that MSHR is the part of the cache that synchronizes stuff pending snoops and ensures that things get invalidated.</p>
    519. 

  519. </div>
    520. 

  520. <div class="ulist">
    521. 

  521. <ul>
    522. 

  522. </ul>
    523. 

  523. </div>
    524. 

  524. </div>
    525. 

  525. <div class="paragraph nav-footer">
    526. 

  526. <p>← Previous: <a href="gem5-request-in-timingsimplecpu.html">gem5 <code>Request</code> in <code>TimingSimpleCPU</code></a> | ↑ Up: <a href="gem5-memory-system.html">gem5 memory system</a> | ⌂ Home: <a href="README.html">Linux Kernel Module Cheat</a> | Next: <a href="gem5-commmonitor.html">gem5 <code>CommMonitor</code></a> →</p>
    527. 

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    528. 

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