mddihosti.c 65 KB

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  1. /* Copyright (c) 2008-2010, 2012 The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/slab.h>
  16. #include <linux/delay.h>
  17. #include <linux/mm.h>
  18. #include <linux/fb.h>
  19. #include <linux/init.h>
  20. #include <linux/ioport.h>
  21. #include <linux/device.h>
  22. #include <linux/dma-mapping.h>
  23. #include "msm_fb_panel.h"
  24. #include "mddihost.h"
  25. #include "mddihosti.h"
  26. #define FEATURE_MDDI_UNDERRUN_RECOVERY
  27. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  28. static void mddi_read_rev_packet(byte *data_ptr);
  29. #endif
  30. struct timer_list mddi_host_timer;
  31. #define MDDI_DEFAULT_TIMER_LENGTH 5000 /* 5 seconds */
  32. uint32 mddi_rtd_frequency = 60000; /* send RTD every 60 seconds */
  33. uint32 mddi_client_status_frequency = 60000; /* get status pkt every 60 secs */
  34. boolean mddi_vsync_detect_enabled = FALSE;
  35. mddi_gpio_info_type mddi_gpio;
  36. uint32 mddi_host_core_version;
  37. boolean mddi_debug_log_statistics = FALSE;
  38. /* #define FEATURE_MDDI_HOST_ENABLE_EARLY_HIBERNATION */
  39. /* default to TRUE in case MDP does not vote */
  40. static boolean mddi_host_mdp_active_flag = TRUE;
  41. static uint32 mddi_log_stats_counter;
  42. uint32 mddi_log_stats_frequency = 4000;
  43. int32 mddi_client_type;
  44. #define MDDI_DEFAULT_REV_PKT_SIZE 0x20
  45. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  46. static boolean mddi_rev_ptr_workaround = TRUE;
  47. static uint32 mddi_reg_read_retry;
  48. static uint32 mddi_reg_read_retry_max = 20;
  49. static boolean mddi_enable_reg_read_retry = TRUE;
  50. static boolean mddi_enable_reg_read_retry_once = FALSE;
  51. #define MDDI_MAX_REV_PKT_SIZE 0x60
  52. #define MDDI_CLIENT_CAPABILITY_REV_PKT_SIZE 0x60
  53. #define MDDI_VIDEO_REV_PKT_SIZE 0x40
  54. #define MDDI_REV_BUFFER_SIZE MDDI_MAX_REV_PKT_SIZE
  55. static byte rev_packet_data[MDDI_MAX_REV_PKT_SIZE];
  56. #endif /* FEATURE_MDDI_DISABLE_REVERSE */
  57. /* leave these variables so graphics will compile */
  58. #define MDDI_MAX_REV_DATA_SIZE 128
  59. /*lint -d__align(x) */
  60. boolean mddi_debug_clear_rev_data = TRUE;
  61. uint32 *mddi_reg_read_value_ptr;
  62. mddi_client_capability_type mddi_client_capability_pkt;
  63. static boolean mddi_client_capability_request = FALSE;
  64. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  65. #define MAX_MDDI_REV_HANDLERS 2
  66. #define INVALID_PKT_TYPE 0xFFFF
  67. typedef struct {
  68. mddi_rev_handler_type handler; /* ISR to be executed */
  69. uint16 pkt_type;
  70. } mddi_rev_pkt_handler_type;
  71. static mddi_rev_pkt_handler_type mddi_rev_pkt_handler[MAX_MDDI_REV_HANDLERS] =
  72. { {NULL, INVALID_PKT_TYPE}, {NULL, INVALID_PKT_TYPE} };
  73. static boolean mddi_rev_encap_user_request = FALSE;
  74. static mddi_linked_list_notify_type mddi_rev_user;
  75. spinlock_t mddi_host_spin_lock;
  76. extern uint32 mdp_in_processing;
  77. #endif
  78. typedef enum {
  79. MDDI_REV_IDLE
  80. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  81. , MDDI_REV_REG_READ_ISSUED,
  82. MDDI_REV_REG_READ_SENT,
  83. MDDI_REV_ENCAP_ISSUED,
  84. MDDI_REV_STATUS_REQ_ISSUED,
  85. MDDI_REV_CLIENT_CAP_ISSUED
  86. #endif
  87. } mddi_rev_link_state_type;
  88. typedef enum {
  89. MDDI_LINK_DISABLED,
  90. MDDI_LINK_HIBERNATING,
  91. MDDI_LINK_ACTIVATING,
  92. MDDI_LINK_ACTIVE
  93. } mddi_host_link_state_type;
  94. typedef struct {
  95. uint32 count;
  96. uint32 in_count;
  97. uint32 disp_req_count;
  98. uint32 state_change_count;
  99. uint32 ll_done_count;
  100. uint32 rev_avail_count;
  101. uint32 error_count;
  102. uint32 rev_encap_count;
  103. uint32 llist_ptr_write_1;
  104. uint32 llist_ptr_write_2;
  105. } mddi_host_int_type;
  106. typedef struct {
  107. uint32 fwd_crc_count;
  108. uint32 rev_crc_count;
  109. uint32 pri_underflow;
  110. uint32 sec_underflow;
  111. uint32 rev_overflow;
  112. uint32 pri_overwrite;
  113. uint32 sec_overwrite;
  114. uint32 rev_overwrite;
  115. uint32 dma_failure;
  116. uint32 rtd_failure;
  117. uint32 reg_read_failure;
  118. #ifdef FEATURE_MDDI_UNDERRUN_RECOVERY
  119. uint32 pri_underrun_detected;
  120. #endif
  121. } mddi_host_stat_type;
  122. typedef struct {
  123. uint32 rtd_cnt;
  124. uint32 rev_enc_cnt;
  125. uint32 vid_cnt;
  126. uint32 reg_acc_cnt;
  127. uint32 cli_stat_cnt;
  128. uint32 cli_cap_cnt;
  129. uint32 reg_read_cnt;
  130. uint32 link_active_cnt;
  131. uint32 link_hibernate_cnt;
  132. uint32 vsync_response_cnt;
  133. uint32 fwd_crc_cnt;
  134. uint32 rev_crc_cnt;
  135. } mddi_log_params_struct_type;
  136. typedef struct {
  137. uint32 rtd_value;
  138. uint32 rtd_counter;
  139. uint32 client_status_cnt;
  140. boolean rev_ptr_written;
  141. uint8 *rev_ptr_start;
  142. uint8 *rev_ptr_curr;
  143. uint32 mddi_rev_ptr_write_val;
  144. dma_addr_t rev_data_dma_addr;
  145. uint16 rev_pkt_size;
  146. mddi_rev_link_state_type rev_state;
  147. mddi_host_link_state_type link_state;
  148. mddi_host_driver_state_type driver_state;
  149. boolean disable_hibernation;
  150. uint32 saved_int_reg;
  151. uint32 saved_int_en;
  152. mddi_linked_list_type *llist_ptr;
  153. dma_addr_t llist_dma_addr;
  154. mddi_linked_list_type *llist_dma_ptr;
  155. uint32 *rev_data_buf;
  156. struct completion mddi_llist_avail_comp;
  157. boolean mddi_waiting_for_llist_avail;
  158. mddi_host_int_type int_type;
  159. mddi_host_stat_type stats;
  160. mddi_log_params_struct_type log_parms;
  161. mddi_llist_info_type llist_info;
  162. mddi_linked_list_notify_type llist_notify[MDDI_MAX_NUM_LLIST_ITEMS];
  163. } mddi_host_cntl_type;
  164. static mddi_host_type mddi_curr_host = MDDI_HOST_PRIM;
  165. static mddi_host_cntl_type mhctl[MDDI_NUM_HOST_CORES];
  166. mddi_linked_list_type *llist_extern[MDDI_NUM_HOST_CORES];
  167. mddi_linked_list_type *llist_dma_extern[MDDI_NUM_HOST_CORES];
  168. mddi_linked_list_notify_type *llist_extern_notify[MDDI_NUM_HOST_CORES];
  169. static mddi_log_params_struct_type prev_parms[MDDI_NUM_HOST_CORES];
  170. extern uint32 mdp_total_vdopkts;
  171. static boolean mddi_host_io_clock_on = FALSE;
  172. static boolean mddi_host_hclk_on = FALSE;
  173. int int_mddi_pri_flag = FALSE;
  174. int int_mddi_ext_flag = FALSE;
  175. static void mddi_report_errors(uint32 int_reg)
  176. {
  177. mddi_host_type host_idx = mddi_curr_host;
  178. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  179. if (int_reg & MDDI_INT_PRI_UNDERFLOW) {
  180. pmhctl->stats.pri_underflow++;
  181. MDDI_MSG_ERR("!!! MDDI Primary Underflow !!!\n");
  182. }
  183. if (int_reg & MDDI_INT_SEC_UNDERFLOW) {
  184. pmhctl->stats.sec_underflow++;
  185. MDDI_MSG_ERR("!!! MDDI Secondary Underflow !!!\n");
  186. }
  187. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  188. if (int_reg & MDDI_INT_REV_OVERFLOW) {
  189. pmhctl->stats.rev_overflow++;
  190. MDDI_MSG_ERR("!!! MDDI Reverse Overflow !!!\n");
  191. pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
  192. mddi_host_reg_out(REV_PTR, pmhctl->mddi_rev_ptr_write_val);
  193. }
  194. if (int_reg & MDDI_INT_CRC_ERROR)
  195. MDDI_MSG_ERR("!!! MDDI Reverse CRC Error !!!\n");
  196. #endif
  197. if (int_reg & MDDI_INT_PRI_OVERWRITE) {
  198. pmhctl->stats.pri_overwrite++;
  199. MDDI_MSG_ERR("!!! MDDI Primary Overwrite !!!\n");
  200. }
  201. if (int_reg & MDDI_INT_SEC_OVERWRITE) {
  202. pmhctl->stats.sec_overwrite++;
  203. MDDI_MSG_ERR("!!! MDDI Secondary Overwrite !!!\n");
  204. }
  205. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  206. if (int_reg & MDDI_INT_REV_OVERWRITE) {
  207. pmhctl->stats.rev_overwrite++;
  208. /* This will show up normally and is not a problem */
  209. MDDI_MSG_DEBUG("MDDI Reverse Overwrite!\n");
  210. }
  211. if (int_reg & MDDI_INT_RTD_FAILURE) {
  212. mddi_host_reg_outm(INTEN, MDDI_INT_RTD_FAILURE, 0);
  213. pmhctl->stats.rtd_failure++;
  214. MDDI_MSG_ERR("!!! MDDI RTD Failure !!!\n");
  215. }
  216. #endif
  217. if (int_reg & MDDI_INT_DMA_FAILURE) {
  218. pmhctl->stats.dma_failure++;
  219. MDDI_MSG_ERR("!!! MDDI DMA Abort !!!\n");
  220. }
  221. }
  222. static void mddi_host_enable_io_clock(void)
  223. {
  224. if (!MDDI_HOST_IS_IO_CLOCK_ON)
  225. MDDI_HOST_ENABLE_IO_CLOCK;
  226. }
  227. static void mddi_host_enable_hclk(void)
  228. {
  229. if (!MDDI_HOST_IS_HCLK_ON)
  230. MDDI_HOST_ENABLE_HCLK;
  231. }
  232. static void mddi_host_disable_io_clock(void)
  233. {
  234. #ifndef FEATURE_MDDI_HOST_IO_CLOCK_CONTROL_DISABLE
  235. if (MDDI_HOST_IS_IO_CLOCK_ON)
  236. MDDI_HOST_DISABLE_IO_CLOCK;
  237. #endif
  238. }
  239. static void mddi_host_disable_hclk(void)
  240. {
  241. #ifndef FEATURE_MDDI_HOST_HCLK_CONTROL_DISABLE
  242. if (MDDI_HOST_IS_HCLK_ON)
  243. MDDI_HOST_DISABLE_HCLK;
  244. #endif
  245. }
  246. static void mddi_vote_to_sleep(mddi_host_type host_idx, boolean sleep)
  247. {
  248. uint16 vote_mask;
  249. if (host_idx == MDDI_HOST_PRIM)
  250. vote_mask = 0x01;
  251. else
  252. vote_mask = 0x02;
  253. }
  254. static void mddi_report_state_change(uint32 int_reg)
  255. {
  256. mddi_host_type host_idx = mddi_curr_host;
  257. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  258. if ((pmhctl->saved_int_reg & MDDI_INT_IN_HIBERNATION) &&
  259. (pmhctl->saved_int_reg & MDDI_INT_LINK_ACTIVE)) {
  260. /* recover from condition where the io_clock was turned off by the
  261. clock driver during a transition to hibernation. The io_clock
  262. disable is to prevent MDP/MDDI underruns when changing ARM
  263. clock speeds. In the process of halting the ARM, the hclk
  264. divider needs to be set to 1. When it is set to 1, there is
  265. a small time (usecs) when hclk is off or slow, and this can
  266. cause an underrun. To prevent the underrun, clock driver turns
  267. off the MDDI io_clock before making the change. */
  268. mddi_host_reg_out(CMD, MDDI_CMD_POWERUP);
  269. }
  270. if (int_reg & MDDI_INT_LINK_ACTIVE) {
  271. pmhctl->link_state = MDDI_LINK_ACTIVE;
  272. pmhctl->log_parms.link_active_cnt++;
  273. pmhctl->rtd_value = mddi_host_reg_in(RTD_VAL);
  274. MDDI_MSG_DEBUG("!!! MDDI Active RTD:0x%x!!!\n",
  275. pmhctl->rtd_value);
  276. /* now interrupt on hibernation */
  277. mddi_host_reg_outm(INTEN,
  278. (MDDI_INT_IN_HIBERNATION |
  279. MDDI_INT_LINK_ACTIVE),
  280. MDDI_INT_IN_HIBERNATION);
  281. #ifdef DEBUG_MDDIHOSTI
  282. /* if gpio interrupt is enabled, start polling at fastest
  283. * registered rate
  284. */
  285. if (mddi_gpio.polling_enabled) {
  286. timer_reg(&mddi_gpio_poll_timer,
  287. mddi_gpio_poll_timer_cb, 0, mddi_gpio.polling_interval, 0);
  288. }
  289. #endif
  290. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  291. if (mddi_rev_ptr_workaround) {
  292. /* HW CR: need to reset reverse register stuff */
  293. pmhctl->rev_ptr_written = FALSE;
  294. pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
  295. }
  296. #endif
  297. /* vote on sleep */
  298. mddi_vote_to_sleep(host_idx, FALSE);
  299. if (host_idx == MDDI_HOST_PRIM) {
  300. if (mddi_vsync_detect_enabled) {
  301. /*
  302. * Indicate to client specific code that vsync
  303. * was enabled, but we did not detect a client
  304. * intiated wakeup. The client specific
  305. * handler can either reassert vsync detection,
  306. * or treat this as a valid vsync.
  307. */
  308. mddi_client_lcd_vsync_detected(FALSE);
  309. pmhctl->log_parms.vsync_response_cnt++;
  310. }
  311. }
  312. }
  313. if (int_reg & MDDI_INT_IN_HIBERNATION) {
  314. pmhctl->link_state = MDDI_LINK_HIBERNATING;
  315. pmhctl->log_parms.link_hibernate_cnt++;
  316. MDDI_MSG_DEBUG("!!! MDDI Hibernating !!!\n");
  317. if (mddi_client_type == 2) {
  318. mddi_host_reg_out(PAD_CTL, 0x402a850f);
  319. mddi_host_reg_out(PAD_CAL, 0x10220020);
  320. mddi_host_reg_out(TA1_LEN, 0x0010);
  321. mddi_host_reg_out(TA2_LEN, 0x0040);
  322. }
  323. /* now interrupt on link_active */
  324. #ifdef FEATURE_MDDI_DISABLE_REVERSE
  325. mddi_host_reg_outm(INTEN,
  326. (MDDI_INT_MDDI_IN |
  327. MDDI_INT_IN_HIBERNATION |
  328. MDDI_INT_LINK_ACTIVE),
  329. MDDI_INT_LINK_ACTIVE);
  330. #else
  331. mddi_host_reg_outm(INTEN,
  332. (MDDI_INT_MDDI_IN |
  333. MDDI_INT_IN_HIBERNATION |
  334. MDDI_INT_LINK_ACTIVE),
  335. (MDDI_INT_MDDI_IN | MDDI_INT_LINK_ACTIVE));
  336. pmhctl->rtd_counter = mddi_rtd_frequency;
  337. if (pmhctl->rev_state != MDDI_REV_IDLE) {
  338. /* a rev_encap will not wake up the link, so we do that here */
  339. pmhctl->link_state = MDDI_LINK_ACTIVATING;
  340. mddi_host_reg_out(CMD, MDDI_CMD_LINK_ACTIVE);
  341. }
  342. #endif
  343. if (pmhctl->disable_hibernation) {
  344. mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE);
  345. mddi_host_reg_out(CMD, MDDI_CMD_LINK_ACTIVE);
  346. pmhctl->link_state = MDDI_LINK_ACTIVATING;
  347. }
  348. #ifdef FEATURE_MDDI_UNDERRUN_RECOVERY
  349. if ((pmhctl->llist_info.transmitting_start_idx !=
  350. UNASSIGNED_INDEX)
  351. &&
  352. ((pmhctl->
  353. saved_int_reg & (MDDI_INT_PRI_LINK_LIST_DONE |
  354. MDDI_INT_PRI_PTR_READ)) ==
  355. MDDI_INT_PRI_PTR_READ)) {
  356. mddi_linked_list_type *llist_dma;
  357. llist_dma = pmhctl->llist_dma_ptr;
  358. /*
  359. * All indications are that we have not received a
  360. * linked list done interrupt, due to an underrun
  361. * condition. Recovery attempt is to send again.
  362. */
  363. dma_coherent_pre_ops();
  364. /* Write to primary pointer register again */
  365. mddi_host_reg_out(PRI_PTR,
  366. &llist_dma[pmhctl->llist_info.
  367. transmitting_start_idx]);
  368. pmhctl->stats.pri_underrun_detected++;
  369. }
  370. #endif
  371. /* vote on sleep */
  372. if (pmhctl->link_state == MDDI_LINK_HIBERNATING) {
  373. mddi_vote_to_sleep(host_idx, TRUE);
  374. }
  375. #ifdef DEBUG_MDDIHOSTI
  376. /* need to stop polling timer */
  377. if (mddi_gpio.polling_enabled) {
  378. (void) timer_clr(&mddi_gpio_poll_timer, T_NONE);
  379. }
  380. #endif
  381. }
  382. }
  383. void mddi_host_timer_service(unsigned long data)
  384. {
  385. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  386. unsigned long flags;
  387. #endif
  388. mddi_host_type host_idx;
  389. mddi_host_cntl_type *pmhctl;
  390. unsigned long time_ms = MDDI_DEFAULT_TIMER_LENGTH;
  391. init_timer(&mddi_host_timer);
  392. for (host_idx = MDDI_HOST_PRIM; host_idx < MDDI_NUM_HOST_CORES;
  393. host_idx++) {
  394. pmhctl = &(mhctl[host_idx]);
  395. mddi_log_stats_counter += (uint32) time_ms;
  396. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  397. pmhctl->rtd_counter += (uint32) time_ms;
  398. pmhctl->client_status_cnt += (uint32) time_ms;
  399. if (host_idx == MDDI_HOST_PRIM) {
  400. if (pmhctl->client_status_cnt >=
  401. mddi_client_status_frequency) {
  402. if ((pmhctl->link_state ==
  403. MDDI_LINK_HIBERNATING)
  404. && (pmhctl->client_status_cnt >
  405. mddi_client_status_frequency)) {
  406. /*
  407. * special case where we are hibernating
  408. * and mddi_host_isr is not firing, so
  409. * kick the link so that the status can
  410. * be retrieved
  411. */
  412. /* need to wake up link before issuing
  413. * rev encap command
  414. */
  415. MDDI_MSG_INFO("wake up link!\n");
  416. spin_lock_irqsave(&mddi_host_spin_lock,
  417. flags);
  418. mddi_host_enable_hclk();
  419. mddi_host_enable_io_clock();
  420. pmhctl->link_state =
  421. MDDI_LINK_ACTIVATING;
  422. mddi_host_reg_out(CMD,
  423. MDDI_CMD_LINK_ACTIVE);
  424. spin_unlock_irqrestore
  425. (&mddi_host_spin_lock, flags);
  426. } else
  427. if ((pmhctl->link_state == MDDI_LINK_ACTIVE)
  428. && pmhctl->disable_hibernation) {
  429. /*
  430. * special case where we have disabled
  431. * hibernation and mddi_host_isr
  432. * is not firing, so enable interrupt
  433. * for no pkts pending, which will
  434. * generate an interrupt
  435. */
  436. MDDI_MSG_INFO("kick isr!\n");
  437. spin_lock_irqsave(&mddi_host_spin_lock,
  438. flags);
  439. mddi_host_enable_hclk();
  440. mddi_host_reg_outm(INTEN,
  441. MDDI_INT_NO_CMD_PKTS_PEND,
  442. MDDI_INT_NO_CMD_PKTS_PEND);
  443. spin_unlock_irqrestore
  444. (&mddi_host_spin_lock, flags);
  445. }
  446. }
  447. }
  448. #endif /* #ifndef FEATURE_MDDI_DISABLE_REVERSE */
  449. }
  450. /* Check if logging is turned on */
  451. for (host_idx = MDDI_HOST_PRIM; host_idx < MDDI_NUM_HOST_CORES;
  452. host_idx++) {
  453. mddi_log_params_struct_type *prev_ptr = &(prev_parms[host_idx]);
  454. pmhctl = &(mhctl[host_idx]);
  455. if (mddi_debug_log_statistics) {
  456. /* get video pkt count from MDP, since MDDI sw cannot know this */
  457. pmhctl->log_parms.vid_cnt = mdp_total_vdopkts;
  458. if (mddi_log_stats_counter >= mddi_log_stats_frequency) {
  459. /* mddi_log_stats_counter = 0; */
  460. if (mddi_debug_log_statistics) {
  461. MDDI_MSG_NOTICE
  462. ("MDDI Statistics since last report:\n");
  463. MDDI_MSG_NOTICE(" Packets sent:\n");
  464. MDDI_MSG_NOTICE
  465. (" %d RTD packet(s)\n",
  466. pmhctl->log_parms.rtd_cnt -
  467. prev_ptr->rtd_cnt);
  468. if (prev_ptr->rtd_cnt !=
  469. pmhctl->log_parms.rtd_cnt) {
  470. unsigned long flags;
  471. spin_lock_irqsave
  472. (&mddi_host_spin_lock,
  473. flags);
  474. mddi_host_enable_hclk();
  475. pmhctl->rtd_value =
  476. mddi_host_reg_in(RTD_VAL);
  477. spin_unlock_irqrestore
  478. (&mddi_host_spin_lock,
  479. flags);
  480. MDDI_MSG_NOTICE
  481. (" RTD value=%d\n",
  482. pmhctl->rtd_value);
  483. }
  484. MDDI_MSG_NOTICE
  485. (" %d VIDEO packets\n",
  486. pmhctl->log_parms.vid_cnt -
  487. prev_ptr->vid_cnt);
  488. MDDI_MSG_NOTICE
  489. (" %d Register Access packets\n",
  490. pmhctl->log_parms.reg_acc_cnt -
  491. prev_ptr->reg_acc_cnt);
  492. MDDI_MSG_NOTICE
  493. (" %d Reverse Encapsulation packet(s)\n",
  494. pmhctl->log_parms.rev_enc_cnt -
  495. prev_ptr->rev_enc_cnt);
  496. if (prev_ptr->rev_enc_cnt !=
  497. pmhctl->log_parms.rev_enc_cnt) {
  498. /* report # of reverse CRC errors */
  499. MDDI_MSG_NOTICE
  500. (" %d reverse CRC errors detected\n",
  501. pmhctl->log_parms.
  502. rev_crc_cnt -
  503. prev_ptr->rev_crc_cnt);
  504. }
  505. MDDI_MSG_NOTICE
  506. (" Packets received:\n");
  507. MDDI_MSG_NOTICE
  508. (" %d Client Status packets",
  509. pmhctl->log_parms.cli_stat_cnt -
  510. prev_ptr->cli_stat_cnt);
  511. if (prev_ptr->cli_stat_cnt !=
  512. pmhctl->log_parms.cli_stat_cnt) {
  513. MDDI_MSG_NOTICE
  514. (" %d forward CRC errors reported\n",
  515. pmhctl->log_parms.
  516. fwd_crc_cnt -
  517. prev_ptr->fwd_crc_cnt);
  518. }
  519. MDDI_MSG_NOTICE
  520. (" %d Register Access Read packets\n",
  521. pmhctl->log_parms.reg_read_cnt -
  522. prev_ptr->reg_read_cnt);
  523. if (pmhctl->link_state ==
  524. MDDI_LINK_ACTIVE) {
  525. MDDI_MSG_NOTICE
  526. (" Current Link Status: Active\n");
  527. } else
  528. if ((pmhctl->link_state ==
  529. MDDI_LINK_HIBERNATING)
  530. || (pmhctl->link_state ==
  531. MDDI_LINK_ACTIVATING)) {
  532. MDDI_MSG_NOTICE
  533. (" Current Link Status: Hibernation\n");
  534. } else {
  535. MDDI_MSG_NOTICE
  536. (" Current Link Status: Inactive\n");
  537. }
  538. MDDI_MSG_NOTICE
  539. (" Active state entered %d times\n",
  540. pmhctl->log_parms.link_active_cnt -
  541. prev_ptr->link_active_cnt);
  542. MDDI_MSG_NOTICE
  543. (" Hibernation state entered %d times\n",
  544. pmhctl->log_parms.
  545. link_hibernate_cnt -
  546. prev_ptr->link_hibernate_cnt);
  547. }
  548. }
  549. prev_parms[host_idx] = pmhctl->log_parms;
  550. }
  551. }
  552. if (mddi_log_stats_counter >= mddi_log_stats_frequency)
  553. mddi_log_stats_counter = 0;
  554. mutex_lock(&mddi_timer_lock);
  555. if (!mddi_timer_shutdown_flag) {
  556. mddi_host_timer.function = mddi_host_timer_service;
  557. mddi_host_timer.data = 0;
  558. mddi_host_timer.expires = jiffies + ((time_ms * HZ) / 1000);
  559. add_timer(&mddi_host_timer);
  560. }
  561. mutex_unlock(&mddi_timer_lock);
  562. return;
  563. } /* mddi_host_timer_cb */
  564. static void mddi_process_link_list_done(void)
  565. {
  566. mddi_host_type host_idx = mddi_curr_host;
  567. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  568. /* normal forward linked list packet(s) were sent */
  569. if (pmhctl->llist_info.transmitting_start_idx == UNASSIGNED_INDEX) {
  570. MDDI_MSG_ERR("**** getting LL done, but no list ****\n");
  571. } else {
  572. uint16 idx;
  573. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  574. if (pmhctl->rev_state == MDDI_REV_REG_READ_ISSUED) {
  575. /* special case where a register read packet was sent */
  576. pmhctl->rev_state = MDDI_REV_REG_READ_SENT;
  577. if (pmhctl->llist_info.reg_read_idx == UNASSIGNED_INDEX) {
  578. MDDI_MSG_ERR
  579. ("**** getting LL done, but no list ****\n");
  580. }
  581. }
  582. #endif
  583. for (idx = pmhctl->llist_info.transmitting_start_idx;;) {
  584. uint16 next_idx = pmhctl->llist_notify[idx].next_idx;
  585. /* with reg read we don't release the waiting tcb until after
  586. * the reverse encapsulation has completed.
  587. */
  588. if (idx != pmhctl->llist_info.reg_read_idx) {
  589. /* notify task that may be waiting on this completion */
  590. if (pmhctl->llist_notify[idx].waiting) {
  591. complete(&
  592. (pmhctl->llist_notify[idx].
  593. done_comp));
  594. }
  595. if (pmhctl->llist_notify[idx].done_cb != NULL) {
  596. (*(pmhctl->llist_notify[idx].done_cb))
  597. ();
  598. }
  599. pmhctl->llist_notify[idx].in_use = FALSE;
  600. pmhctl->llist_notify[idx].waiting = FALSE;
  601. pmhctl->llist_notify[idx].done_cb = NULL;
  602. if (idx < MDDI_NUM_DYNAMIC_LLIST_ITEMS) {
  603. /* static LLIST items are configured only once */
  604. pmhctl->llist_notify[idx].next_idx =
  605. UNASSIGNED_INDEX;
  606. }
  607. /*
  608. * currently, all linked list packets are
  609. * register access, so we can increment the
  610. * counter for that packet type here.
  611. */
  612. pmhctl->log_parms.reg_acc_cnt++;
  613. }
  614. if (idx == pmhctl->llist_info.transmitting_end_idx)
  615. break;
  616. idx = next_idx;
  617. if (idx == UNASSIGNED_INDEX)
  618. MDDI_MSG_CRIT("MDDI linked list corruption!\n");
  619. }
  620. pmhctl->llist_info.transmitting_start_idx = UNASSIGNED_INDEX;
  621. pmhctl->llist_info.transmitting_end_idx = UNASSIGNED_INDEX;
  622. if (pmhctl->mddi_waiting_for_llist_avail) {
  623. if (!
  624. (pmhctl->
  625. llist_notify[pmhctl->llist_info.next_free_idx].
  626. in_use)) {
  627. pmhctl->mddi_waiting_for_llist_avail = FALSE;
  628. complete(&(pmhctl->mddi_llist_avail_comp));
  629. }
  630. }
  631. }
  632. /* Turn off MDDI_INT_PRI_LINK_LIST_DONE interrupt */
  633. mddi_host_reg_outm(INTEN, MDDI_INT_PRI_LINK_LIST_DONE, 0);
  634. }
  635. static void mddi_queue_forward_linked_list(void)
  636. {
  637. uint16 first_pkt_index;
  638. mddi_linked_list_type *llist_dma;
  639. mddi_host_type host_idx = mddi_curr_host;
  640. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  641. llist_dma = pmhctl->llist_dma_ptr;
  642. first_pkt_index = UNASSIGNED_INDEX;
  643. if (pmhctl->llist_info.transmitting_start_idx == UNASSIGNED_INDEX) {
  644. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  645. if (pmhctl->llist_info.reg_read_waiting) {
  646. if (pmhctl->rev_state == MDDI_REV_IDLE) {
  647. /*
  648. * we have a register read to send and
  649. * can send it now
  650. */
  651. pmhctl->rev_state = MDDI_REV_REG_READ_ISSUED;
  652. mddi_reg_read_retry = 0;
  653. first_pkt_index =
  654. pmhctl->llist_info.waiting_start_idx;
  655. pmhctl->llist_info.reg_read_waiting = FALSE;
  656. }
  657. } else
  658. #endif
  659. {
  660. /*
  661. * not register read to worry about, go ahead and write
  662. * anything that may be on the waiting list.
  663. */
  664. first_pkt_index = pmhctl->llist_info.waiting_start_idx;
  665. }
  666. }
  667. if (first_pkt_index != UNASSIGNED_INDEX) {
  668. pmhctl->llist_info.transmitting_start_idx =
  669. pmhctl->llist_info.waiting_start_idx;
  670. pmhctl->llist_info.transmitting_end_idx =
  671. pmhctl->llist_info.waiting_end_idx;
  672. pmhctl->llist_info.waiting_start_idx = UNASSIGNED_INDEX;
  673. pmhctl->llist_info.waiting_end_idx = UNASSIGNED_INDEX;
  674. /* write to the primary pointer register */
  675. MDDI_MSG_DEBUG("MDDI writing primary ptr with idx=%d\n",
  676. first_pkt_index);
  677. pmhctl->int_type.llist_ptr_write_2++;
  678. dma_coherent_pre_ops();
  679. mddi_host_reg_out(PRI_PTR, &llist_dma[first_pkt_index]);
  680. /* enable interrupt when complete */
  681. mddi_host_reg_outm(INTEN, MDDI_INT_PRI_LINK_LIST_DONE,
  682. MDDI_INT_PRI_LINK_LIST_DONE);
  683. }
  684. }
  685. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  686. static void mddi_read_rev_packet(byte *data_ptr)
  687. {
  688. uint16 i, length;
  689. mddi_host_type host_idx = mddi_curr_host;
  690. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  691. uint8 *rev_ptr_overflow =
  692. (pmhctl->rev_ptr_start + MDDI_REV_BUFFER_SIZE);
  693. /* first determine the length and handle invalid lengths */
  694. length = *pmhctl->rev_ptr_curr++;
  695. if (pmhctl->rev_ptr_curr >= rev_ptr_overflow)
  696. pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
  697. length |= ((*pmhctl->rev_ptr_curr++) << 8);
  698. if (pmhctl->rev_ptr_curr >= rev_ptr_overflow)
  699. pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
  700. if (length > (pmhctl->rev_pkt_size - 2)) {
  701. MDDI_MSG_ERR("Invalid rev pkt length %d\n", length);
  702. /* rev_pkt_size should always be <= rev_ptr_size so limit to packet size */
  703. length = pmhctl->rev_pkt_size - 2;
  704. }
  705. /* If the data pointer is NULL, just increment the pmhctl->rev_ptr_curr.
  706. * Loop around if necessary. Don't bother reading the data.
  707. */
  708. if (data_ptr == NULL) {
  709. pmhctl->rev_ptr_curr += length;
  710. if (pmhctl->rev_ptr_curr >= rev_ptr_overflow)
  711. pmhctl->rev_ptr_curr -= MDDI_REV_BUFFER_SIZE;
  712. return;
  713. }
  714. data_ptr[0] = length & 0x0ff;
  715. data_ptr[1] = length >> 8;
  716. data_ptr += 2;
  717. /* copy the data to data_ptr byte-at-a-time */
  718. for (i = 0; (i < length) && (pmhctl->rev_ptr_curr < rev_ptr_overflow);
  719. i++)
  720. *data_ptr++ = *pmhctl->rev_ptr_curr++;
  721. if (pmhctl->rev_ptr_curr >= rev_ptr_overflow)
  722. pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
  723. for (; (i < length) && (pmhctl->rev_ptr_curr < rev_ptr_overflow); i++)
  724. *data_ptr++ = *pmhctl->rev_ptr_curr++;
  725. }
  726. static void mddi_process_rev_packets(void)
  727. {
  728. uint32 rev_packet_count;
  729. word i;
  730. uint32 crc_errors;
  731. boolean mddi_reg_read_successful = FALSE;
  732. mddi_host_type host_idx = mddi_curr_host;
  733. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  734. pmhctl->log_parms.rev_enc_cnt++;
  735. if ((pmhctl->rev_state != MDDI_REV_ENCAP_ISSUED) &&
  736. (pmhctl->rev_state != MDDI_REV_STATUS_REQ_ISSUED) &&
  737. (pmhctl->rev_state != MDDI_REV_CLIENT_CAP_ISSUED)) {
  738. MDDI_MSG_ERR("Wrong state %d for reverse int\n",
  739. pmhctl->rev_state);
  740. }
  741. /* Turn off MDDI_INT_REV_AVAIL interrupt */
  742. mddi_host_reg_outm(INTEN, MDDI_INT_REV_DATA_AVAIL, 0);
  743. /* Clear rev data avail int */
  744. mddi_host_reg_out(INT, MDDI_INT_REV_DATA_AVAIL);
  745. /* Get Number of packets */
  746. rev_packet_count = mddi_host_reg_in(REV_PKT_CNT);
  747. #ifndef T_MSM7500
  748. /* Clear out rev packet counter */
  749. mddi_host_reg_out(REV_PKT_CNT, 0x0000);
  750. #endif
  751. #if defined(CONFIG_FB_MSM_MDP31) || defined(CONFIG_FB_MSM_MDP40)
  752. if ((pmhctl->rev_state == MDDI_REV_CLIENT_CAP_ISSUED) &&
  753. (rev_packet_count > 0) &&
  754. (mddi_host_core_version == 0x28 ||
  755. mddi_host_core_version == 0x30)) {
  756. uint32 int_reg;
  757. uint32 max_count = 0;
  758. mddi_host_reg_out(REV_PTR, pmhctl->mddi_rev_ptr_write_val);
  759. int_reg = mddi_host_reg_in(INT);
  760. while ((int_reg & 0x100000) == 0) {
  761. udelay(3);
  762. int_reg = mddi_host_reg_in(INT);
  763. if (++max_count > 100)
  764. break;
  765. }
  766. }
  767. #endif
  768. /* Get CRC error count */
  769. crc_errors = mddi_host_reg_in(REV_CRC_ERR);
  770. if (crc_errors != 0) {
  771. pmhctl->log_parms.rev_crc_cnt += crc_errors;
  772. pmhctl->stats.rev_crc_count += crc_errors;
  773. MDDI_MSG_ERR("!!! MDDI %d Reverse CRC Error(s) !!!\n",
  774. crc_errors);
  775. #ifndef T_MSM7500
  776. /* Clear CRC error count */
  777. mddi_host_reg_out(REV_CRC_ERR, 0x0000);
  778. #endif
  779. /* also issue an RTD to attempt recovery */
  780. pmhctl->rtd_counter = mddi_rtd_frequency;
  781. }
  782. pmhctl->rtd_value = mddi_host_reg_in(RTD_VAL);
  783. MDDI_MSG_DEBUG("MDDI rev pkt cnt=%d, ptr=0x%x, RTD:0x%x\n",
  784. rev_packet_count,
  785. pmhctl->rev_ptr_curr - pmhctl->rev_ptr_start,
  786. pmhctl->rtd_value);
  787. if (rev_packet_count >= 1) {
  788. mddi_invalidate_cache_lines((uint32 *) pmhctl->rev_ptr_start,
  789. MDDI_REV_BUFFER_SIZE);
  790. } else {
  791. MDDI_MSG_ERR("Reverse pkt sent, no data rxd\n");
  792. if (mddi_reg_read_value_ptr)
  793. *mddi_reg_read_value_ptr = -EBUSY;
  794. }
  795. /* order the reads */
  796. dma_coherent_post_ops();
  797. for (i = 0; i < rev_packet_count; i++) {
  798. mddi_rev_packet_type *rev_pkt_ptr;
  799. mddi_read_rev_packet(rev_packet_data);
  800. rev_pkt_ptr = (mddi_rev_packet_type *) rev_packet_data;
  801. if (rev_pkt_ptr->packet_length > pmhctl->rev_pkt_size) {
  802. MDDI_MSG_ERR("!!!invalid packet size: %d\n",
  803. rev_pkt_ptr->packet_length);
  804. }
  805. MDDI_MSG_DEBUG("MDDI rev pkt 0x%x size 0x%x\n",
  806. rev_pkt_ptr->packet_type,
  807. rev_pkt_ptr->packet_length);
  808. /* Do whatever you want to do with the data based on the packet type */
  809. switch (rev_pkt_ptr->packet_type) {
  810. case 66: /* Client Capability */
  811. {
  812. mddi_client_capability_type
  813. *client_capability_pkt_ptr;
  814. client_capability_pkt_ptr =
  815. (mddi_client_capability_type *)
  816. rev_packet_data;
  817. MDDI_MSG_NOTICE
  818. ("Client Capability: Week=%d, Year=%d\n",
  819. client_capability_pkt_ptr->
  820. Week_of_Manufacture,
  821. client_capability_pkt_ptr->
  822. Year_of_Manufacture);
  823. memcpy((void *)&mddi_client_capability_pkt,
  824. (void *)rev_packet_data,
  825. sizeof(mddi_client_capability_type));
  826. pmhctl->log_parms.cli_cap_cnt++;
  827. }
  828. break;
  829. case 70: /* Display Status */
  830. {
  831. mddi_client_status_type *client_status_pkt_ptr;
  832. client_status_pkt_ptr =
  833. (mddi_client_status_type *) rev_packet_data;
  834. if ((client_status_pkt_ptr->crc_error_count !=
  835. 0)
  836. || (client_status_pkt_ptr->
  837. reverse_link_request != 0)) {
  838. MDDI_MSG_ERR
  839. ("Client Status: RevReq=%d, CrcErr=%d\n",
  840. client_status_pkt_ptr->
  841. reverse_link_request,
  842. client_status_pkt_ptr->
  843. crc_error_count);
  844. } else {
  845. MDDI_MSG_DEBUG
  846. ("Client Status: RevReq=%d, CrcErr=%d\n",
  847. client_status_pkt_ptr->
  848. reverse_link_request,
  849. client_status_pkt_ptr->
  850. crc_error_count);
  851. }
  852. pmhctl->log_parms.fwd_crc_cnt +=
  853. client_status_pkt_ptr->crc_error_count;
  854. pmhctl->stats.fwd_crc_count +=
  855. client_status_pkt_ptr->crc_error_count;
  856. pmhctl->log_parms.cli_stat_cnt++;
  857. }
  858. break;
  859. case 146: /* register access packet */
  860. {
  861. mddi_register_access_packet_type
  862. * regacc_pkt_ptr;
  863. uint32 data_count;
  864. regacc_pkt_ptr =
  865. (mddi_register_access_packet_type *)
  866. rev_packet_data;
  867. /* Bits[0:13] - read data count */
  868. data_count = regacc_pkt_ptr->read_write_info
  869. & 0x3FFF;
  870. MDDI_MSG_DEBUG("\n MDDI rev read: 0x%x",
  871. regacc_pkt_ptr->read_write_info);
  872. MDDI_MSG_DEBUG("Reg Acc parse reg=0x%x,"
  873. "value=0x%x\n", regacc_pkt_ptr->
  874. register_address, regacc_pkt_ptr->
  875. register_data_list[0]);
  876. /* Copy register value to location passed in */
  877. if (mddi_reg_read_value_ptr) {
  878. #if defined(T_MSM6280) && !defined(T_MSM7200)
  879. /* only least significant 16 bits are valid with 6280 */
  880. *mddi_reg_read_value_ptr =
  881. regacc_pkt_ptr->
  882. register_data_list[0] & 0x0000ffff;
  883. mddi_reg_read_successful = TRUE;
  884. mddi_reg_read_value_ptr = NULL;
  885. #else
  886. if (data_count && data_count <=
  887. MDDI_HOST_MAX_CLIENT_REG_IN_SAME_ADDR) {
  888. memcpy(mddi_reg_read_value_ptr,
  889. (void *)&regacc_pkt_ptr->
  890. register_data_list[0],
  891. data_count * 4);
  892. mddi_reg_read_successful = TRUE;
  893. mddi_reg_read_value_ptr = NULL;
  894. }
  895. #endif
  896. }
  897. #ifdef DEBUG_MDDIHOSTI
  898. if ((mddi_gpio.polling_enabled) &&
  899. (regacc_pkt_ptr->register_address ==
  900. mddi_gpio.polling_reg)) {
  901. /*
  902. * ToDo: need to call Linux GPIO call
  903. * here...
  904. */
  905. mddi_client_lcd_gpio_poll(
  906. regacc_pkt_ptr->register_data_list[0]);
  907. }
  908. #endif
  909. pmhctl->log_parms.reg_read_cnt++;
  910. }
  911. break;
  912. case INVALID_PKT_TYPE: /* 0xFFFF */
  913. MDDI_MSG_ERR("!!!INVALID_PKT_TYPE rcvd\n");
  914. break;
  915. default: /* any other packet */
  916. {
  917. uint16 hdlr;
  918. for (hdlr = 0; hdlr < MAX_MDDI_REV_HANDLERS;
  919. hdlr++) {
  920. if (mddi_rev_pkt_handler[hdlr].
  921. handler == NULL)
  922. continue;
  923. if (mddi_rev_pkt_handler[hdlr].
  924. pkt_type ==
  925. rev_pkt_ptr->packet_type) {
  926. (*(mddi_rev_pkt_handler[hdlr].
  927. handler)) (rev_pkt_ptr);
  928. /* pmhctl->rev_state = MDDI_REV_IDLE; */
  929. break;
  930. }
  931. }
  932. if (hdlr >= MAX_MDDI_REV_HANDLERS)
  933. MDDI_MSG_ERR("MDDI unknown rev pkt\n");
  934. }
  935. break;
  936. }
  937. }
  938. if ((pmhctl->rev_ptr_curr + pmhctl->rev_pkt_size) >=
  939. (pmhctl->rev_ptr_start + MDDI_REV_BUFFER_SIZE)) {
  940. pmhctl->rev_ptr_written = FALSE;
  941. }
  942. if (pmhctl->rev_state == MDDI_REV_ENCAP_ISSUED) {
  943. pmhctl->rev_state = MDDI_REV_IDLE;
  944. if (mddi_rev_user.waiting) {
  945. mddi_rev_user.waiting = FALSE;
  946. complete(&(mddi_rev_user.done_comp));
  947. } else if (pmhctl->llist_info.reg_read_idx == UNASSIGNED_INDEX) {
  948. MDDI_MSG_ERR
  949. ("Reverse Encap state, but no reg read in progress\n");
  950. } else {
  951. if ((!mddi_reg_read_successful) &&
  952. (mddi_reg_read_retry < mddi_reg_read_retry_max) &&
  953. (mddi_enable_reg_read_retry)) {
  954. /*
  955. * There is a race condition that can happen
  956. * where the reverse encapsulation message is
  957. * sent out by the MDDI host before the register
  958. * read packet is sent. As a work-around for
  959. * that problem we issue the reverse
  960. * encapsulation one more time before giving up.
  961. */
  962. if (mddi_enable_reg_read_retry_once)
  963. mddi_reg_read_retry =
  964. mddi_reg_read_retry_max;
  965. else
  966. mddi_reg_read_retry++;
  967. pmhctl->rev_state = MDDI_REV_REG_READ_SENT;
  968. pmhctl->stats.reg_read_failure++;
  969. } else {
  970. uint16 reg_read_idx =
  971. pmhctl->llist_info.reg_read_idx;
  972. mddi_reg_read_retry = 0;
  973. if (pmhctl->llist_notify[reg_read_idx].waiting) {
  974. complete(&
  975. (pmhctl->
  976. llist_notify[reg_read_idx].
  977. done_comp));
  978. }
  979. pmhctl->llist_info.reg_read_idx =
  980. UNASSIGNED_INDEX;
  981. if (pmhctl->llist_notify[reg_read_idx].
  982. done_cb != NULL) {
  983. (*
  984. (pmhctl->llist_notify[reg_read_idx].
  985. done_cb)) ();
  986. }
  987. pmhctl->llist_notify[reg_read_idx].next_idx =
  988. UNASSIGNED_INDEX;
  989. pmhctl->llist_notify[reg_read_idx].in_use =
  990. FALSE;
  991. pmhctl->llist_notify[reg_read_idx].waiting =
  992. FALSE;
  993. pmhctl->llist_notify[reg_read_idx].done_cb =
  994. NULL;
  995. if (!mddi_reg_read_successful)
  996. pmhctl->stats.reg_read_failure++;
  997. }
  998. }
  999. } else if (pmhctl->rev_state == MDDI_REV_CLIENT_CAP_ISSUED) {
  1000. #if defined(CONFIG_FB_MSM_MDP31) || defined(CONFIG_FB_MSM_MDP40)
  1001. if (mddi_host_core_version == 0x28 ||
  1002. mddi_host_core_version == 0x30) {
  1003. mddi_host_reg_out(FIFO_ALLOC, 0x00);
  1004. pmhctl->rev_ptr_written = TRUE;
  1005. mddi_host_reg_out(REV_PTR,
  1006. pmhctl->mddi_rev_ptr_write_val);
  1007. pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
  1008. mddi_host_reg_out(CMD, 0xC00);
  1009. }
  1010. #endif
  1011. if (mddi_rev_user.waiting) {
  1012. mddi_rev_user.waiting = FALSE;
  1013. complete(&(mddi_rev_user.done_comp));
  1014. }
  1015. pmhctl->rev_state = MDDI_REV_IDLE;
  1016. } else {
  1017. pmhctl->rev_state = MDDI_REV_IDLE;
  1018. }
  1019. /* pmhctl->rev_state = MDDI_REV_IDLE; */
  1020. /* Re-enable interrupt */
  1021. mddi_host_reg_outm(INTEN, MDDI_INT_REV_DATA_AVAIL,
  1022. MDDI_INT_REV_DATA_AVAIL);
  1023. }
  1024. static void mddi_issue_reverse_encapsulation(void)
  1025. {
  1026. mddi_host_type host_idx = mddi_curr_host;
  1027. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  1028. /* Only issue a reverse encapsulation packet if:
  1029. * 1) another reverse is not in progress (MDDI_REV_IDLE).
  1030. * 2) a register read has been sent (MDDI_REV_REG_READ_SENT).
  1031. * 3) forward is not in progress, because of a hw bug in client that
  1032. * causes forward crc errors on packet immediately after rev encap.
  1033. */
  1034. if (((pmhctl->rev_state == MDDI_REV_IDLE) ||
  1035. (pmhctl->rev_state == MDDI_REV_REG_READ_SENT)) &&
  1036. (pmhctl->llist_info.transmitting_start_idx == UNASSIGNED_INDEX) &&
  1037. (!mdp_in_processing)) {
  1038. uint32 mddi_command = MDDI_CMD_SEND_REV_ENCAP;
  1039. if ((pmhctl->rev_state == MDDI_REV_REG_READ_SENT) ||
  1040. (mddi_rev_encap_user_request == TRUE)) {
  1041. mddi_host_enable_io_clock();
  1042. if (pmhctl->link_state == MDDI_LINK_HIBERNATING) {
  1043. /* need to wake up link before issuing rev encap command */
  1044. MDDI_MSG_DEBUG("wake up link!\n");
  1045. pmhctl->link_state = MDDI_LINK_ACTIVATING;
  1046. mddi_host_reg_out(CMD, MDDI_CMD_LINK_ACTIVE);
  1047. } else {
  1048. if (pmhctl->rtd_counter >= mddi_rtd_frequency) {
  1049. MDDI_MSG_DEBUG
  1050. ("mddi sending RTD command!\n");
  1051. mddi_host_reg_out(CMD,
  1052. MDDI_CMD_SEND_RTD);
  1053. pmhctl->rtd_counter = 0;
  1054. pmhctl->log_parms.rtd_cnt++;
  1055. }
  1056. if (pmhctl->rev_state != MDDI_REV_REG_READ_SENT) {
  1057. /* this is generic reverse request by user, so
  1058. * reset the waiting flag. */
  1059. mddi_rev_encap_user_request = FALSE;
  1060. }
  1061. /* link is active so send reverse encap to get register read results */
  1062. pmhctl->rev_state = MDDI_REV_ENCAP_ISSUED;
  1063. mddi_command = MDDI_CMD_SEND_REV_ENCAP;
  1064. MDDI_MSG_DEBUG("sending rev encap!\n");
  1065. }
  1066. } else
  1067. if ((pmhctl->client_status_cnt >=
  1068. mddi_client_status_frequency)
  1069. || mddi_client_capability_request) {
  1070. mddi_host_enable_io_clock();
  1071. if (pmhctl->link_state == MDDI_LINK_HIBERNATING) {
  1072. /* only wake up the link if it client status is overdue */
  1073. if ((pmhctl->client_status_cnt >=
  1074. (mddi_client_status_frequency * 2))
  1075. || mddi_client_capability_request) {
  1076. /* need to wake up link before issuing rev encap command */
  1077. MDDI_MSG_DEBUG("wake up link!\n");
  1078. pmhctl->link_state =
  1079. MDDI_LINK_ACTIVATING;
  1080. mddi_host_reg_out(CMD,
  1081. MDDI_CMD_LINK_ACTIVE);
  1082. }
  1083. } else {
  1084. if (pmhctl->rtd_counter >= mddi_rtd_frequency) {
  1085. MDDI_MSG_DEBUG
  1086. ("mddi sending RTD command!\n");
  1087. mddi_host_reg_out(CMD,
  1088. MDDI_CMD_SEND_RTD);
  1089. pmhctl->rtd_counter = 0;
  1090. pmhctl->log_parms.rtd_cnt++;
  1091. }
  1092. /* periodically get client status */
  1093. MDDI_MSG_DEBUG
  1094. ("mddi sending rev enc! (get status)\n");
  1095. if (mddi_client_capability_request) {
  1096. pmhctl->rev_state =
  1097. MDDI_REV_CLIENT_CAP_ISSUED;
  1098. mddi_command = MDDI_CMD_GET_CLIENT_CAP;
  1099. mddi_client_capability_request = FALSE;
  1100. } else {
  1101. pmhctl->rev_state =
  1102. MDDI_REV_STATUS_REQ_ISSUED;
  1103. pmhctl->client_status_cnt = 0;
  1104. mddi_command =
  1105. MDDI_CMD_GET_CLIENT_STATUS;
  1106. }
  1107. }
  1108. }
  1109. if ((pmhctl->rev_state == MDDI_REV_ENCAP_ISSUED) ||
  1110. (pmhctl->rev_state == MDDI_REV_STATUS_REQ_ISSUED) ||
  1111. (pmhctl->rev_state == MDDI_REV_CLIENT_CAP_ISSUED)) {
  1112. pmhctl->int_type.rev_encap_count++;
  1113. #if defined(T_MSM6280) && !defined(T_MSM7200)
  1114. mddi_rev_pointer_written = TRUE;
  1115. mddi_host_reg_out(REV_PTR, mddi_rev_ptr_write_val);
  1116. mddi_rev_ptr_curr = mddi_rev_ptr_start;
  1117. /* force new rev ptr command */
  1118. mddi_host_reg_out(CMD, 0xC00);
  1119. #else
  1120. if (!pmhctl->rev_ptr_written) {
  1121. MDDI_MSG_DEBUG("writing reverse pointer!\n");
  1122. pmhctl->rev_ptr_written = TRUE;
  1123. #if defined(CONFIG_FB_MSM_MDP31) || defined(CONFIG_FB_MSM_MDP40)
  1124. if ((pmhctl->rev_state ==
  1125. MDDI_REV_CLIENT_CAP_ISSUED) &&
  1126. (mddi_host_core_version == 0x28 ||
  1127. mddi_host_core_version == 0x30)) {
  1128. pmhctl->rev_ptr_written = FALSE;
  1129. mddi_host_reg_out(FIFO_ALLOC, 0x02);
  1130. } else
  1131. mddi_host_reg_out(REV_PTR,
  1132. pmhctl->
  1133. mddi_rev_ptr_write_val);
  1134. #else
  1135. mddi_host_reg_out(REV_PTR,
  1136. pmhctl->
  1137. mddi_rev_ptr_write_val);
  1138. #endif
  1139. }
  1140. #endif
  1141. if (mddi_debug_clear_rev_data) {
  1142. uint16 i;
  1143. for (i = 0; i < MDDI_MAX_REV_DATA_SIZE / 4; i++)
  1144. pmhctl->rev_data_buf[i] = 0xdddddddd;
  1145. /* clean cache */
  1146. mddi_flush_cache_lines(pmhctl->rev_data_buf,
  1147. MDDI_MAX_REV_DATA_SIZE);
  1148. }
  1149. /* send reverse encapsulation to get needed data */
  1150. mddi_host_reg_out(CMD, mddi_command);
  1151. }
  1152. }
  1153. }
  1154. static void mddi_process_client_initiated_wakeup(void)
  1155. {
  1156. mddi_host_type host_idx = mddi_curr_host;
  1157. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  1158. /* Disable MDDI_INT Interrupt, we detect client initiated wakeup one
  1159. * time for each entry into hibernation */
  1160. mddi_host_reg_outm(INTEN, MDDI_INT_MDDI_IN, 0);
  1161. if (host_idx == MDDI_HOST_PRIM) {
  1162. if (mddi_vsync_detect_enabled) {
  1163. mddi_host_enable_io_clock();
  1164. #ifndef MDDI_HOST_DISP_LISTEN
  1165. /* issue command to bring up link */
  1166. /* need to do this to clear the vsync condition */
  1167. if (pmhctl->link_state == MDDI_LINK_HIBERNATING) {
  1168. pmhctl->link_state = MDDI_LINK_ACTIVATING;
  1169. mddi_host_reg_out(CMD, MDDI_CMD_LINK_ACTIVE);
  1170. }
  1171. #endif
  1172. /*
  1173. * Indicate to client specific code that vsync was
  1174. * enabled, and we did not detect a client initiated
  1175. * wakeup. The client specific handler can clear the
  1176. * condition if necessary to prevent subsequent
  1177. * client initiated wakeups.
  1178. */
  1179. mddi_client_lcd_vsync_detected(TRUE);
  1180. pmhctl->log_parms.vsync_response_cnt++;
  1181. MDDI_MSG_NOTICE("MDDI_INT_IN condition\n");
  1182. }
  1183. }
  1184. if (mddi_gpio.polling_enabled) {
  1185. mddi_host_enable_io_clock();
  1186. /* check interrupt status now */
  1187. (void)mddi_queue_register_read_int(mddi_gpio.polling_reg,
  1188. &mddi_gpio.polling_val);
  1189. }
  1190. }
  1191. #endif /* FEATURE_MDDI_DISABLE_REVERSE */
  1192. static void mddi_host_isr(void)
  1193. {
  1194. uint32 int_reg, int_en;
  1195. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  1196. uint32 status_reg;
  1197. #endif
  1198. mddi_host_type host_idx = mddi_curr_host;
  1199. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  1200. if (!MDDI_HOST_IS_HCLK_ON) {
  1201. MDDI_HOST_ENABLE_HCLK;
  1202. }
  1203. int_reg = mddi_host_reg_in(INT);
  1204. int_en = mddi_host_reg_in(INTEN);
  1205. pmhctl->saved_int_reg = int_reg;
  1206. pmhctl->saved_int_en = int_en;
  1207. int_reg = int_reg & int_en;
  1208. pmhctl->int_type.count++;
  1209. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  1210. status_reg = mddi_host_reg_in(STAT);
  1211. if ((int_reg & MDDI_INT_MDDI_IN) ||
  1212. ((int_en & MDDI_INT_MDDI_IN) &&
  1213. ((int_reg == 0) || (status_reg & MDDI_STAT_CLIENT_WAKEUP_REQ)))) {
  1214. /*
  1215. * The MDDI_IN condition will clear itself, and so it is
  1216. * possible that MDDI_IN was the reason for the isr firing,
  1217. * even though the interrupt register does not have the
  1218. * MDDI_IN bit set. To check if this was the case we need to
  1219. * look at the status register bit that signifies a client
  1220. * initiated wakeup. If the status register bit is set, as well
  1221. * as the MDDI_IN interrupt enabled, then we treat this as a
  1222. * client initiated wakeup.
  1223. */
  1224. if (int_reg & MDDI_INT_MDDI_IN)
  1225. pmhctl->int_type.in_count++;
  1226. mddi_process_client_initiated_wakeup();
  1227. }
  1228. #endif
  1229. if (int_reg & MDDI_INT_LINK_STATE_CHANGES) {
  1230. pmhctl->int_type.state_change_count++;
  1231. mddi_report_state_change(int_reg);
  1232. }
  1233. if (int_reg & MDDI_INT_PRI_LINK_LIST_DONE) {
  1234. pmhctl->int_type.ll_done_count++;
  1235. mddi_process_link_list_done();
  1236. }
  1237. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  1238. if (int_reg & MDDI_INT_REV_DATA_AVAIL) {
  1239. pmhctl->int_type.rev_avail_count++;
  1240. mddi_process_rev_packets();
  1241. }
  1242. #endif
  1243. if (int_reg & MDDI_INT_ERROR_CONDITIONS) {
  1244. pmhctl->int_type.error_count++;
  1245. mddi_report_errors(int_reg);
  1246. mddi_host_reg_out(INT, int_reg & MDDI_INT_ERROR_CONDITIONS);
  1247. }
  1248. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  1249. mddi_issue_reverse_encapsulation();
  1250. if ((pmhctl->rev_state != MDDI_REV_ENCAP_ISSUED) &&
  1251. (pmhctl->rev_state != MDDI_REV_STATUS_REQ_ISSUED))
  1252. #endif
  1253. /* don't want simultaneous reverse and forward with Eagle */
  1254. mddi_queue_forward_linked_list();
  1255. if (int_reg & MDDI_INT_NO_CMD_PKTS_PEND) {
  1256. /* this interrupt is used to kick the isr when hibernation is disabled */
  1257. mddi_host_reg_outm(INTEN, MDDI_INT_NO_CMD_PKTS_PEND, 0);
  1258. }
  1259. if ((!mddi_host_mdp_active_flag) &&
  1260. (!mddi_vsync_detect_enabled) &&
  1261. (pmhctl->llist_info.transmitting_start_idx == UNASSIGNED_INDEX) &&
  1262. (pmhctl->llist_info.waiting_start_idx == UNASSIGNED_INDEX) &&
  1263. (pmhctl->rev_state == MDDI_REV_IDLE)) {
  1264. if (pmhctl->link_state == MDDI_LINK_HIBERNATING) {
  1265. mddi_host_disable_io_clock();
  1266. mddi_host_disable_hclk();
  1267. }
  1268. #ifdef FEATURE_MDDI_HOST_ENABLE_EARLY_HIBERNATION
  1269. else if ((pmhctl->link_state == MDDI_LINK_ACTIVE) &&
  1270. (!pmhctl->disable_hibernation)) {
  1271. mddi_host_reg_out(CMD, MDDI_CMD_POWERDOWN);
  1272. }
  1273. #endif
  1274. }
  1275. }
  1276. static void mddi_host_isr_primary(void)
  1277. {
  1278. mddi_curr_host = MDDI_HOST_PRIM;
  1279. mddi_host_isr();
  1280. }
  1281. irqreturn_t mddi_pmdh_isr_proxy(int irq, void *ptr)
  1282. {
  1283. mddi_host_isr_primary();
  1284. return IRQ_HANDLED;
  1285. }
  1286. static void mddi_host_isr_external(void)
  1287. {
  1288. mddi_curr_host = MDDI_HOST_EXT;
  1289. mddi_host_isr();
  1290. mddi_curr_host = MDDI_HOST_PRIM;
  1291. }
  1292. irqreturn_t mddi_emdh_isr_proxy(int irq, void *ptr)
  1293. {
  1294. mddi_host_isr_external();
  1295. return IRQ_HANDLED;
  1296. }
  1297. static void mddi_host_initialize_registers(mddi_host_type host_idx)
  1298. {
  1299. uint32 pad_reg_val;
  1300. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  1301. if (pmhctl->driver_state == MDDI_DRIVER_ENABLED)
  1302. return;
  1303. /* turn on HCLK to MDDI host core */
  1304. mddi_host_enable_hclk();
  1305. /* MDDI Reset command */
  1306. mddi_host_reg_out(CMD, MDDI_CMD_RESET);
  1307. /* Version register (= 0x01) */
  1308. mddi_host_reg_out(VERSION, 0x0001);
  1309. /* Bytes per subframe register */
  1310. mddi_host_reg_out(BPS, MDDI_HOST_BYTES_PER_SUBFRAME);
  1311. /* Subframes per media frames register (= 0x03) */
  1312. mddi_host_reg_out(SPM, 0x0003);
  1313. /* Turn Around 1 register (= 0x05) */
  1314. mddi_host_reg_out(TA1_LEN, 0x0005);
  1315. /* Turn Around 2 register (= 0x0C) */
  1316. mddi_host_reg_out(TA2_LEN, MDDI_HOST_TA2_LEN);
  1317. /* Drive hi register (= 0x96) */
  1318. mddi_host_reg_out(DRIVE_HI, 0x0096);
  1319. /* Drive lo register (= 0x32) */
  1320. mddi_host_reg_out(DRIVE_LO, 0x0032);
  1321. /* Display wakeup count register (= 0x3c) */
  1322. mddi_host_reg_out(DISP_WAKE, 0x003c);
  1323. /* Reverse Rate Divisor register (= 0x2) */
  1324. mddi_host_reg_out(REV_RATE_DIV, MDDI_HOST_REV_RATE_DIV);
  1325. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  1326. /* Reverse Pointer Size */
  1327. mddi_host_reg_out(REV_SIZE, MDDI_REV_BUFFER_SIZE);
  1328. /* Rev Encap Size */
  1329. mddi_host_reg_out(REV_ENCAP_SZ, pmhctl->rev_pkt_size);
  1330. #endif
  1331. /* Periodic Rev Encap */
  1332. /* don't send periodically */
  1333. mddi_host_reg_out(CMD, MDDI_CMD_PERIODIC_REV_ENCAP);
  1334. pad_reg_val = mddi_host_reg_in(PAD_CTL);
  1335. if (pad_reg_val == 0) {
  1336. /* If we are turning on band gap, need to wait 5us before turning
  1337. * on the rest of the PAD */
  1338. mddi_host_reg_out(PAD_CTL, 0x08000);
  1339. udelay(5);
  1340. }
  1341. #ifdef T_MSM7200
  1342. /* Recommendation from PAD hw team */
  1343. mddi_host_reg_out(PAD_CTL, 0xa850a);
  1344. #else
  1345. /* Recommendation from PAD hw team */
  1346. mddi_host_reg_out(PAD_CTL, 0xa850f);
  1347. #endif
  1348. pad_reg_val = 0x00220020;
  1349. #if defined(CONFIG_FB_MSM_MDP31) || defined(CONFIG_FB_MSM_MDP40)
  1350. mddi_host_reg_out(PAD_IO_CTL, 0x00320000);
  1351. mddi_host_reg_out(PAD_CAL, pad_reg_val);
  1352. #endif
  1353. mddi_host_core_version = mddi_host_reg_inm(CORE_VER, 0xffff);
  1354. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  1355. if (mddi_host_core_version >= 8)
  1356. mddi_rev_ptr_workaround = FALSE;
  1357. pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
  1358. #endif
  1359. if ((mddi_host_core_version > 8) && (mddi_host_core_version < 0x19))
  1360. mddi_host_reg_out(TEST, 0x2);
  1361. /* Need an even number for counts */
  1362. mddi_host_reg_out(DRIVER_START_CNT, 0x60006);
  1363. #ifndef T_MSM7500
  1364. /* Setup defaults for MDP related register */
  1365. mddi_host_reg_out(MDP_VID_FMT_DES, 0x5666);
  1366. mddi_host_reg_out(MDP_VID_PIX_ATTR, 0x00C3);
  1367. mddi_host_reg_out(MDP_VID_CLIENTID, 0);
  1368. #endif
  1369. /* automatically hibernate after 1 empty subframe */
  1370. if (pmhctl->disable_hibernation)
  1371. mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE);
  1372. else
  1373. mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE | 1);
  1374. /* Bring up link if display (client) requests it */
  1375. #ifdef MDDI_HOST_DISP_LISTEN
  1376. mddi_host_reg_out(CMD, MDDI_CMD_DISP_LISTEN);
  1377. #else
  1378. mddi_host_reg_out(CMD, MDDI_CMD_DISP_IGNORE);
  1379. #endif
  1380. }
  1381. void mddi_host_configure_interrupts(mddi_host_type host_idx, boolean enable)
  1382. {
  1383. unsigned long flags;
  1384. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  1385. spin_lock_irqsave(&mddi_host_spin_lock, flags);
  1386. /* turn on HCLK to MDDI host core if it has been disabled */
  1387. mddi_host_enable_hclk();
  1388. /* Clear MDDI Interrupt enable reg */
  1389. mddi_host_reg_out(INTEN, 0);
  1390. spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
  1391. if (enable) {
  1392. pmhctl->driver_state = MDDI_DRIVER_ENABLED;
  1393. if (host_idx == MDDI_HOST_PRIM) {
  1394. if (request_irq
  1395. (INT_MDDI_PRI, mddi_pmdh_isr_proxy, IRQF_DISABLED,
  1396. "PMDH", 0) != 0)
  1397. printk(KERN_ERR
  1398. "a mddi: unable to request_irq\n");
  1399. else {
  1400. int_mddi_pri_flag = TRUE;
  1401. irq_enabled = 1;
  1402. }
  1403. } else {
  1404. if (request_irq
  1405. (INT_MDDI_EXT, mddi_emdh_isr_proxy, IRQF_DISABLED,
  1406. "EMDH", 0) != 0)
  1407. printk(KERN_ERR
  1408. "b mddi: unable to request_irq\n");
  1409. else
  1410. int_mddi_ext_flag = TRUE;
  1411. }
  1412. /* Set MDDI Interrupt enable reg -- Enable Reverse data avail */
  1413. #ifdef FEATURE_MDDI_DISABLE_REVERSE
  1414. mddi_host_reg_out(INTEN,
  1415. MDDI_INT_ERROR_CONDITIONS |
  1416. MDDI_INT_LINK_STATE_CHANGES);
  1417. #else
  1418. /* Reverse Pointer register */
  1419. pmhctl->rev_ptr_written = FALSE;
  1420. mddi_host_reg_out(INTEN,
  1421. MDDI_INT_REV_DATA_AVAIL |
  1422. MDDI_INT_ERROR_CONDITIONS |
  1423. MDDI_INT_LINK_STATE_CHANGES);
  1424. pmhctl->rtd_counter = mddi_rtd_frequency;
  1425. pmhctl->client_status_cnt = 0;
  1426. #endif
  1427. } else {
  1428. if (pmhctl->driver_state == MDDI_DRIVER_ENABLED)
  1429. pmhctl->driver_state = MDDI_DRIVER_DISABLED;
  1430. }
  1431. }
  1432. /*
  1433. * mddi_host_client_cnt_reset:
  1434. * reset client_status_cnt to 0 to make sure host does not
  1435. * send RTD cmd to client right after resume before mddi
  1436. * client be powered up. this fix "MDDI RTD Failure" problem
  1437. */
  1438. void mddi_host_client_cnt_reset(void)
  1439. {
  1440. unsigned long flags;
  1441. mddi_host_cntl_type *pmhctl;
  1442. pmhctl = &(mhctl[MDDI_HOST_PRIM]);
  1443. spin_lock_irqsave(&mddi_host_spin_lock, flags);
  1444. pmhctl->client_status_cnt = 0;
  1445. spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
  1446. }
  1447. static void mddi_host_powerup(mddi_host_type host_idx)
  1448. {
  1449. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  1450. if (pmhctl->link_state != MDDI_LINK_DISABLED)
  1451. return;
  1452. /* enable IO_CLK and hclk to MDDI host core */
  1453. mddi_host_enable_io_clock();
  1454. mddi_host_initialize_registers(host_idx);
  1455. mddi_host_configure_interrupts(host_idx, TRUE);
  1456. pmhctl->link_state = MDDI_LINK_ACTIVATING;
  1457. /* Link activate command */
  1458. mddi_host_reg_out(CMD, MDDI_CMD_LINK_ACTIVE);
  1459. #ifdef CLKRGM_MDDI_IO_CLOCK_IN_MHZ
  1460. MDDI_MSG_NOTICE("MDDI Host: Activating Link %d Mbps\n",
  1461. CLKRGM_MDDI_IO_CLOCK_IN_MHZ * 2);
  1462. #else
  1463. MDDI_MSG_NOTICE("MDDI Host: Activating Link\n");
  1464. #endif
  1465. /* Initialize the timer */
  1466. if (host_idx == MDDI_HOST_PRIM)
  1467. mddi_host_timer_service(0);
  1468. }
  1469. void mddi_send_fw_link_skew_cal(mddi_host_type host_idx)
  1470. {
  1471. mddi_host_reg_out(CMD, MDDI_CMD_FW_LINK_SKEW_CAL);
  1472. MDDI_MSG_DEBUG("%s: Skew Calibration done!!\n", __func__);
  1473. }
  1474. void mddi_host_init(mddi_host_type host_idx)
  1475. /* Write out the MDDI configuration registers */
  1476. {
  1477. static boolean initialized = FALSE;
  1478. mddi_host_cntl_type *pmhctl;
  1479. if (host_idx >= MDDI_NUM_HOST_CORES) {
  1480. MDDI_MSG_ERR("Invalid host core index\n");
  1481. return;
  1482. }
  1483. if (!initialized) {
  1484. uint16 idx;
  1485. mddi_host_type host;
  1486. for (host = MDDI_HOST_PRIM; host < MDDI_NUM_HOST_CORES; host++) {
  1487. pmhctl = &(mhctl[host]);
  1488. initialized = TRUE;
  1489. pmhctl->llist_ptr =
  1490. dma_alloc_coherent(NULL, MDDI_LLIST_POOL_SIZE,
  1491. &(pmhctl->llist_dma_addr),
  1492. GFP_KERNEL);
  1493. pmhctl->llist_dma_ptr =
  1494. (mddi_linked_list_type *) (void *)pmhctl->
  1495. llist_dma_addr;
  1496. #ifdef FEATURE_MDDI_DISABLE_REVERSE
  1497. pmhctl->rev_data_buf = NULL;
  1498. if (pmhctl->llist_ptr == NULL)
  1499. #else
  1500. mddi_rev_user.waiting = FALSE;
  1501. init_completion(&(mddi_rev_user.done_comp));
  1502. pmhctl->rev_data_buf =
  1503. dma_alloc_coherent(NULL, MDDI_MAX_REV_DATA_SIZE,
  1504. &(pmhctl->rev_data_dma_addr),
  1505. GFP_KERNEL);
  1506. if ((pmhctl->llist_ptr == NULL)
  1507. || (pmhctl->rev_data_buf == NULL))
  1508. #endif
  1509. {
  1510. MDDI_MSG_CRIT
  1511. ("unable to alloc non-cached memory\n");
  1512. }
  1513. llist_extern[host] = pmhctl->llist_ptr;
  1514. llist_dma_extern[host] = pmhctl->llist_dma_ptr;
  1515. llist_extern_notify[host] = pmhctl->llist_notify;
  1516. for (idx = 0; idx < UNASSIGNED_INDEX; idx++) {
  1517. init_completion(&
  1518. (pmhctl->llist_notify[idx].
  1519. done_comp));
  1520. }
  1521. init_completion(&(pmhctl->mddi_llist_avail_comp));
  1522. spin_lock_init(&mddi_host_spin_lock);
  1523. pmhctl->mddi_waiting_for_llist_avail = FALSE;
  1524. pmhctl->mddi_rev_ptr_write_val =
  1525. (uint32) (void *)(pmhctl->rev_data_dma_addr);
  1526. pmhctl->rev_ptr_start = (void *)pmhctl->rev_data_buf;
  1527. pmhctl->rev_pkt_size = MDDI_DEFAULT_REV_PKT_SIZE;
  1528. pmhctl->rev_state = MDDI_REV_IDLE;
  1529. #ifdef IMAGE_MODEM_PROC
  1530. /* assume hibernation state is last state from APPS proc, so that
  1531. * we don't reinitialize the host core */
  1532. pmhctl->link_state = MDDI_LINK_HIBERNATING;
  1533. #else
  1534. pmhctl->link_state = MDDI_LINK_DISABLED;
  1535. #endif
  1536. pmhctl->driver_state = MDDI_DRIVER_DISABLED;
  1537. pmhctl->disable_hibernation = FALSE;
  1538. /* initialize llist variables */
  1539. pmhctl->llist_info.transmitting_start_idx =
  1540. UNASSIGNED_INDEX;
  1541. pmhctl->llist_info.transmitting_end_idx =
  1542. UNASSIGNED_INDEX;
  1543. pmhctl->llist_info.waiting_start_idx = UNASSIGNED_INDEX;
  1544. pmhctl->llist_info.waiting_end_idx = UNASSIGNED_INDEX;
  1545. pmhctl->llist_info.reg_read_idx = UNASSIGNED_INDEX;
  1546. pmhctl->llist_info.next_free_idx =
  1547. MDDI_FIRST_DYNAMIC_LLIST_IDX;
  1548. pmhctl->llist_info.reg_read_waiting = FALSE;
  1549. mddi_vsync_detect_enabled = FALSE;
  1550. mddi_gpio.polling_enabled = FALSE;
  1551. pmhctl->int_type.count = 0;
  1552. pmhctl->int_type.in_count = 0;
  1553. pmhctl->int_type.disp_req_count = 0;
  1554. pmhctl->int_type.state_change_count = 0;
  1555. pmhctl->int_type.ll_done_count = 0;
  1556. pmhctl->int_type.rev_avail_count = 0;
  1557. pmhctl->int_type.error_count = 0;
  1558. pmhctl->int_type.rev_encap_count = 0;
  1559. pmhctl->int_type.llist_ptr_write_1 = 0;
  1560. pmhctl->int_type.llist_ptr_write_2 = 0;
  1561. pmhctl->stats.fwd_crc_count = 0;
  1562. pmhctl->stats.rev_crc_count = 0;
  1563. pmhctl->stats.pri_underflow = 0;
  1564. pmhctl->stats.sec_underflow = 0;
  1565. pmhctl->stats.rev_overflow = 0;
  1566. pmhctl->stats.pri_overwrite = 0;
  1567. pmhctl->stats.sec_overwrite = 0;
  1568. pmhctl->stats.rev_overwrite = 0;
  1569. pmhctl->stats.dma_failure = 0;
  1570. pmhctl->stats.rtd_failure = 0;
  1571. pmhctl->stats.reg_read_failure = 0;
  1572. #ifdef FEATURE_MDDI_UNDERRUN_RECOVERY
  1573. pmhctl->stats.pri_underrun_detected = 0;
  1574. #endif
  1575. pmhctl->log_parms.rtd_cnt = 0;
  1576. pmhctl->log_parms.rev_enc_cnt = 0;
  1577. pmhctl->log_parms.vid_cnt = 0;
  1578. pmhctl->log_parms.reg_acc_cnt = 0;
  1579. pmhctl->log_parms.cli_stat_cnt = 0;
  1580. pmhctl->log_parms.cli_cap_cnt = 0;
  1581. pmhctl->log_parms.reg_read_cnt = 0;
  1582. pmhctl->log_parms.link_active_cnt = 0;
  1583. pmhctl->log_parms.link_hibernate_cnt = 0;
  1584. pmhctl->log_parms.fwd_crc_cnt = 0;
  1585. pmhctl->log_parms.rev_crc_cnt = 0;
  1586. pmhctl->log_parms.vsync_response_cnt = 0;
  1587. prev_parms[host_idx] = pmhctl->log_parms;
  1588. mddi_client_capability_pkt.packet_length = 0;
  1589. }
  1590. #ifndef T_MSM7500
  1591. /* tell clock driver we are user of this PLL */
  1592. MDDI_HOST_ENABLE_IO_CLOCK;
  1593. #endif
  1594. }
  1595. mddi_host_powerup(host_idx);
  1596. pmhctl = &(mhctl[host_idx]);
  1597. }
  1598. #ifdef CONFIG_FB_MSM_MDDI_AUTO_DETECT
  1599. static uint32 mddi_client_id;
  1600. uint32 mddi_get_client_id(void)
  1601. {
  1602. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  1603. mddi_host_type host_idx = MDDI_HOST_PRIM;
  1604. static boolean client_detection_try = FALSE;
  1605. mddi_host_cntl_type *pmhctl;
  1606. unsigned long flags;
  1607. uint16 saved_rev_pkt_size;
  1608. int ret;
  1609. if (!client_detection_try) {
  1610. /* Toshiba display requires larger drive_lo value */
  1611. mddi_host_reg_out(DRIVE_LO, 0x0050);
  1612. pmhctl = &(mhctl[MDDI_HOST_PRIM]);
  1613. saved_rev_pkt_size = pmhctl->rev_pkt_size;
  1614. /* Increase Rev Encap Size */
  1615. pmhctl->rev_pkt_size = MDDI_CLIENT_CAPABILITY_REV_PKT_SIZE;
  1616. mddi_host_reg_out(REV_ENCAP_SZ, pmhctl->rev_pkt_size);
  1617. /* disable hibernation temporarily */
  1618. if (!pmhctl->disable_hibernation)
  1619. mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE);
  1620. mddi_rev_user.waiting = TRUE;
  1621. INIT_COMPLETION(mddi_rev_user.done_comp);
  1622. spin_lock_irqsave(&mddi_host_spin_lock, flags);
  1623. /* turn on clock(s), if they have been disabled */
  1624. mddi_host_enable_hclk();
  1625. mddi_host_enable_io_clock();
  1626. mddi_client_capability_request = TRUE;
  1627. if (pmhctl->rev_state == MDDI_REV_IDLE) {
  1628. /* attempt to send the reverse encapsulation now */
  1629. mddi_issue_reverse_encapsulation();
  1630. }
  1631. spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
  1632. wait_for_completion_killable(&(mddi_rev_user.done_comp));
  1633. /* Set Rev Encap Size back to its original value */
  1634. pmhctl->rev_pkt_size = saved_rev_pkt_size;
  1635. mddi_host_reg_out(REV_ENCAP_SZ, pmhctl->rev_pkt_size);
  1636. /* reenable auto-hibernate */
  1637. if (!pmhctl->disable_hibernation)
  1638. mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE | 1);
  1639. mddi_host_reg_out(DRIVE_LO, 0x0032);
  1640. client_detection_try = TRUE;
  1641. mddi_client_id = (mddi_client_capability_pkt.Mfr_Name<<16) |
  1642. mddi_client_capability_pkt.Product_Code;
  1643. if (!mddi_client_id)
  1644. mddi_disable(1);
  1645. ret = mddi_client_power(mddi_client_id);
  1646. if (ret < 0)
  1647. MDDI_MSG_ERR("mddi_client_power return %d", ret);
  1648. }
  1649. #endif
  1650. return mddi_client_id;
  1651. }
  1652. #endif
  1653. void mddi_host_powerdown(mddi_host_type host_idx)
  1654. {
  1655. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  1656. if (host_idx >= MDDI_NUM_HOST_CORES) {
  1657. MDDI_MSG_ERR("Invalid host core index\n");
  1658. return;
  1659. }
  1660. if (pmhctl->driver_state == MDDI_DRIVER_RESET) {
  1661. return;
  1662. }
  1663. if (host_idx == MDDI_HOST_PRIM) {
  1664. /* disable timer */
  1665. del_timer(&mddi_host_timer);
  1666. }
  1667. mddi_host_configure_interrupts(host_idx, FALSE);
  1668. /* turn on HCLK to MDDI host core if it has been disabled */
  1669. mddi_host_enable_hclk();
  1670. /* MDDI Reset command */
  1671. mddi_host_reg_out(CMD, MDDI_CMD_RESET);
  1672. /* Pad Control Register */
  1673. mddi_host_reg_out(PAD_CTL, 0x0);
  1674. /* disable IO_CLK and hclk to MDDI host core */
  1675. mddi_host_disable_io_clock();
  1676. mddi_host_disable_hclk();
  1677. pmhctl->link_state = MDDI_LINK_DISABLED;
  1678. pmhctl->driver_state = MDDI_DRIVER_RESET;
  1679. MDDI_MSG_NOTICE("MDDI Host: Disabling Link\n");
  1680. }
  1681. uint16 mddi_get_next_free_llist_item(mddi_host_type host_idx, boolean wait)
  1682. {
  1683. unsigned long flags;
  1684. uint16 ret_idx;
  1685. boolean forced_wait = FALSE;
  1686. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  1687. ret_idx = pmhctl->llist_info.next_free_idx;
  1688. pmhctl->llist_info.next_free_idx++;
  1689. if (pmhctl->llist_info.next_free_idx >= MDDI_NUM_DYNAMIC_LLIST_ITEMS)
  1690. pmhctl->llist_info.next_free_idx = MDDI_FIRST_DYNAMIC_LLIST_IDX;
  1691. spin_lock_irqsave(&mddi_host_spin_lock, flags);
  1692. if (pmhctl->llist_notify[ret_idx].in_use) {
  1693. if (!wait) {
  1694. pmhctl->llist_info.next_free_idx = ret_idx;
  1695. ret_idx = UNASSIGNED_INDEX;
  1696. } else {
  1697. forced_wait = TRUE;
  1698. INIT_COMPLETION(pmhctl->mddi_llist_avail_comp);
  1699. }
  1700. }
  1701. spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
  1702. if (forced_wait) {
  1703. wait_for_completion_killable(&
  1704. (pmhctl->
  1705. mddi_llist_avail_comp));
  1706. MDDI_MSG_ERR("task waiting on mddi llist item\n");
  1707. }
  1708. if (ret_idx != UNASSIGNED_INDEX) {
  1709. pmhctl->llist_notify[ret_idx].waiting = FALSE;
  1710. pmhctl->llist_notify[ret_idx].done_cb = NULL;
  1711. pmhctl->llist_notify[ret_idx].in_use = TRUE;
  1712. pmhctl->llist_notify[ret_idx].next_idx = UNASSIGNED_INDEX;
  1713. }
  1714. return ret_idx;
  1715. }
  1716. uint16 mddi_get_reg_read_llist_item(mddi_host_type host_idx, boolean wait)
  1717. {
  1718. #ifdef FEATURE_MDDI_DISABLE_REVERSE
  1719. MDDI_MSG_CRIT("No reverse link available\n");
  1720. (void)wait;
  1721. return FALSE;
  1722. #else
  1723. unsigned long flags;
  1724. uint16 ret_idx;
  1725. boolean error = FALSE;
  1726. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  1727. spin_lock_irqsave(&mddi_host_spin_lock, flags);
  1728. if (pmhctl->llist_info.reg_read_idx != UNASSIGNED_INDEX) {
  1729. /* need to block here or is this an error condition? */
  1730. error = TRUE;
  1731. ret_idx = UNASSIGNED_INDEX;
  1732. }
  1733. spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
  1734. if (!error) {
  1735. ret_idx = pmhctl->llist_info.reg_read_idx =
  1736. mddi_get_next_free_llist_item(host_idx, wait);
  1737. /* clear the reg_read_waiting flag */
  1738. pmhctl->llist_info.reg_read_waiting = FALSE;
  1739. }
  1740. if (error)
  1741. MDDI_MSG_ERR("***** Reg read still in progress! ****\n");
  1742. return ret_idx;
  1743. #endif
  1744. }
  1745. void mddi_queue_forward_packets(uint16 first_llist_idx,
  1746. uint16 last_llist_idx,
  1747. boolean wait,
  1748. mddi_llist_done_cb_type llist_done_cb,
  1749. mddi_host_type host_idx)
  1750. {
  1751. unsigned long flags;
  1752. mddi_linked_list_type *llist;
  1753. mddi_linked_list_type *llist_dma;
  1754. mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
  1755. if ((first_llist_idx >= UNASSIGNED_INDEX) ||
  1756. (last_llist_idx >= UNASSIGNED_INDEX)) {
  1757. MDDI_MSG_ERR("MDDI queueing invalid linked list\n");
  1758. return;
  1759. }
  1760. if (pmhctl->link_state == MDDI_LINK_DISABLED)
  1761. MDDI_MSG_CRIT("MDDI host powered down!\n");
  1762. llist = pmhctl->llist_ptr;
  1763. llist_dma = pmhctl->llist_dma_ptr;
  1764. /* clean cache so MDDI host can read data */
  1765. memory_barrier();
  1766. pmhctl->llist_notify[last_llist_idx].waiting = wait;
  1767. if (wait)
  1768. INIT_COMPLETION(pmhctl->llist_notify[last_llist_idx].done_comp);
  1769. pmhctl->llist_notify[last_llist_idx].done_cb = llist_done_cb;
  1770. spin_lock_irqsave(&mddi_host_spin_lock, flags);
  1771. if ((pmhctl->llist_info.transmitting_start_idx == UNASSIGNED_INDEX) &&
  1772. (pmhctl->llist_info.waiting_start_idx == UNASSIGNED_INDEX) &&
  1773. (pmhctl->rev_state == MDDI_REV_IDLE)) {
  1774. /* no packets are currently transmitting */
  1775. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  1776. if (first_llist_idx == pmhctl->llist_info.reg_read_idx) {
  1777. /* This is the special case where the packet is a register read. */
  1778. pmhctl->rev_state = MDDI_REV_REG_READ_ISSUED;
  1779. mddi_reg_read_retry = 0;
  1780. /* mddi_rev_reg_read_attempt = 1; */
  1781. }
  1782. #endif
  1783. /* assign transmitting index values */
  1784. pmhctl->llist_info.transmitting_start_idx = first_llist_idx;
  1785. pmhctl->llist_info.transmitting_end_idx = last_llist_idx;
  1786. /* turn on clock(s), if they have been disabled */
  1787. mddi_host_enable_hclk();
  1788. mddi_host_enable_io_clock();
  1789. pmhctl->int_type.llist_ptr_write_1++;
  1790. /* Write to primary pointer register */
  1791. dma_coherent_pre_ops();
  1792. mddi_host_reg_out(PRI_PTR, &llist_dma[first_llist_idx]);
  1793. /* enable interrupt when complete */
  1794. mddi_host_reg_outm(INTEN, MDDI_INT_PRI_LINK_LIST_DONE,
  1795. MDDI_INT_PRI_LINK_LIST_DONE);
  1796. } else if (pmhctl->llist_info.waiting_start_idx == UNASSIGNED_INDEX) {
  1797. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  1798. if (first_llist_idx == pmhctl->llist_info.reg_read_idx) {
  1799. /*
  1800. * we have a register read to send but need to wait
  1801. * for current reverse activity to end or there are
  1802. * packets currently transmitting
  1803. */
  1804. /* mddi_rev_reg_read_attempt = 0; */
  1805. pmhctl->llist_info.reg_read_waiting = TRUE;
  1806. }
  1807. #endif
  1808. /* assign waiting index values */
  1809. pmhctl->llist_info.waiting_start_idx = first_llist_idx;
  1810. pmhctl->llist_info.waiting_end_idx = last_llist_idx;
  1811. } else {
  1812. uint16 prev_end_idx = pmhctl->llist_info.waiting_end_idx;
  1813. #ifndef FEATURE_MDDI_DISABLE_REVERSE
  1814. if (first_llist_idx == pmhctl->llist_info.reg_read_idx) {
  1815. /*
  1816. * we have a register read to send but need to wait
  1817. * for current reverse activity to end or there are
  1818. * packets currently transmitting
  1819. */
  1820. /* mddi_rev_reg_read_attempt = 0; */
  1821. pmhctl->llist_info.reg_read_waiting = TRUE;
  1822. }
  1823. #endif
  1824. llist = pmhctl->llist_ptr;
  1825. /* clear end flag in previous last packet */
  1826. llist[prev_end_idx].link_controller_flags = 0;
  1827. pmhctl->llist_notify[prev_end_idx].next_idx = first_llist_idx;
  1828. /* set the next_packet_pointer of the previous last packet */
  1829. llist[prev_end_idx].next_packet_pointer =
  1830. (void *)(&llist_dma[first_llist_idx]);
  1831. /* clean cache so MDDI host can read data */
  1832. memory_barrier();
  1833. /* assign new waiting last index value */
  1834. pmhctl->llist_info.waiting_end_idx = last_llist_idx;
  1835. }
  1836. spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
  1837. }
  1838. void mddi_host_write_pix_attr_reg(uint32 value)
  1839. {
  1840. (void)value;
  1841. }
  1842. void mddi_queue_reverse_encapsulation(boolean wait)
  1843. {
  1844. #ifdef FEATURE_MDDI_DISABLE_REVERSE
  1845. MDDI_MSG_CRIT("No reverse link available\n");
  1846. (void)wait;
  1847. #else
  1848. unsigned long flags;
  1849. boolean error = FALSE;
  1850. mddi_host_type host_idx = MDDI_HOST_PRIM;
  1851. mddi_host_cntl_type *pmhctl = &(mhctl[MDDI_HOST_PRIM]);
  1852. spin_lock_irqsave(&mddi_host_spin_lock, flags);
  1853. /* turn on clock(s), if they have been disabled */
  1854. mddi_host_enable_hclk();
  1855. mddi_host_enable_io_clock();
  1856. if (wait) {
  1857. if (!mddi_rev_user.waiting) {
  1858. mddi_rev_user.waiting = TRUE;
  1859. INIT_COMPLETION(mddi_rev_user.done_comp);
  1860. } else
  1861. error = TRUE;
  1862. }
  1863. mddi_rev_encap_user_request = TRUE;
  1864. if (pmhctl->rev_state == MDDI_REV_IDLE) {
  1865. /* attempt to send the reverse encapsulation now */
  1866. mddi_host_type orig_host_idx = mddi_curr_host;
  1867. mddi_curr_host = host_idx;
  1868. mddi_issue_reverse_encapsulation();
  1869. mddi_curr_host = orig_host_idx;
  1870. }
  1871. spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
  1872. if (error) {
  1873. MDDI_MSG_ERR("Reverse Encap request already in progress\n");
  1874. } else if (wait)
  1875. wait_for_completion_killable(&(mddi_rev_user.done_comp));
  1876. #endif
  1877. }
  1878. /* ISR to be executed */
  1879. boolean mddi_set_rev_handler(mddi_rev_handler_type handler, uint16 pkt_type)
  1880. {
  1881. #ifdef FEATURE_MDDI_DISABLE_REVERSE
  1882. MDDI_MSG_CRIT("No reverse link available\n");
  1883. (void)handler;
  1884. (void)pkt_type;
  1885. return (FALSE);
  1886. #else
  1887. unsigned long flags;
  1888. uint16 hdlr;
  1889. boolean handler_set = FALSE;
  1890. boolean overwrite = FALSE;
  1891. mddi_host_type host_idx = MDDI_HOST_PRIM;
  1892. mddi_host_cntl_type *pmhctl = &(mhctl[MDDI_HOST_PRIM]);
  1893. /* Disable interrupts */
  1894. spin_lock_irqsave(&mddi_host_spin_lock, flags);
  1895. for (hdlr = 0; hdlr < MAX_MDDI_REV_HANDLERS; hdlr++) {
  1896. if (mddi_rev_pkt_handler[hdlr].pkt_type == pkt_type) {
  1897. mddi_rev_pkt_handler[hdlr].handler = handler;
  1898. if (handler == NULL) {
  1899. /* clearing handler from table */
  1900. mddi_rev_pkt_handler[hdlr].pkt_type =
  1901. INVALID_PKT_TYPE;
  1902. handler_set = TRUE;
  1903. if (pkt_type == 0x10) { /* video stream packet */
  1904. /* ensure HCLK on to MDDI host core before register write */
  1905. mddi_host_enable_hclk();
  1906. /* No longer getting video, so reset rev encap size to default */
  1907. pmhctl->rev_pkt_size =
  1908. MDDI_DEFAULT_REV_PKT_SIZE;
  1909. mddi_host_reg_out(REV_ENCAP_SZ,
  1910. pmhctl->rev_pkt_size);
  1911. }
  1912. } else {
  1913. /* already a handler for this packet */
  1914. overwrite = TRUE;
  1915. }
  1916. break;
  1917. }
  1918. }
  1919. if ((hdlr >= MAX_MDDI_REV_HANDLERS) && (handler != NULL)) {
  1920. /* assigning new handler */
  1921. for (hdlr = 0; hdlr < MAX_MDDI_REV_HANDLERS; hdlr++) {
  1922. if (mddi_rev_pkt_handler[hdlr].pkt_type ==
  1923. INVALID_PKT_TYPE) {
  1924. if ((pkt_type == 0x10) && /* video stream packet */
  1925. (pmhctl->rev_pkt_size <
  1926. MDDI_VIDEO_REV_PKT_SIZE)) {
  1927. /* ensure HCLK on to MDDI host core before register write */
  1928. mddi_host_enable_hclk();
  1929. /* Increase Rev Encap Size */
  1930. pmhctl->rev_pkt_size =
  1931. MDDI_VIDEO_REV_PKT_SIZE;
  1932. mddi_host_reg_out(REV_ENCAP_SZ,
  1933. pmhctl->rev_pkt_size);
  1934. }
  1935. mddi_rev_pkt_handler[hdlr].handler = handler;
  1936. mddi_rev_pkt_handler[hdlr].pkt_type = pkt_type;
  1937. handler_set = TRUE;
  1938. break;
  1939. }
  1940. }
  1941. }
  1942. /* Restore interrupts */
  1943. spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
  1944. if (overwrite)
  1945. MDDI_MSG_ERR("Overwriting previous rev packet handler\n");
  1946. return handler_set;
  1947. #endif
  1948. } /* mddi_set_rev_handler */
  1949. void mddi_host_disable_hibernation(boolean disable)
  1950. {
  1951. mddi_host_type host_idx = MDDI_HOST_PRIM;
  1952. mddi_host_cntl_type *pmhctl = &(mhctl[MDDI_HOST_PRIM]);
  1953. if (disable) {
  1954. pmhctl->disable_hibernation = TRUE;
  1955. /* hibernation will be turned off by isr next time it is entered */
  1956. } else {
  1957. if (pmhctl->disable_hibernation) {
  1958. unsigned long flags;
  1959. spin_lock_irqsave(&mddi_host_spin_lock, flags);
  1960. if (!MDDI_HOST_IS_HCLK_ON)
  1961. MDDI_HOST_ENABLE_HCLK;
  1962. mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE | 1);
  1963. spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
  1964. pmhctl->disable_hibernation = FALSE;
  1965. }
  1966. }
  1967. }
  1968. void mddi_mhctl_remove(mddi_host_type host_idx)
  1969. {
  1970. mddi_host_cntl_type *pmhctl;
  1971. pmhctl = &(mhctl[host_idx]);
  1972. dma_free_coherent(NULL, MDDI_LLIST_POOL_SIZE, (void *)pmhctl->llist_ptr,
  1973. pmhctl->llist_dma_addr);
  1974. dma_free_coherent(NULL, MDDI_MAX_REV_DATA_SIZE,
  1975. (void *)pmhctl->rev_data_buf,
  1976. pmhctl->rev_data_dma_addr);
  1977. }